include/opcode/ChangeLog

   1 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
   2
   3         * mips.h (INSN_ISA*): Redefine certain values as an
   4         enumeration.  Update comments.
   5         (mips_isa_table): New.
   6         (ISA_MIPS*): Redefine to match enumeration.
   7         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
   8         values.
   9
  10 2007-08-08  Ben Elliston  <bje@au.ibm.com>
  11
  12         * ppc.h (PPC_OPCODE_PPCPS): New.
  13
  14 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
  15
  16         * m68k.h: Document j K & E.
  17
  18 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  19
  20         * cr16.h: New file for CR16 target.
  21
  22 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
  23
  24         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
  25
  26 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
  27
  28         * m68k.h (mcfisa_c): New.
  29         (mcfusp, mcf_mask): Adjust.
  30
  31 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
  32
  33         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
  34         (num_powerpc_operands): Declare.
  35         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  36         (PPC_OPERAND_PLUS1): Define.
  37
  38 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  39
  40         * i386.h (REX_MODE64): Renamed to ...
  41         (REX_W): This.
  42         (REX_EXTX): Renamed to ...
  43         (REX_R): This.
  44         (REX_EXTY): Renamed to ...
  45         (REX_X): This.
  46         (REX_EXTZ): Renamed to ...
  47         (REX_B): This.
  48
  49 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * i386.h: Add entries from config/tc-i386.h and move tables
  52         to opcodes/i386-opc.h.
  53
  54 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         * i386.h (FloatDR): Removed.
  57         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  58
  59 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  60
  61         * spu-insns.h: Add soma double-float insns.
  62
  63 2007-02-20  Thiemo Seufer  <ths@mips.com>
  64             Chao-Ying Fu  <fu@mips.com>
  65
  66         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  67         (INSN_DSPR2): Add flag for DSP R2 instructions.
  68         (M_BALIGN): New macro.
  69
  70 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  71
  72         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  73         and Seg3ShortFrom with Shortform.
  74
  75 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         PR gas/4027
  78         * i386.h (i386_optab): Put the real "test" before the pseudo
  79         one.
  80
  81 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  82
  83         * m68k.h (m68010up): OR fido_a.
  84
  85 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  86
  87         * m68k.h (fido_a): New.
  88
  89 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  90
  91         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
  92         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
  93         values.
  94
  95 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  96
  97         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  98
  99 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 100
 101         * score-inst.h (enum score_insn_type): Add Insn_internal.
 102
 103 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 104             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 105             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 106             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 107             Alan Modra  <amodra@bigpond.net.au>
 108
 109         * spu-insns.h: New file.
 110         * spu.h: New file.
 111
 112 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 113
 114         * ppc.h (PPC_OPCODE_CELL): Define.
 115
 116 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 117
 118         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 119         in amdfam10 architecture.
 120
 121 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 122
 123         * i386.h: Replace CpuMNI with CpuSSSE3.
 124
 125 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 126             Joseph Myers  <joseph@codesourcery.com>
 127             Ian Lance Taylor  <ian@wasabisystems.com>
 128             Ben Elliston  <bje@wasabisystems.com>
 129
 130         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 131
 132 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 133
 134         * score-datadep.h: New file.
 135         * score-inst.h: New file.
 136
 137 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 140         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 141         movdq2q and movq2dq.
 142
 143 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 144            Michael Meissner             <michael.meissner@amd.com>
 145
 146         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 147
 148 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 149
 150         * i386.h (i386_optab): Add "nop" with memory reference.
 151
 152 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 153
 154         * i386.h (i386_optab): Update comment for 64bit NOP.
 155
 156 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 157             Anton Blanchard  <anton@samba.org>
 158
 159         * ppc.h (PPC_OPCODE_POWER6): Define.
 160         Adjust whitespace.
 161
 162 2006-06-05  Thiemo Seufer  <ths@mips.com>
 163
 164         * mips.h: Improve description of MT flags.
 165
 166 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 167
 168         * m68k.h (mcf_mask): Define.
 169
 170 2006-05-05  Thiemo Seufer  <ths@mips.com>
 171             David Ung  <davidu@mips.com>
 172
 173         * mips.h (enum): Add macro M_CACHE_AB.
 174
 175 2006-05-04  Thiemo Seufer  <ths@mips.com>
 176             Nigel Stephens  <nigel@mips.com>
 177             David Ung  <davidu@mips.com>
 178
 179         * mips.h: Add INSN_SMARTMIPS define.
 180
 181 2006-04-30  Thiemo Seufer  <ths@mips.com>
 182             David Ung  <davidu@mips.com>
 183
 184         * mips.h: Defines udi bits and masks.  Add description of
 185         characters which may appear in the args field of udi
 186         instructions.
 187
 188 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 189
 190         * mips.h: Improve comments describing the bitfield instruction
 191         fields.
 192
 193 2006-04-26  Julian Brown  <julian@codesourcery.com>
 194
 195         * arm.h (FPU_VFP_EXT_V3): Define constant.
 196         (FPU_NEON_EXT_V1): Likewise.
 197         (FPU_VFP_HARD): Update.
 198         (FPU_VFP_V3): Define macro.
 199         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 200
 201 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 202
 203         * avr.h (AVR_ISA_PWMx): New.
 204
 205 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 206
 207         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 208         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 209         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 210         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 211         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 212
 213 2006-03-10  Paul Brook  <paul@codesourcery.com>
 214
 215         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 216
 217 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 218
 219         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 220         first.  Correct mask of bb "B" opcode.
 221
 222 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 223
 224         * i386.h (i386_optab): Support Intel Merom New Instructions.
 225
 226 2006-02-24  Paul Brook  <paul@codesourcery.com>
 227
 228         * arm.h: Add V7 feature bits.
 229
 230 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 233
 234 2006-01-31  Paul Brook  <paul@codesourcery.com>
 235         Richard Earnshaw <rearnsha@arm.com>
 236
 237         * arm.h: Use ARM_CPU_FEATURE.
 238         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 239         (arm_feature_set): Change to a structure.
 240         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 241         ARM_FEATURE): New macros.
 242
 243 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 244
 245         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 246         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 247         (ADD_PC_INCR_OPCODE): Don't define.
 248
 249 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         PR gas/1874
 252         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 253
 254 2005-11-14  David Ung  <davidu@mips.com>
 255
 256         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 257         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 258         save/restore encoding of the args field.
 259
 260 2005-10-28  Dave Brolley  <brolley@redhat.com>
 261
 262         Contribute the following changes:
 263         2005-02-16  Dave Brolley  <brolley@redhat.com>
 264
 265         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 266         cgen_isa_mask_* to cgen_bitset_*.
 267         * cgen.h: Likewise.
 268
 269         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 270
 271         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 272         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 273         (CGEN_CPU_TABLE): Make isas a ponter.
 274
 275         2003-09-29  Dave Brolley  <brolley@redhat.com>
 276
 277         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 278         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 279         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 280
 281         2002-12-13  Dave Brolley  <brolley@redhat.com>
 282
 283         * cgen.h (symcat.h): #include it.
 284         (cgen-bitset.h): #include it.
 285         (CGEN_ATTR_VALUE_TYPE): Now a union.
 286         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 287         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 288         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 289         * cgen-bitset.h: New file.
 290
 291 2005-09-30  Catherine Moore  <clm@cm00re.com>
 292
 293         * bfin.h: New file.
 294
 295 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 296
 297         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 298         indirect operands.
 299
 300 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 301
 302         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 303         Add FLAG_STRICT to pa10 ftest opcode.
 304
 305 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 306
 307         * hppa.h (pa_opcodes): Remove lha entries.
 308
 309 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 310
 311         * hppa.h (FLAG_STRICT): Revise comment.
 312         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 313         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 314         entries for "fdc".
 315
 316 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 317
 318         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 319
 320 2005-09-06  Chao-ying Fu  <fu@mips.com>
 321
 322         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 323         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 324         define.
 325         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 326         (INSN_ASE_MASK): Update to include INSN_MT.
 327         (INSN_MT): New define for MT ASE.
 328
 329 2005-08-25  Chao-ying Fu  <fu@mips.com>
 330
 331         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 332         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 333         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 334         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 335         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 336         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 337         instructions.
 338         (INSN_DSP): New define for DSP ASE.
 339
 340 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 341
 342         * a29k.h: Delete.
 343
 344 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 345
 346         * ppc.h (PPC_OPCODE_E300): Define.
 347
 348 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 349
 350         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 351
 352 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 353
 354         PR gas/336
 355         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 356         and pitlb.
 357
 358 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 359
 360         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 361         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 362         Add movq-s as 64-bit variants of movd-s.
 363
 364 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 365
 366         * hppa.h: Fix punctuation in comment.
 367
 368         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 369         implicit space-register addressing.  Set space-register bits on opcodes
 370         using implicit space-register addressing.  Add various missing pa20
 371         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 372         space-register addressing.  Use "fE" instead of "fe" in various
 373         fstw opcodes.
 374
 375 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 376
 377         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 378
 379 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 380
 381         * i386.h (i386_optab): Support Intel VMX Instructions.
 382
 383 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 384
 385         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 386
 387 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 388
 389         * i386.h (i386_optab): Add new insns.
 390
 391 2005-07-01  Nick Clifton  <nickc@redhat.com>
 392
 393         * sparc.h: Add typedefs to structure declarations.
 394
 395 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         PR 1013
 398         * i386.h (i386_optab): Update comments for 64bit addressing on
 399         mov. Allow 64bit addressing for mov and movq.
 400
 401 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 402
 403         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 404         respectively, in various floating-point load and store patterns.
 405
 406 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 407
 408         * hppa.h (FLAG_STRICT): Correct comment.
 409         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 410         PA 2.0 mneumonics when equivalent.  Entries with cache control
 411         completers now require PA 1.1.  Adjust whitespace.
 412
 413 2005-05-19  Anton Blanchard  <anton@samba.org>
 414
 415         * ppc.h (PPC_OPCODE_POWER5): Define.
 416
 417 2005-05-10  Nick Clifton  <nickc@redhat.com>
 418
 419         * Update the address and phone number of the FSF organization in
 420         the GPL notices in the following files:
 421         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 422         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 423         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 424         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 425         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 426         tic54x.h, tic80.h, v850.h, vax.h
 427
 428 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 429
 430         * i386.h (i386_optab): Add ht and hnt.
 431
 432 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 433
 434         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 435         Add xcrypt-ctr.  Provide aliases without hyphens.
 436
 437 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         Moved from ../ChangeLog
 440
 441         2005-04-12  Paul Brook  <paul@codesourcery.com>
 442         * m88k.h: Rename psr macros to avoid conflicts.
 443
 444         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 445         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 446         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 447         and ARM_ARCH_V6ZKT2.
 448
 449         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 450         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 451         Remove redundant instruction types.
 452         (struct argument): X_op - new field.
 453         (struct cst4_entry): Remove.
 454         (no_op_insn): Declare.
 455
 456         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 457         * crx.h (enum argtype): Rename types, remove unused types.
 458
 459         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 460         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 461         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 462         (enum operand_type): Rearrange operands, edit comments.
 463         replace us<N> with ui<N> for unsigned immediate.
 464         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 465         displacements (respectively).
 466         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 467         (instruction type): Add NO_TYPE_INS.
 468         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 469         (operand_entry): New field - 'flags'.
 470         (operand flags): New.
 471
 472         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 473         * crx.h (operand_type): Remove redundant types i3, i4,
 474         i5, i8, i12.
 475         Add new unsigned immediate types us3, us4, us5, us16.
 476
 477 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 478
 479         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 480         adjust them accordingly.
 481
 482 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 483
 484         * i386.h (i386_optab): Add rdtscp.
 485
 486 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 489         between memory and segment register. Allow movq for moving between
 490         general-purpose register and segment register.
 491
 492 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 493
 494         PR gas/707
 495         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 496         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 497         fnstsw.
 498
 499 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 500
 501         * m68k.h (m68008, m68ec030, m68882): Remove.
 502         (m68k_mask): New.
 503         (cpu_m68k, cpu_cf): New.
 504         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 505         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 506
 507 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 508
 509         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 510         * cgen.h (enum cgen_parse_operand_type): Add
 511         CGEN_PARSE_OPERAND_SYMBOLIC.
 512
 513 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 514
 515         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 516         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 517         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 518
 519 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 520
 521         * mips.h (struct mips_opcode): Add new pinfo2 member.
 522         (INSN_ALIAS): New define for opcode table entries that are
 523         specific instances of another entry, such as 'move' for an 'or'
 524         with a zero operand.
 525         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 526         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 527
 528 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 529
 530         * mips.h (CPU_RM9000): Define.
 531         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 532
 533 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 534
 535         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 536         to/from test registers are illegal in 64-bit mode. Add missing
 537         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 538         (previously one had to explicitly encode a rex64 prefix). Re-enable
 539         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 540         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 541
 542 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 543
 544         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 545         available only with SSE2. Change the MMX additions introduced by SSE
 546         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 547         instructions by their now designated identifier (since combining i686
 548         and 3DNow! does not really imply 3DNow!A).
 549
 550 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 551
 552         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 553         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 554
 555 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 556             Vineet Sharma      <vineets@noida.hcltech.com>
 557
 558         * maxq.h: New file: Disassembly information for the maxq port.
 559
 560 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 561
 562         * i386.h (i386_optab): Put back "movzb".
 563
 564 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 565
 566         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 567         comments.  Remove member cris_ver_sim.  Add members
 568         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 569         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 570         (struct cris_support_reg, struct cris_cond15): New types.
 571         (cris_conds15): Declare.
 572         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 573         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 574         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 575         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 576         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 577         SIZE_FIELD_UNSIGNED.
 578
 579 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 580
 581         * i386.h (sldx_Suf): Remove.
 582         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 583         (q_FP): Define, implying no REX64.
 584         (x_FP, sl_FP): Imply FloatMF.
 585         (i386_optab): Split reg and mem forms of moving from segment registers
 586         so that the memory forms can ignore the 16-/32-bit operand size
 587         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 588         all non-floating-point instructions. Unite 32- and 64-bit forms of
 589         movsx, movzx, and movd. Adjust floating point operations for the above
 590         changes to the *FP macros. Add DefaultSize to floating point control
 591         insns operating on larger memory ranges. Remove left over comments
 592         hinting at certain insns being Intel-syntax ones where the ones
 593         actually meant are already gone.
 594
 595 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 596
 597         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 598         instruction type.
 599
 600 2004-09-30  Paul Brook  <paul@codesourcery.com>
 601
 602         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 603         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 604
 605 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 606
 607         * avr.h: Add support for
 608         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 609
 610 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 611
 612         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 613
 614 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 615
 616         * msp430.h (msp430_opc): Add new instructions.
 617         (msp430_rcodes): Declare new instructions.
 618         (msp430_hcodes): Likewise..
 619
 620 2004-08-13  Nick Clifton  <nickc@redhat.com>
 621
 622         PR/301
 623         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 624         processors.
 625
 626 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 627
 628         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 629
 630 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 631
 632         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 633
 634 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 635
 636         * i386.h: Adjust instruction descriptions to better match the
 637         specification.
 638
 639 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 640
 641         * arm.h: Remove all old content.  Replace with architecture defines
 642         from gas/config/tc-arm.c.
 643
 644 2004-07-09  Andreas Schwab  <schwab@suse.de>
 645
 646         * m68k.h: Fix comment.
 647
 648 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 649
 650         * crx.h: New file.
 651
 652 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 653
 654         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 655
 656 2004-05-24  Peter Barada  <peter@the-baradas.com>
 657
 658         * m68k.h: Add 'size' to m68k_opcode.
 659
 660 2004-05-05  Peter Barada  <peter@the-baradas.com>
 661
 662         * m68k.h: Switch from ColdFire chip name to core variant.
 663
 664 2004-04-22  Peter Barada  <peter@the-baradas.com>
 665
 666         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 667         descriptions for new EMAC cases.
 668         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 669         handle Motorola MAC syntax.
 670         Allow disassembly of ColdFire V4e object files.
 671
 672 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 673
 674         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 675
 676 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 677
 678         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 679
 680 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 681
 682         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 683
 684 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 685
 686         * i386.h (i386_optab): Added xstore/xcrypt insns.
 687
 688 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 689
 690         * h8300.h (32bit ldc/stc): Add relaxing support.
 691
 692 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 693
 694         * h8300.h (BITOP): Pass MEMRELAX flag.
 695
 696 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 697
 698         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 699         except for the H8S.
 700
 701 For older changes see ChangeLog-9103
 702 \f
 703 Local Variables:
 704 mode: change-log
 705 left-margin: 8
 706 fill-column: 74
 707 version-control: never
 708 End: