include/opcode/ChangeLog

   1 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
   2
   3         * mips.h (INSN_XLR): Define.
   4         (INSN_CHIP_MASK): Update.
   5         (CPU_XLR): Define.
   6         (OPCODE_IS_MEMBER): Update.
   7         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
   8
   9 2009-01-28  Doug Evans  <dje@google.com>
  10
  11         * opcode/i386.h: Add multiple inclusion protection.
  12         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  13         (EDI_REG_NUM): New macros.
  14         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  15         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  16         (REX_PREFIX_P): New macro.
  17
  18 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  19
  20         * ppc.h (struct powerpc_opcode): New field "deprecated".
  21         (PPC_OPCODE_NOPOWER4): Delete.
  22
  23 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  24
  25         * mips.h: Define CPU_R14000, CPU_R16000.
  26         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  27
  28 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  29
  30         * arm.h (FPU_NEON_FP16): New.
  31         (FPU_ARCH_NEON_FP16): New.
  32
  33 2008-11-06  Chao-ying Fu  <fu@mips.com>
  34
  35         * mips.h: Doucument '1' for 5-bit sync type.
  36
  37 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  40         IA64_RS_CR.
  41
  42 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
  43
  44         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
  45
  46 2008-07-30  Michael J. Eager  <eager@eagercon.com>
  47
  48         * ppc.h (PPC_OPCODE_405): Define.
  49         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
  50
  51 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
  52
  53         * ppc.h (ppc_cpu_t): New typedef.
  54         (struct powerpc_opcode <flags>): Use it.
  55         (struct powerpc_operand <insert, extract>): Likewise.
  56         (struct powerpc_macro <flags>): Likewise.
  57
  58 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
  59
  60         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
  61         Update comment before MIPS16 field descriptors to mention MIPS16.
  62         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
  63         BBIT.
  64         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
  65         New bit masks and shift counts for cins and exts.
  66
  67         * mips.h: Document new field descriptors +Q.
  68         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
  69
  70 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
  71
  72         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
  73         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
  74
  75 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
  76
  77         * ppc.h: (PPC_OPCODE_E500MC): New.
  78
  79 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         * i386.h (MAX_OPERANDS): Set to 5.
  82         (MAX_MNEM_SIZE): Changed to 20.
  83
  84 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
  85
  86         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
  87
  88 2008-03-09  Paul Brook  <paul@codesourcery.com>
  89
  90         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
  91
  92 2008-03-04  Paul Brook  <paul@codesourcery.com>
  93
  94         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
  95         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
  96         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
  97
  98 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
  99             Nick Clifton  <nickc@redhat.com>
 100
 101         PR 3134
 102         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 103         with a 32-bit displacement but without the top bit of the 4th byte
 104         set.
 105
 106 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 107
 108         * cr16.h (cr16_num_optab): Declared.
 109
 110 2008-02-14  Hakan Ardo  <hakan@debian.org>
 111
 112         PR gas/2626
 113         * avr.h (AVR_ISA_2xxe): Define.
 114
 115 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 116
 117         * mips.h: Update copyright.
 118         (INSN_CHIP_MASK): New macro.
 119         (INSN_OCTEON): New macro.
 120         (CPU_OCTEON): New macro.
 121         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 122
 123 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 124
 125         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 126
 127 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 128
 129         * avr.h (AVR_ISA_USB162): Add new opcode set.
 130         (AVR_ISA_AVR3): Likewise.
 131
 132 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 133
 134         * mips.h (INSN_LOONGSON_2E): New.
 135         (INSN_LOONGSON_2F): New.
 136         (CPU_LOONGSON_2E): New.
 137         (CPU_LOONGSON_2F): New.
 138         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 139
 140 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 141
 142         * mips.h (INSN_ISA*): Redefine certain values as an
 143         enumeration.  Update comments.
 144         (mips_isa_table): New.
 145         (ISA_MIPS*): Redefine to match enumeration.
 146         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 147         values.
 148
 149 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 150
 151         * ppc.h (PPC_OPCODE_PPCPS): New.
 152
 153 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 154
 155         * m68k.h: Document j K & E.
 156
 157 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 158
 159         * cr16.h: New file for CR16 target.
 160
 161 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 162
 163         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 164
 165 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 166
 167         * m68k.h (mcfisa_c): New.
 168         (mcfusp, mcf_mask): Adjust.
 169
 170 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 171
 172         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 173         (num_powerpc_operands): Declare.
 174         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 175         (PPC_OPERAND_PLUS1): Define.
 176
 177 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 178
 179         * i386.h (REX_MODE64): Renamed to ...
 180         (REX_W): This.
 181         (REX_EXTX): Renamed to ...
 182         (REX_R): This.
 183         (REX_EXTY): Renamed to ...
 184         (REX_X): This.
 185         (REX_EXTZ): Renamed to ...
 186         (REX_B): This.
 187
 188 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 189
 190         * i386.h: Add entries from config/tc-i386.h and move tables
 191         to opcodes/i386-opc.h.
 192
 193 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 194
 195         * i386.h (FloatDR): Removed.
 196         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 197
 198 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 199
 200         * spu-insns.h: Add soma double-float insns.
 201
 202 2007-02-20  Thiemo Seufer  <ths@mips.com>
 203             Chao-Ying Fu  <fu@mips.com>
 204
 205         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 206         (INSN_DSPR2): Add flag for DSP R2 instructions.
 207         (M_BALIGN): New macro.
 208
 209 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 210
 211         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 212         and Seg3ShortFrom with Shortform.
 213
 214 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         PR gas/4027
 217         * i386.h (i386_optab): Put the real "test" before the pseudo
 218         one.
 219
 220 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 221
 222         * m68k.h (m68010up): OR fido_a.
 223
 224 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 225
 226         * m68k.h (fido_a): New.
 227
 228 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 229
 230         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 231         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 232         values.
 233
 234 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 237
 238 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 239
 240         * score-inst.h (enum score_insn_type): Add Insn_internal.
 241
 242 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 243             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 244             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 245             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 246             Alan Modra  <amodra@bigpond.net.au>
 247
 248         * spu-insns.h: New file.
 249         * spu.h: New file.
 250
 251 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 252
 253         * ppc.h (PPC_OPCODE_CELL): Define.
 254
 255 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 256
 257         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 258         in amdfam10 architecture.
 259
 260 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 261
 262         * i386.h: Replace CpuMNI with CpuSSSE3.
 263
 264 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 265             Joseph Myers  <joseph@codesourcery.com>
 266             Ian Lance Taylor  <ian@wasabisystems.com>
 267             Ben Elliston  <bje@wasabisystems.com>
 268
 269         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 270
 271 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 272
 273         * score-datadep.h: New file.
 274         * score-inst.h: New file.
 275
 276 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 279         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 280         movdq2q and movq2dq.
 281
 282 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 283            Michael Meissner             <michael.meissner@amd.com>
 284
 285         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 286
 287 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 288
 289         * i386.h (i386_optab): Add "nop" with memory reference.
 290
 291 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 292
 293         * i386.h (i386_optab): Update comment for 64bit NOP.
 294
 295 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 296             Anton Blanchard  <anton@samba.org>
 297
 298         * ppc.h (PPC_OPCODE_POWER6): Define.
 299         Adjust whitespace.
 300
 301 2006-06-05  Thiemo Seufer  <ths@mips.com>
 302
 303         * mips.h: Improve description of MT flags.
 304
 305 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 306
 307         * m68k.h (mcf_mask): Define.
 308
 309 2006-05-05  Thiemo Seufer  <ths@mips.com>
 310             David Ung  <davidu@mips.com>
 311
 312         * mips.h (enum): Add macro M_CACHE_AB.
 313
 314 2006-05-04  Thiemo Seufer  <ths@mips.com>
 315             Nigel Stephens  <nigel@mips.com>
 316             David Ung  <davidu@mips.com>
 317
 318         * mips.h: Add INSN_SMARTMIPS define.
 319
 320 2006-04-30  Thiemo Seufer  <ths@mips.com>
 321             David Ung  <davidu@mips.com>
 322
 323         * mips.h: Defines udi bits and masks.  Add description of
 324         characters which may appear in the args field of udi
 325         instructions.
 326
 327 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 328
 329         * mips.h: Improve comments describing the bitfield instruction
 330         fields.
 331
 332 2006-04-26  Julian Brown  <julian@codesourcery.com>
 333
 334         * arm.h (FPU_VFP_EXT_V3): Define constant.
 335         (FPU_NEON_EXT_V1): Likewise.
 336         (FPU_VFP_HARD): Update.
 337         (FPU_VFP_V3): Define macro.
 338         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 339
 340 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 341
 342         * avr.h (AVR_ISA_PWMx): New.
 343
 344 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 345
 346         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 347         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 348         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 349         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 350         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 351
 352 2006-03-10  Paul Brook  <paul@codesourcery.com>
 353
 354         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 355
 356 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 357
 358         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 359         first.  Correct mask of bb "B" opcode.
 360
 361 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 362
 363         * i386.h (i386_optab): Support Intel Merom New Instructions.
 364
 365 2006-02-24  Paul Brook  <paul@codesourcery.com>
 366
 367         * arm.h: Add V7 feature bits.
 368
 369 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 370
 371         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 372
 373 2006-01-31  Paul Brook  <paul@codesourcery.com>
 374         Richard Earnshaw <rearnsha@arm.com>
 375
 376         * arm.h: Use ARM_CPU_FEATURE.
 377         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 378         (arm_feature_set): Change to a structure.
 379         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 380         ARM_FEATURE): New macros.
 381
 382 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 383
 384         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 385         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 386         (ADD_PC_INCR_OPCODE): Don't define.
 387
 388 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 389
 390         PR gas/1874
 391         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 392
 393 2005-11-14  David Ung  <davidu@mips.com>
 394
 395         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 396         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 397         save/restore encoding of the args field.
 398
 399 2005-10-28  Dave Brolley  <brolley@redhat.com>
 400
 401         Contribute the following changes:
 402         2005-02-16  Dave Brolley  <brolley@redhat.com>
 403
 404         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 405         cgen_isa_mask_* to cgen_bitset_*.
 406         * cgen.h: Likewise.
 407
 408         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 409
 410         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 411         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 412         (CGEN_CPU_TABLE): Make isas a ponter.
 413
 414         2003-09-29  Dave Brolley  <brolley@redhat.com>
 415
 416         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 417         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 418         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 419
 420         2002-12-13  Dave Brolley  <brolley@redhat.com>
 421
 422         * cgen.h (symcat.h): #include it.
 423         (cgen-bitset.h): #include it.
 424         (CGEN_ATTR_VALUE_TYPE): Now a union.
 425         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 426         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 427         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 428         * cgen-bitset.h: New file.
 429
 430 2005-09-30  Catherine Moore  <clm@cm00re.com>
 431
 432         * bfin.h: New file.
 433
 434 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 435
 436         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 437         indirect operands.
 438
 439 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 440
 441         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 442         Add FLAG_STRICT to pa10 ftest opcode.
 443
 444 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 445
 446         * hppa.h (pa_opcodes): Remove lha entries.
 447
 448 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 449
 450         * hppa.h (FLAG_STRICT): Revise comment.
 451         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 452         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 453         entries for "fdc".
 454
 455 2005-09-30  Catherine Moore  <clm@cm00re.com>
 456
 457         * bfin.h: New file.
 458
 459 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 460
 461         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 462
 463 2005-09-06  Chao-ying Fu  <fu@mips.com>
 464
 465         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 466         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 467         define.
 468         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 469         (INSN_ASE_MASK): Update to include INSN_MT.
 470         (INSN_MT): New define for MT ASE.
 471
 472 2005-08-25  Chao-ying Fu  <fu@mips.com>
 473
 474         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 475         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 476         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 477         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 478         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 479         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 480         instructions.
 481         (INSN_DSP): New define for DSP ASE.
 482
 483 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 484
 485         * a29k.h: Delete.
 486
 487 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 488
 489         * ppc.h (PPC_OPCODE_E300): Define.
 490
 491 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 492
 493         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 494
 495 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 496
 497         PR gas/336
 498         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 499         and pitlb.
 500
 501 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 502
 503         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 504         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 505         Add movq-s as 64-bit variants of movd-s.
 506
 507 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 508
 509         * hppa.h: Fix punctuation in comment.
 510
 511         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 512         implicit space-register addressing.  Set space-register bits on opcodes
 513         using implicit space-register addressing.  Add various missing pa20
 514         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 515         space-register addressing.  Use "fE" instead of "fe" in various
 516         fstw opcodes.
 517
 518 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 519
 520         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 521
 522 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 523
 524         * i386.h (i386_optab): Support Intel VMX Instructions.
 525
 526 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 527
 528         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 529
 530 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 531
 532         * i386.h (i386_optab): Add new insns.
 533
 534 2005-07-01  Nick Clifton  <nickc@redhat.com>
 535
 536         * sparc.h: Add typedefs to structure declarations.
 537
 538 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         PR 1013
 541         * i386.h (i386_optab): Update comments for 64bit addressing on
 542         mov. Allow 64bit addressing for mov and movq.
 543
 544 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 545
 546         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 547         respectively, in various floating-point load and store patterns.
 548
 549 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 550
 551         * hppa.h (FLAG_STRICT): Correct comment.
 552         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 553         PA 2.0 mneumonics when equivalent.  Entries with cache control
 554         completers now require PA 1.1.  Adjust whitespace.
 555
 556 2005-05-19  Anton Blanchard  <anton@samba.org>
 557
 558         * ppc.h (PPC_OPCODE_POWER5): Define.
 559
 560 2005-05-10  Nick Clifton  <nickc@redhat.com>
 561
 562         * Update the address and phone number of the FSF organization in
 563         the GPL notices in the following files:
 564         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 565         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 566         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 567         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 568         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 569         tic54x.h, tic80.h, v850.h, vax.h
 570
 571 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 572
 573         * i386.h (i386_optab): Add ht and hnt.
 574
 575 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 576
 577         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 578         Add xcrypt-ctr.  Provide aliases without hyphens.
 579
 580 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         Moved from ../ChangeLog
 583
 584         2005-04-12  Paul Brook  <paul@codesourcery.com>
 585         * m88k.h: Rename psr macros to avoid conflicts.
 586
 587         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 588         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 589         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 590         and ARM_ARCH_V6ZKT2.
 591
 592         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 593         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 594         Remove redundant instruction types.
 595         (struct argument): X_op - new field.
 596         (struct cst4_entry): Remove.
 597         (no_op_insn): Declare.
 598
 599         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 600         * crx.h (enum argtype): Rename types, remove unused types.
 601
 602         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 603         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 604         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 605         (enum operand_type): Rearrange operands, edit comments.
 606         replace us<N> with ui<N> for unsigned immediate.
 607         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 608         displacements (respectively).
 609         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 610         (instruction type): Add NO_TYPE_INS.
 611         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 612         (operand_entry): New field - 'flags'.
 613         (operand flags): New.
 614
 615         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 616         * crx.h (operand_type): Remove redundant types i3, i4,
 617         i5, i8, i12.
 618         Add new unsigned immediate types us3, us4, us5, us16.
 619
 620 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 621
 622         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 623         adjust them accordingly.
 624
 625 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 626
 627         * i386.h (i386_optab): Add rdtscp.
 628
 629 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 630
 631         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 632         between memory and segment register. Allow movq for moving between
 633         general-purpose register and segment register.
 634
 635 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 636
 637         PR gas/707
 638         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 639         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 640         fnstsw.
 641
 642 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 643
 644         * m68k.h (m68008, m68ec030, m68882): Remove.
 645         (m68k_mask): New.
 646         (cpu_m68k, cpu_cf): New.
 647         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 648         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 649
 650 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 651
 652         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 653         * cgen.h (enum cgen_parse_operand_type): Add
 654         CGEN_PARSE_OPERAND_SYMBOLIC.
 655
 656 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 657
 658         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 659         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 660         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 661
 662 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 663
 664         * mips.h (struct mips_opcode): Add new pinfo2 member.
 665         (INSN_ALIAS): New define for opcode table entries that are
 666         specific instances of another entry, such as 'move' for an 'or'
 667         with a zero operand.
 668         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 669         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 670
 671 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 672
 673         * mips.h (CPU_RM9000): Define.
 674         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 675
 676 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 677
 678         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 679         to/from test registers are illegal in 64-bit mode. Add missing
 680         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 681         (previously one had to explicitly encode a rex64 prefix). Re-enable
 682         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 683         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 684
 685 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 686
 687         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 688         available only with SSE2. Change the MMX additions introduced by SSE
 689         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 690         instructions by their now designated identifier (since combining i686
 691         and 3DNow! does not really imply 3DNow!A).
 692
 693 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 694
 695         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 696         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 697
 698 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 699             Vineet Sharma      <vineets@noida.hcltech.com>
 700
 701         * maxq.h: New file: Disassembly information for the maxq port.
 702
 703 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         * i386.h (i386_optab): Put back "movzb".
 706
 707 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 708
 709         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 710         comments.  Remove member cris_ver_sim.  Add members
 711         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 712         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 713         (struct cris_support_reg, struct cris_cond15): New types.
 714         (cris_conds15): Declare.
 715         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 716         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 717         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 718         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 719         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 720         SIZE_FIELD_UNSIGNED.
 721
 722 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 723
 724         * i386.h (sldx_Suf): Remove.
 725         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 726         (q_FP): Define, implying no REX64.
 727         (x_FP, sl_FP): Imply FloatMF.
 728         (i386_optab): Split reg and mem forms of moving from segment registers
 729         so that the memory forms can ignore the 16-/32-bit operand size
 730         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 731         all non-floating-point instructions. Unite 32- and 64-bit forms of
 732         movsx, movzx, and movd. Adjust floating point operations for the above
 733         changes to the *FP macros. Add DefaultSize to floating point control
 734         insns operating on larger memory ranges. Remove left over comments
 735         hinting at certain insns being Intel-syntax ones where the ones
 736         actually meant are already gone.
 737
 738 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 739
 740         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 741         instruction type.
 742
 743 2004-09-30  Paul Brook  <paul@codesourcery.com>
 744
 745         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 746         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 747
 748 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 749
 750         * avr.h: Add support for
 751         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 752
 753 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 754
 755         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 756
 757 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 758
 759         * msp430.h (msp430_opc): Add new instructions.
 760         (msp430_rcodes): Declare new instructions.
 761         (msp430_hcodes): Likewise..
 762
 763 2004-08-13  Nick Clifton  <nickc@redhat.com>
 764
 765         PR/301
 766         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 767         processors.
 768
 769 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 770
 771         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 772
 773 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 776
 777 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 778
 779         * i386.h: Adjust instruction descriptions to better match the
 780         specification.
 781
 782 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 783
 784         * arm.h: Remove all old content.  Replace with architecture defines
 785         from gas/config/tc-arm.c.
 786
 787 2004-07-09  Andreas Schwab  <schwab@suse.de>
 788
 789         * m68k.h: Fix comment.
 790
 791 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 792
 793         * crx.h: New file.
 794
 795 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 796
 797         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 798
 799 2004-05-24  Peter Barada  <peter@the-baradas.com>
 800
 801         * m68k.h: Add 'size' to m68k_opcode.
 802
 803 2004-05-05  Peter Barada  <peter@the-baradas.com>
 804
 805         * m68k.h: Switch from ColdFire chip name to core variant.
 806
 807 2004-04-22  Peter Barada  <peter@the-baradas.com>
 808
 809         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 810         descriptions for new EMAC cases.
 811         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 812         handle Motorola MAC syntax.
 813         Allow disassembly of ColdFire V4e object files.
 814
 815 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 816
 817         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 818
 819 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 820
 821         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 822
 823 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 824
 825         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 826
 827 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 828
 829         * i386.h (i386_optab): Added xstore/xcrypt insns.
 830
 831 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 832
 833         * h8300.h (32bit ldc/stc): Add relaxing support.
 834
 835 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 836
 837         * h8300.h (BITOP): Pass MEMRELAX flag.
 838
 839 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 840
 841         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 842         except for the H8S.
 843
 844 For older changes see ChangeLog-9103
 845 \f
 846 Local Variables:
 847 mode: change-log
 848 left-margin: 8
 849 fill-column: 74
 850 version-control: never
 851 End: