include/opcode/ChangeLog

   1 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
   2
   3         * mips.h (INSN_ISA_MASK): Updated.
   4         (INSN_ISA32R3): New define.
   5         (INSN_ISA32R5): New define.
   6         (INSN_ISA64R3): New define.
   7         (INSN_ISA64R5): New define.
   8         (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
   9         INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
  10         (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
  11         mips64r5.
  12         (INSN_UPTO32R3): New define.
  13         (INSN_UPTO32R5): New define.
  14         (INSN_UPTO64R3): New define.
  15         (INSN_UPTO64R5): New define.
  16         (ISA_MIPS32R3): New define.
  17         (ISA_MIPS32R5): New define.
  18         (ISA_MIPS64R3): New define.
  19         (ISA_MIPS64R5): New define.
  20         (CPU_MIPS32R3): New define.
  21         (CPU_MIPS32R5): New define.
  22         (CPU_MIPS64R3): New define.
  23         (CPU_MIPS64R5): New define.
  24
  25 2014-05-01  Richard Sandiford  <rdsandiford@googlemail.com>
  26
  27         * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
  28
  29 2014-04-22  Christian Svensson  <blue@cmd.nu>
  30
  31         * or32.h: Delete.
  32
  33 2014-03-05  Alan Modra  <amodra@gmail.com>
  34
  35         Update copyright years.
  36
  37 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
  38
  39         * mips.h: Updated description of +o, +u, +v and +w for MIPS and
  40         microMIPS.
  41
  42 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  43             Wei-Cheng Wang  <cole945@gmail.com>
  44
  45         * nds32.h: New file for Andes NDS32.
  46
  47 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
  48
  49         * bfin.h: Remove +x file mode.
  50
  51 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  52
  53         * aarch64.h (aarch64_pstatefields): Change element type to
  54         aarch64_sys_reg.
  55
  56 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
  57
  58         * arm.h (ARM_AEXT_V7VE): New define.
  59         (ARM_ARCH_V7VE): New define.
  60         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
  61
  62 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  63
  64         Revert
  65
  66         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  67
  68         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  69         (aarch64_sys_reg_writeonly_p): Ditto.
  70
  71 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  72
  73         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  74         (aarch64_sys_reg_writeonly_p): Ditto.
  75
  76 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  77
  78         * aarch64.h (aarch64_sys_reg): New typedef.
  79         (aarch64_sys_regs): Change to define with the new type.
  80         (aarch64_sys_reg_deprecated_p): Declare.
  81
  82 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  83
  84         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
  85         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
  86
  87 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  88
  89         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
  90         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
  91         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  92         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  93         For MIPS, update extension character sequences after +.
  94         (ASE_MSA): New define.
  95         (ASE_MSA64): New define.
  96         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  97         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  98         For microMIPS, update extension character sequences after +.
  99
 100 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 101
 102         PR binutils/15834
 103         * i960.h: Fix typos.
 104
 105 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 106
 107         * mips.h: Remove references to "+I" and imm2_expr.
 108
 109 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 110
 111         * mips.h (M_DEXT, M_DINS): Delete.
 112
 113 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 114
 115         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
 116         (mips_optional_operand_p): New function.
 117
 118 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 119             Richard Sandiford  <rdsandiford@googlemail.com>
 120
 121         * mips.h: Document new VU0 operand characters.
 122         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
 123         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
 124         (OP_REG_R5900_ACC): New mips_reg_operand_types.
 125         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
 126         (mips_vu0_channel_mask): Declare.
 127
 128 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 129
 130         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
 131         (mips_int_operand_min, mips_int_operand_max): New functions.
 132         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
 133
 134 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 135
 136         * mips.h (mips_decode_reg_operand): New function.
 137         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
 138         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
 139         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
 140         New macros.
 141         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
 142         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
 143         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
 144         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
 145         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 146         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 147         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 148         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 149         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 150         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 151         macros to cover the gaps.
 152         (INSN2_MOD_SP): Replace with...
 153         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 154         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 155         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 156         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 157         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 158         Delete.
 159
 160 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 161
 162         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 163         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 164         (MIPS16_INSN_COND_BRANCH): Delete.
 165
 166 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 167             Kirill Yukhin  <kirill.yukhin@intel.com>
 168             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 169
 170         * i386.h (BND_PREFIX_OPCODE): New.
 171
 172 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 173
 174         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 175         OP_SAVE_RESTORE_LIST.
 176         (decode_mips16_operand): Declare.
 177
 178 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 179
 180         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 181         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 182         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 183         (mips_pcrel_operand): New structures.
 184         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 185         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 186         (decode_mips_operand, decode_micromips_operand): Declare.
 187
 188 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 189
 190         * mips.h: Document MIPS16 "I" opcode.
 191
 192 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 193
 194         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 195         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 196         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 197         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 198         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 199         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 200         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 201         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 202         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 203         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 204         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 205         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 206         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 207         Rename to...
 208         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 209         (M_USD_AB): ...these.
 210
 211 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 212
 213         * mips.h: Remove documentation of "[" and "]".  Update documentation
 214         of "k" and the MDMX formats.
 215
 216 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 217
 218         * mips.h: Update documentation of "+s" and "+S".
 219
 220 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 221
 222         * mips.h: Document "+i".
 223
 224 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 225
 226         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 227         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 228         Delete.
 229         (INSN2_WRITE_GPR_MHI): Rename to...
 230         (INSN2_WRITE_GPR_MH): ...this.
 231
 232 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 233
 234         * mips.h: Remove documentation of "+D" and "+T".
 235
 236 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 237
 238         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 239         Use "source" rather than "destination" for microMIPS "G".
 240
 241 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 242
 243         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 244         values.
 245
 246 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 247
 248         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 249
 250 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 251             Maciej W. Rozycki  <macro@codesourcery.com>
 252             Chao-Ying Fu  <fu@mips.com>
 253
 254         * mips.h (OP_SH_EVAOFFSET): Define.
 255         (OP_MASK_EVAOFFSET): Define.
 256         (INSN_ASE_MASK): Delete.
 257         (ASE_EVA): Define.
 258         (M_CACHEE_AB, M_CACHEE_OB): New.
 259         (M_LBE_OB, M_LBE_AB): New.
 260         (M_LBUE_OB, M_LBUE_AB): New.
 261         (M_LHE_OB, M_LHE_AB): New.
 262         (M_LHUE_OB, M_LHUE_AB): New.
 263         (M_LLE_AB, M_LLE_OB): New.
 264         (M_LWE_OB, M_LWE_AB): New.
 265         (M_LWLE_AB, M_LWLE_OB): New.
 266         (M_LWRE_AB, M_LWRE_OB): New.
 267         (M_PREFE_AB, M_PREFE_OB): New.
 268         (M_SCE_AB, M_SCE_OB): New.
 269         (M_SBE_OB, M_SBE_AB): New.
 270         (M_SHE_OB, M_SHE_AB): New.
 271         (M_SWE_OB, M_SWE_AB): New.
 272         (M_SWLE_AB, M_SWLE_OB): New.
 273         (M_SWRE_AB, M_SWRE_OB): New.
 274         (MICROMIPSOP_SH_EVAOFFSET): Define.
 275         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 276
 277 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 278
 279         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 280
 281 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 282
 283         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 284
 285 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 286
 287         * mips.h (OP_MASK_CODE10): Correct definition.
 288         (OP_SH_CODE10): Likewise.
 289         Add a comment that "+J" is used now for OP_*CODE10.
 290         (INSN_ASE_MASK): Update.
 291         (INSN_VIRT): New macro.
 292         (INSN_VIRT64): New macro
 293
 294 2013-05-02  Nick Clifton  <nickc@redhat.com>
 295
 296         * msp430.h: Add patterns for MSP430X instructions.
 297
 298 2013-04-06  David S. Miller  <davem@davemloft.net>
 299
 300         * sparc.h (F_PREFERRED): Define.
 301         (F_PREF_ALIAS): Define.
 302
 303 2013-04-03  Nick Clifton  <nickc@redhat.com>
 304
 305         * v850.h (V850_INVERSE_PCREL): Define.
 306
 307 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 308
 309         PR binutils/15068
 310         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 311
 312 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 313
 314         PR binutils/15068
 315         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 316         Add 16-bit opcodes.
 317         * tic6xc-opcode-table.h: Add 16-bit insns.
 318         * tic6x.h: Add support for 16-bit insns.
 319
 320 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 321
 322         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 323         and mov.b/w/l Rs,@(d:32,ERd).
 324
 325 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 326
 327         PR gas/15082
 328         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 329         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 330         tic6x_operand_xregpair operand coding type.
 331         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 332         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 333         TIC6X_FLAG_NO_CROSS.
 334
 335 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 336
 337         PR gas/15095
 338         * tic6x.h (enum tic6x_coding_method): Add
 339         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 340         separately the msb and lsb of a register pair.  This is needed to
 341         encode the opcodes in the same way as TI assembler does.
 342         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 343         and rsqrdp opcodes to use the new field coding types.
 344
 345 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 346
 347         * arm.h (CRC_EXT_ARMV8): New constant.
 348         (ARCH_CRC_ARMV8): New macro.
 349
 350 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 351
 352         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 353
 354 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 355             Andrew Jenner <andrew@codesourcery.com>
 356
 357         Based on patches from Altera Corporation.
 358
 359         * nios2.h: New file.
 360
 361 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 362
 363         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 364
 365 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 366
 367         PR gas/15069
 368         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 369
 370 2013-01-24  Nick Clifton  <nickc@redhat.com>
 371
 372         * v850.h: Add e3v5 support.
 373
 374 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 375
 376         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 377
 378 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 379
 380         * ppc.h (PPC_OPCODE_POWER8): New define.
 381         (PPC_OPCODE_HTM): Likewise.
 382
 383 2013-01-10  Will Newton <will.newton@imgtec.com>
 384
 385         * metag.h: New file.
 386
 387 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 388
 389         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 390         (match_opcode): Rename to cr16_match_opcode.
 391
 392 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 393
 394         * mips.h: Add support for r5900 instructions including lq and sq.
 395
 396 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 397
 398         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 399         (make_instruction,match_opcode): Added function prototypes.
 400         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 401
 402 2012-11-23  Alan Modra  <amodra@gmail.com>
 403
 404         * ppc.h (ppc_parse_cpu): Update prototype.
 405
 406 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 407
 408         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 409         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 410
 411 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 412
 413         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 414
 415 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 416
 417         * ia64.h (ia64_opnd): Add new operand types.
 418
 419 2012-08-21  David S. Miller  <davem@davemloft.net>
 420
 421         * sparc.h (F3F4): New macro.
 422
 423 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 424             Laurent Desnogues  <laurent.desnogues@arm.com>
 425             Jim MacArthur  <jim.macarthur@arm.com>
 426             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 427             Nigel Stephens  <nigel.stephens@arm.com>
 428             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 429             Richard Earnshaw  <rearnsha@arm.com>
 430             Sofiane Naci  <sofiane.naci@arm.com>
 431             Tejas Belagod  <tejas.belagod@arm.com>
 432             Yufeng Zhang  <yufeng.zhang@arm.com>
 433
 434         * aarch64.h: New file.
 435
 436 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 437             Maciej W. Rozycki  <macro@codesourcery.com>
 438
 439         * mips.h (mips_opcode): Add the exclusions field.
 440         (OPCODE_IS_MEMBER): Remove macro.
 441         (cpu_is_member): New inline function.
 442         (opcode_is_member): Likewise.
 443
 444 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 445             Catherine Moore  <clm@codesourcery.com>
 446             Maciej W. Rozycki  <macro@codesourcery.com>
 447
 448         * mips.h: Document microMIPS DSP ASE usage.
 449         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 450         microMIPS DSP ASE support.
 451         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 452         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 453         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 454         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 455         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 456         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 457         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 458
 459 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 460
 461         * mips.h: Fix a typo in description.
 462
 463 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 464
 465         * avr.h: (AVR_ISA_XCH): New define.
 466         (AVR_ISA_XMEGA): Use it.
 467         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 468
 469 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 470
 471         * m68hc11.h: Add XGate definitions.
 472         (struct m68hc11_opcode): Add xg_mask field.
 473
 474 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 475             Maciej W. Rozycki  <macro@codesourcery.com>
 476             Rhonda Wittels  <rhonda@codesourcery.com>
 477
 478         * ppc.h (PPC_OPCODE_VLE): New definition.
 479         (PPC_OP_SA): New macro.
 480         (PPC_OP_SE_VLE): New macro.
 481         (PPC_OP): Use a variable shift amount.
 482         (powerpc_operand): Update comments.
 483         (PPC_OPSHIFT_INV): New macro.
 484         (PPC_OPERAND_CR): Replace with...
 485         (PPC_OPERAND_CR_BIT): ...this and
 486         (PPC_OPERAND_CR_REG): ...this.
 487
 488
 489 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 490
 491         * xgate.h: Header file for XGATE assembler.
 492
 493 2012-04-27  David S. Miller  <davem@davemloft.net>
 494
 495         * sparc.h: Document new arg code' )' for crypto RS3
 496         immediates.
 497
 498         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 499         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 500         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 501         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 502         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 503         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 504         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 505         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 506         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 507         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 508         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 509
 510 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 511
 512         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 513
 514 2012-02-27  Alan Modra  <amodra@gmail.com>
 515
 516         * crx.h (cst4_map): Update declaration.
 517
 518 2012-02-25  Walter Lee  <walt@tilera.com>
 519
 520         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 521         TILEGX_OPC_LD_TLS.
 522         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 523         TILEPRO_OPC_LW_TLS_SN.
 524
 525 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 528         (XRELEASE_PREFIX_OPCODE): Likewise.
 529
 530 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 531             Adam Nemet  <anemet@caviumnetworks.com>
 532
 533         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 534         (INSN_OCTEON2): New macro.
 535         (CPU_OCTEON2): New macro.
 536         (OPCODE_IS_MEMBER): Add Octeon2.
 537
 538 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 539
 540         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 541         (INSN_OCTEONP): New macro.
 542         (CPU_OCTEONP): New macro.
 543         (OPCODE_IS_MEMBER): Add Octeon+.
 544         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 545
 546 2011-11-01  DJ Delorie  <dj@redhat.com>
 547
 548         * rl78.h: New file.
 549
 550 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 551
 552         * mips.h: Fix a typo in description.
 553
 554 2011-09-21  David S. Miller  <davem@davemloft.net>
 555
 556         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 557         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 558         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 559         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 560
 561 2011-08-09  Chao-ying Fu  <fu@mips.com>
 562             Maciej W. Rozycki  <macro@codesourcery.com>
 563
 564         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 565         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 566         (INSN_ASE_MASK): Add the MCU bit.
 567         (INSN_MCU): New macro.
 568         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 569         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 570
 571 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 572
 573         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 574         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 575         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 576         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 577         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 578         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 579         (INSN2_READ_GPR_MMN): Likewise.
 580         (INSN2_READ_FPR_D): Change the bit used.
 581         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 582         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 583         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 584         (INSN2_COND_BRANCH): Likewise.
 585         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 586         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 587         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 588         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 589         (INSN2_MOD_GPR_MN): Likewise.
 590
 591 2011-08-05  David S. Miller  <davem@davemloft.net>
 592
 593         * sparc.h: Document new format codes '4', '5', and '('.
 594         (OPF_LOW4, RS3): New macros.
 595
 596 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 597
 598         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 599         order of flags documented.
 600
 601 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 602
 603         * mips.h: Clarify the description of microMIPS instruction
 604         manipulation macros.
 605         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 606
 607 2011-07-24  Chao-ying Fu  <fu@mips.com>
 608             Maciej W. Rozycki  <macro@codesourcery.com>
 609
 610         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 611         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 612         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 613         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 614         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 615         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 616         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 617         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 618         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 619         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 620         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 621         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 622         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 623         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 624         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 625         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 626         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 627         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 628         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 629         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 630         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 631         (INSN_WRITE_GPR_S): New macro.
 632         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 633         (INSN2_READ_FPR_D): Likewise.
 634         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 635         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 636         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 637         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 638         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 639         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 640         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 641         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 642         (CPU_MICROMIPS): New macro.
 643         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 644         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 645         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 646         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 647         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 648         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 649         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 650         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 651         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 652         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 653         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 654         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 655         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 656         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 657         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 658         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 659         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 660         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 661         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 662         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 663         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 664         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 665         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 666         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 667         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 668         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 669         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 670         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 671         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 672         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 673         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 674         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 675         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 676         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 677         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 678         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 679         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 680         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 681         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 682         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 683         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 684         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 685         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 686         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 687         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 688         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 689         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 690         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 691         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 692         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 693         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 694         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 695         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 696         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 697         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 698         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 699         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 700         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 701         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 702         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 703         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 704         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 705         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 706         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 707         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 708         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 709         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 710         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 711         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 712         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 713         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 714         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 715         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 716         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 717         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 718         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 719         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 720         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 721         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 722         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 723         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 724         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 725         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 726         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 727         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 728         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 729         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 730         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 731         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 732         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 733         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 734         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 735         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 736         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 737         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 738         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 739         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 740         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 741         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 742         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 743         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 744         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 745         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 746         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 747         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 748         (micromips_opcodes): New declaration.
 749         (bfd_micromips_num_opcodes): Likewise.
 750
 751 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 752
 753         * mips.h (INSN_TRAP): Rename to...
 754         (INSN_NO_DELAY_SLOT): ... this.
 755         (INSN_SYNC): Remove macro.
 756
 757 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 758
 759         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 760         a duplicate of AVR_ISA_SPM.
 761
 762 2011-07-01  Nick Clifton  <nickc@redhat.com>
 763
 764         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 765
 766 2011-06-18  Robin Getz  <robin.getz@analog.com>
 767
 768         * bfin.h (is_macmod_signed): New func
 769
 770 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 771
 772         * bfin.h (is_macmod_pmove): Add missing space before func args.
 773         (is_macmod_hmove): Likewise.
 774
 775 2011-06-13  Walter Lee  <walt@tilera.com>
 776
 777         * tilegx.h: New file.
 778         * tilepro.h: New file.
 779
 780 2011-05-31  Paul Brook  <paul@codesourcery.com>
 781
 782         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 783
 784 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 785
 786         * s390.h: Replace S390_OPERAND_REG_EVEN with
 787         S390_OPERAND_REG_PAIR.
 788
 789 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 790
 791         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 792
 793 2011-04-18  Julian Brown  <julian@codesourcery.com>
 794
 795         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 796
 797 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 798
 799         PR gas/12296
 800         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 801
 802 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 803
 804         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 805         New instruction set flags.
 806         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 807
 808 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 809
 810         * mips.h (M_PREF_AB): New enum value.
 811
 812 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 813
 814         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 815         M_IU): Define.
 816         (is_macmod_pmove, is_macmod_hmove): New functions.
 817
 818 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 819
 820         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 821
 822 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 823
 824         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 825         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 826
 827 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 828
 829         PR gas/11395
 830         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 831         "bb" entries.
 832
 833 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 834
 835         PR gas/11395
 836         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 837
 838 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 839
 840         * mips.h: Update commentary after last commit.
 841
 842 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 843
 844         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 845         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 846         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 847
 848 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 849
 850         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 851
 852 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 853
 854         * mips.h: Fix previous commit.
 855
 856 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 857
 858         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 859         (INSN_LOONGSON_3A): Clear bit 31.
 860
 861 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 862
 863         PR gas/12198
 864         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 865         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 866         (ARM_ARCH_V6M_ONLY): New define.
 867
 868 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 869
 870         * mips.h (INSN_LOONGSON_3A): Defined.
 871         (CPU_LOONGSON_3A): Defined.
 872         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 873
 874 2010-10-09  Matt Rice  <ratmice@gmail.com>
 875
 876         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 877         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 878
 879 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 880
 881         * arm.h (ARM_EXT_VIRT): New define.
 882         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 883         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 884         Extensions.
 885
 886 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 887
 888         * arm.h (ARM_AEXT_ADIV): New define.
 889         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 890
 891 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 892
 893         * arm.h (ARM_EXT_OS): New define.
 894         (ARM_AEXT_V6SM): Likewise.
 895         (ARM_ARCH_V6SM): Likewise.
 896
 897 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 898
 899         * arm.h (ARM_EXT_MP): Add.
 900         (ARM_ARCH_V7A_MP): Likewise.
 901
 902 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 903
 904         * bfin.h: Declare pseudoChr structs/defines.
 905
 906 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 907
 908         * bfin.h: Strip trailing whitespace.
 909
 910 2010-07-29  DJ Delorie  <dj@redhat.com>
 911
 912         * rx.h (RX_Operand_Type): Add TwoReg.
 913         (RX_Opcode_ID): Remove ediv and ediv2.
 914
 915 2010-07-27  DJ Delorie  <dj@redhat.com>
 916
 917         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 918
 919 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 920             Ina Pandit  <ina.pandit@kpitcummins.com>
 921
 922         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 923         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 924         PROCESSOR_V850E2_ALL.
 925         Remove PROCESSOR_V850EA support.
 926         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 927         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 928         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 929         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 930         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 931         V850_OPERAND_PERCENT.
 932         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 933         V850_NOT_R0.
 934         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 935         and V850E_PUSH_POP
 936
 937 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 938
 939         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 940         (MIPS16_INSN_BRANCH): Rename to...
 941         (MIPS16_INSN_COND_BRANCH): ... this.
 942
 943 2010-07-03  Alan Modra  <amodra@gmail.com>
 944
 945         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 946         Renumber other PPC_OPCODE defines.
 947
 948 2010-07-03  Alan Modra  <amodra@gmail.com>
 949
 950         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 951
 952 2010-06-29  Alan Modra  <amodra@gmail.com>
 953
 954         * maxq.h: Delete file.
 955
 956 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 957
 958         * ppc.h (PPC_OPCODE_E500): Define.
 959
 960 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 961
 962         * opcode/mips.h (INSN_MIPS16): Remove.
 963
 964 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 965
 966         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 967
 968 2010-04-15  Nick Clifton  <nickc@redhat.com>
 969
 970         * alpha.h: Update copyright notice to use GPLv3.
 971         * arc.h: Likewise.
 972         * arm.h: Likewise.
 973         * avr.h: Likewise.
 974         * bfin.h: Likewise.
 975         * cgen.h: Likewise.
 976         * convex.h: Likewise.
 977         * cr16.h: Likewise.
 978         * cris.h: Likewise.
 979         * crx.h: Likewise.
 980         * d10v.h: Likewise.
 981         * d30v.h: Likewise.
 982         * dlx.h: Likewise.
 983         * h8300.h: Likewise.
 984         * hppa.h: Likewise.
 985         * i370.h: Likewise.
 986         * i386.h: Likewise.
 987         * i860.h: Likewise.
 988         * i960.h: Likewise.
 989         * ia64.h: Likewise.
 990         * m68hc11.h: Likewise.
 991         * m68k.h: Likewise.
 992         * m88k.h: Likewise.
 993         * maxq.h: Likewise.
 994         * mips.h: Likewise.
 995         * mmix.h: Likewise.
 996         * mn10200.h: Likewise.
 997         * mn10300.h: Likewise.
 998         * msp430.h: Likewise.
 999         * np1.h: Likewise.
1000         * ns32k.h: Likewise.
1001         * or32.h: Likewise.
1002         * pdp11.h: Likewise.
1003         * pj.h: Likewise.
1004         * pn.h: Likewise.
1005         * ppc.h: Likewise.
1006         * pyr.h: Likewise.
1007         * rx.h: Likewise.
1008         * s390.h: Likewise.
1009         * score-datadep.h: Likewise.
1010         * score-inst.h: Likewise.
1011         * sparc.h: Likewise.
1012         * spu-insns.h: Likewise.
1013         * spu.h: Likewise.
1014         * tic30.h: Likewise.
1015         * tic4x.h: Likewise.
1016         * tic54x.h: Likewise.
1017         * tic80.h: Likewise.
1018         * v850.h: Likewise.
1019         * vax.h: Likewise.
1020
1021 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
1022
1023         * tic6x-control-registers.h, tic6x-insn-formats.h,
1024         tic6x-opcode-table.h, tic6x.h: New.
1025
1026 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
1027
1028         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1029
1030 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
1031
1032         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1033
1034 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
1035
1036         * ia64.h (ia64_find_opcode): Remove argument name.
1037         (ia64_find_next_opcode): Likewise.
1038         (ia64_dis_opcode): Likewise.
1039         (ia64_free_opcode): Likewise.
1040         (ia64_find_dependency): Likewise.
1041
1042 2009-11-22  Doug Evans  <dje@sebabeach.org>
1043
1044         * cgen.h: Include bfd_stdint.h.
1045         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1046
1047 2009-11-18  Paul Brook  <paul@codesourcery.com>
1048
1049         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1050
1051 2009-11-17  Paul Brook  <paul@codesourcery.com>
1052         Daniel Jacobowitz  <dan@codesourcery.com>
1053
1054         * arm.h (ARM_EXT_V6_DSP): Define.
1055         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1056         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1057
1058 2009-11-04  DJ Delorie  <dj@redhat.com>
1059
1060         * rx.h (rx_decode_opcode) (mvtipl): Add.
1061         (mvtcp, mvfcp, opecp): Remove.
1062
1063 2009-11-02  Paul Brook  <paul@codesourcery.com>
1064
1065         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1066         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1067         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1068         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1069         FPU_ARCH_NEON_VFP_V4): Define.
1070
1071 2009-10-23  Doug Evans  <dje@sebabeach.org>
1072
1073         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1074         * cgen.h: Update.  Improve multi-inclusion macro name.
1075
1076 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1077
1078         * ppc.h (PPC_OPCODE_476): Define.
1079
1080 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1081
1082         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1083
1084 2009-09-29  DJ Delorie  <dj@redhat.com>
1085
1086         * rx.h: New file.
1087
1088 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1089
1090         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1091
1092 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1093
1094         * ppc.h (PPC_OPCODE_PPCA2): New.
1095
1096 2009-09-05  Martin Thuresson  <martin@mtme.org>
1097
1098         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1099
1100 2009-08-29  Martin Thuresson  <martin@mtme.org>
1101
1102         * tic30.h (template): Rename type template to
1103         insn_template. Updated code to use new name.
1104         * tic54x.h (template): Rename type template to
1105         insn_template.
1106
1107 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1108
1109         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1110
1111 2009-06-11  Anthony Green  <green@moxielogic.com>
1112
1113         * moxie.h (MOXIE_F3_PCREL): Define.
1114         (moxie_form3_opc_info): Grow.
1115
1116 2009-06-06  Anthony Green  <green@moxielogic.com>
1117
1118         * moxie.h (MOXIE_F1_M): Define.
1119
1120 2009-04-15  Anthony Green  <green@moxielogic.com>
1121
1122         * moxie.h: Created.
1123
1124 2009-04-06  DJ Delorie  <dj@redhat.com>
1125
1126         * h8300.h: Add relaxation attributes to MOVA opcodes.
1127
1128 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1129
1130         * ppc.h (ppc_parse_cpu): Declare.
1131
1132 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1133
1134         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1135         and _IMM11 for mbitclr and mbitset.
1136         * score-datadep.h: Update dependency information.
1137
1138 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1139
1140         * ppc.h (PPC_OPCODE_POWER7): New.
1141
1142 2009-02-06  Doug Evans  <dje@google.com>
1143
1144         * i386.h: Add comment regarding sse* insns and prefixes.
1145
1146 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1147
1148         * mips.h (INSN_XLR): Define.
1149         (INSN_CHIP_MASK): Update.
1150         (CPU_XLR): Define.
1151         (OPCODE_IS_MEMBER): Update.
1152         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1153
1154 2009-01-28  Doug Evans  <dje@google.com>
1155
1156         * opcode/i386.h: Add multiple inclusion protection.
1157         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1158         (EDI_REG_NUM): New macros.
1159         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1160         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1161         (REX_PREFIX_P): New macro.
1162
1163 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1164
1165         * ppc.h (struct powerpc_opcode): New field "deprecated".
1166         (PPC_OPCODE_NOPOWER4): Delete.
1167
1168 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1169
1170         * mips.h: Define CPU_R14000, CPU_R16000.
1171         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1172
1173 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1174
1175         * arm.h (FPU_NEON_FP16): New.
1176         (FPU_ARCH_NEON_FP16): New.
1177
1178 2008-11-06  Chao-ying Fu  <fu@mips.com>
1179
1180         * mips.h: Doucument '1' for 5-bit sync type.
1181
1182 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1183
1184         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1185         IA64_RS_CR.
1186
1187 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1188
1189         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1190
1191 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1192
1193         * ppc.h (PPC_OPCODE_405): Define.
1194         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1195
1196 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1197
1198         * ppc.h (ppc_cpu_t): New typedef.
1199         (struct powerpc_opcode <flags>): Use it.
1200         (struct powerpc_operand <insert, extract>): Likewise.
1201         (struct powerpc_macro <flags>): Likewise.
1202
1203 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1204
1205         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1206         Update comment before MIPS16 field descriptors to mention MIPS16.
1207         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1208         BBIT.
1209         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1210         New bit masks and shift counts for cins and exts.
1211
1212         * mips.h: Document new field descriptors +Q.
1213         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1214
1215 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1216
1217         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1218         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1219
1220 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1221
1222         * ppc.h: (PPC_OPCODE_E500MC): New.
1223
1224 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1225
1226         * i386.h (MAX_OPERANDS): Set to 5.
1227         (MAX_MNEM_SIZE): Changed to 20.
1228
1229 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1230
1231         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1232
1233 2008-03-09  Paul Brook  <paul@codesourcery.com>
1234
1235         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1236
1237 2008-03-04  Paul Brook  <paul@codesourcery.com>
1238
1239         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1240         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1241         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1242
1243 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1244             Nick Clifton  <nickc@redhat.com>
1245
1246         PR 3134
1247         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1248         with a 32-bit displacement but without the top bit of the 4th byte
1249         set.
1250
1251 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1252
1253         * cr16.h (cr16_num_optab): Declared.
1254
1255 2008-02-14  Hakan Ardo  <hakan@debian.org>
1256
1257         PR gas/2626
1258         * avr.h (AVR_ISA_2xxe): Define.
1259
1260 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1261
1262         * mips.h: Update copyright.
1263         (INSN_CHIP_MASK): New macro.
1264         (INSN_OCTEON): New macro.
1265         (CPU_OCTEON): New macro.
1266         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1267
1268 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1269
1270         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1271
1272 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1273
1274         * avr.h (AVR_ISA_USB162): Add new opcode set.
1275         (AVR_ISA_AVR3): Likewise.
1276
1277 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1278
1279         * mips.h (INSN_LOONGSON_2E): New.
1280         (INSN_LOONGSON_2F): New.
1281         (CPU_LOONGSON_2E): New.
1282         (CPU_LOONGSON_2F): New.
1283         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1284
1285 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1286
1287         * mips.h (INSN_ISA*): Redefine certain values as an
1288         enumeration.  Update comments.
1289         (mips_isa_table): New.
1290         (ISA_MIPS*): Redefine to match enumeration.
1291         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1292         values.
1293
1294 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1295
1296         * ppc.h (PPC_OPCODE_PPCPS): New.
1297
1298 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1299
1300         * m68k.h: Document j K & E.
1301
1302 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1303
1304         * cr16.h: New file for CR16 target.
1305
1306 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1307
1308         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1309
1310 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1311
1312         * m68k.h (mcfisa_c): New.
1313         (mcfusp, mcf_mask): Adjust.
1314
1315 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1316
1317         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1318         (num_powerpc_operands): Declare.
1319         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1320         (PPC_OPERAND_PLUS1): Define.
1321
1322 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1323
1324         * i386.h (REX_MODE64): Renamed to ...
1325         (REX_W): This.
1326         (REX_EXTX): Renamed to ...
1327         (REX_R): This.
1328         (REX_EXTY): Renamed to ...
1329         (REX_X): This.
1330         (REX_EXTZ): Renamed to ...
1331         (REX_B): This.
1332
1333 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1334
1335         * i386.h: Add entries from config/tc-i386.h and move tables
1336         to opcodes/i386-opc.h.
1337
1338 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1339
1340         * i386.h (FloatDR): Removed.
1341         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1342
1343 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1344
1345         * spu-insns.h: Add soma double-float insns.
1346
1347 2007-02-20  Thiemo Seufer  <ths@mips.com>
1348             Chao-Ying Fu  <fu@mips.com>
1349
1350         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1351         (INSN_DSPR2): Add flag for DSP R2 instructions.
1352         (M_BALIGN): New macro.
1353
1354 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1355
1356         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1357         and Seg3ShortFrom with Shortform.
1358
1359 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1360
1361         PR gas/4027
1362         * i386.h (i386_optab): Put the real "test" before the pseudo
1363         one.
1364
1365 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1366
1367         * m68k.h (m68010up): OR fido_a.
1368
1369 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1370
1371         * m68k.h (fido_a): New.
1372
1373 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1374
1375         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1376         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1377         values.
1378
1379 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1380
1381         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1382
1383 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1384
1385         * score-inst.h (enum score_insn_type): Add Insn_internal.
1386
1387 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1388             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1389             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1390             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1391             Alan Modra  <amodra@bigpond.net.au>
1392
1393         * spu-insns.h: New file.
1394         * spu.h: New file.
1395
1396 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1397
1398         * ppc.h (PPC_OPCODE_CELL): Define.
1399
1400 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1401
1402         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1403         in amdfam10 architecture.
1404
1405 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1406
1407         * i386.h: Replace CpuMNI with CpuSSSE3.
1408
1409 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1410             Joseph Myers  <joseph@codesourcery.com>
1411             Ian Lance Taylor  <ian@wasabisystems.com>
1412             Ben Elliston  <bje@wasabisystems.com>
1413
1414         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1415
1416 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1417
1418         * score-datadep.h: New file.
1419         * score-inst.h: New file.
1420
1421 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1422
1423         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1424         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1425         movdq2q and movq2dq.
1426
1427 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1428            Michael Meissner             <michael.meissner@amd.com>
1429
1430         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1431
1432 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1433
1434         * i386.h (i386_optab): Add "nop" with memory reference.
1435
1436 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1437
1438         * i386.h (i386_optab): Update comment for 64bit NOP.
1439
1440 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1441             Anton Blanchard  <anton@samba.org>
1442
1443         * ppc.h (PPC_OPCODE_POWER6): Define.
1444         Adjust whitespace.
1445
1446 2006-06-05  Thiemo Seufer  <ths@mips.com>
1447
1448         * mips.h: Improve description of MT flags.
1449
1450 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1451
1452         * m68k.h (mcf_mask): Define.
1453
1454 2006-05-05  Thiemo Seufer  <ths@mips.com>
1455             David Ung  <davidu@mips.com>
1456
1457         * mips.h (enum): Add macro M_CACHE_AB.
1458
1459 2006-05-04  Thiemo Seufer  <ths@mips.com>
1460             Nigel Stephens  <nigel@mips.com>
1461             David Ung  <davidu@mips.com>
1462
1463         * mips.h: Add INSN_SMARTMIPS define.
1464
1465 2006-04-30  Thiemo Seufer  <ths@mips.com>
1466             David Ung  <davidu@mips.com>
1467
1468         * mips.h: Defines udi bits and masks.  Add description of
1469         characters which may appear in the args field of udi
1470         instructions.
1471
1472 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1473
1474         * mips.h: Improve comments describing the bitfield instruction
1475         fields.
1476
1477 2006-04-26  Julian Brown  <julian@codesourcery.com>
1478
1479         * arm.h (FPU_VFP_EXT_V3): Define constant.
1480         (FPU_NEON_EXT_V1): Likewise.
1481         (FPU_VFP_HARD): Update.
1482         (FPU_VFP_V3): Define macro.
1483         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1484
1485 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1486
1487         * avr.h (AVR_ISA_PWMx): New.
1488
1489 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1490
1491         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1492         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1493         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1494         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1495         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1496
1497 2006-03-10  Paul Brook  <paul@codesourcery.com>
1498
1499         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1500
1501 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1502
1503         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1504         first.  Correct mask of bb "B" opcode.
1505
1506 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1507
1508         * i386.h (i386_optab): Support Intel Merom New Instructions.
1509
1510 2006-02-24  Paul Brook  <paul@codesourcery.com>
1511
1512         * arm.h: Add V7 feature bits.
1513
1514 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1515
1516         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1517
1518 2006-01-31  Paul Brook  <paul@codesourcery.com>
1519         Richard Earnshaw <rearnsha@arm.com>
1520
1521         * arm.h: Use ARM_CPU_FEATURE.
1522         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1523         (arm_feature_set): Change to a structure.
1524         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1525         ARM_FEATURE): New macros.
1526
1527 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1528
1529         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1530         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1531         (ADD_PC_INCR_OPCODE): Don't define.
1532
1533 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1534
1535         PR gas/1874
1536         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1537
1538 2005-11-14  David Ung  <davidu@mips.com>
1539
1540         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1541         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1542         save/restore encoding of the args field.
1543
1544 2005-10-28  Dave Brolley  <brolley@redhat.com>
1545
1546         Contribute the following changes:
1547         2005-02-16  Dave Brolley  <brolley@redhat.com>
1548
1549         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1550         cgen_isa_mask_* to cgen_bitset_*.
1551         * cgen.h: Likewise.
1552
1553         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1554
1555         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1556         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1557         (CGEN_CPU_TABLE): Make isas a ponter.
1558
1559         2003-09-29  Dave Brolley  <brolley@redhat.com>
1560
1561         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1562         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1563         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1564
1565         2002-12-13  Dave Brolley  <brolley@redhat.com>
1566
1567         * cgen.h (symcat.h): #include it.
1568         (cgen-bitset.h): #include it.
1569         (CGEN_ATTR_VALUE_TYPE): Now a union.
1570         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1571         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1572         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1573         * cgen-bitset.h: New file.
1574
1575 2005-09-30  Catherine Moore  <clm@cm00re.com>
1576
1577         * bfin.h: New file.
1578
1579 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1580
1581         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1582         indirect operands.
1583
1584 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1585
1586         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1587         Add FLAG_STRICT to pa10 ftest opcode.
1588
1589 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1590
1591         * hppa.h (pa_opcodes): Remove lha entries.
1592
1593 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1594
1595         * hppa.h (FLAG_STRICT): Revise comment.
1596         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1597         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1598         entries for "fdc".
1599
1600 2005-09-30  Catherine Moore  <clm@cm00re.com>
1601
1602         * bfin.h: New file.
1603
1604 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1605
1606         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1607
1608 2005-09-06  Chao-ying Fu  <fu@mips.com>
1609
1610         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1611         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1612         define.
1613         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1614         (INSN_ASE_MASK): Update to include INSN_MT.
1615         (INSN_MT): New define for MT ASE.
1616
1617 2005-08-25  Chao-ying Fu  <fu@mips.com>
1618
1619         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1620         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1621         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1622         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1623         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1624         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1625         instructions.
1626         (INSN_DSP): New define for DSP ASE.
1627
1628 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1629
1630         * a29k.h: Delete.
1631
1632 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1633
1634         * ppc.h (PPC_OPCODE_E300): Define.
1635
1636 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1637
1638         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1639
1640 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1641
1642         PR gas/336
1643         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1644         and pitlb.
1645
1646 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1647
1648         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1649         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1650         Add movq-s as 64-bit variants of movd-s.
1651
1652 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1653
1654         * hppa.h: Fix punctuation in comment.
1655
1656         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1657         implicit space-register addressing.  Set space-register bits on opcodes
1658         using implicit space-register addressing.  Add various missing pa20
1659         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1660         space-register addressing.  Use "fE" instead of "fe" in various
1661         fstw opcodes.
1662
1663 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1664
1665         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1666
1667 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1668
1669         * i386.h (i386_optab): Support Intel VMX Instructions.
1670
1671 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1672
1673         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1674
1675 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1676
1677         * i386.h (i386_optab): Add new insns.
1678
1679 2005-07-01  Nick Clifton  <nickc@redhat.com>
1680
1681         * sparc.h: Add typedefs to structure declarations.
1682
1683 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1684
1685         PR 1013
1686         * i386.h (i386_optab): Update comments for 64bit addressing on
1687         mov. Allow 64bit addressing for mov and movq.
1688
1689 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1690
1691         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1692         respectively, in various floating-point load and store patterns.
1693
1694 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1695
1696         * hppa.h (FLAG_STRICT): Correct comment.
1697         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1698         PA 2.0 mneumonics when equivalent.  Entries with cache control
1699         completers now require PA 1.1.  Adjust whitespace.
1700
1701 2005-05-19  Anton Blanchard  <anton@samba.org>
1702
1703         * ppc.h (PPC_OPCODE_POWER5): Define.
1704
1705 2005-05-10  Nick Clifton  <nickc@redhat.com>
1706
1707         * Update the address and phone number of the FSF organization in
1708         the GPL notices in the following files:
1709         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1710         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1711         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1712         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1713         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1714         tic54x.h, tic80.h, v850.h, vax.h
1715
1716 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1717
1718         * i386.h (i386_optab): Add ht and hnt.
1719
1720 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1721
1722         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1723         Add xcrypt-ctr.  Provide aliases without hyphens.
1724
1725 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1726
1727         Moved from ../ChangeLog
1728
1729         2005-04-12  Paul Brook  <paul@codesourcery.com>
1730         * m88k.h: Rename psr macros to avoid conflicts.
1731
1732         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1733         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1734         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1735         and ARM_ARCH_V6ZKT2.
1736
1737         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1738         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1739         Remove redundant instruction types.
1740         (struct argument): X_op - new field.
1741         (struct cst4_entry): Remove.
1742         (no_op_insn): Declare.
1743
1744         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1745         * crx.h (enum argtype): Rename types, remove unused types.
1746
1747         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1748         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1749         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1750         (enum operand_type): Rearrange operands, edit comments.
1751         replace us<N> with ui<N> for unsigned immediate.
1752         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1753         displacements (respectively).
1754         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1755         (instruction type): Add NO_TYPE_INS.
1756         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1757         (operand_entry): New field - 'flags'.
1758         (operand flags): New.
1759
1760         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1761         * crx.h (operand_type): Remove redundant types i3, i4,
1762         i5, i8, i12.
1763         Add new unsigned immediate types us3, us4, us5, us16.
1764
1765 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1766
1767         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1768         adjust them accordingly.
1769
1770 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1771
1772         * i386.h (i386_optab): Add rdtscp.
1773
1774 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1775
1776         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1777         between memory and segment register. Allow movq for moving between
1778         general-purpose register and segment register.
1779
1780 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1781
1782         PR gas/707
1783         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1784         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1785         fnstsw.
1786
1787 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1788
1789         * m68k.h (m68008, m68ec030, m68882): Remove.
1790         (m68k_mask): New.
1791         (cpu_m68k, cpu_cf): New.
1792         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1793         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1794
1795 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1796
1797         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1798         * cgen.h (enum cgen_parse_operand_type): Add
1799         CGEN_PARSE_OPERAND_SYMBOLIC.
1800
1801 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1802
1803         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1804         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1805         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1806
1807 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1808
1809         * mips.h (struct mips_opcode): Add new pinfo2 member.
1810         (INSN_ALIAS): New define for opcode table entries that are
1811         specific instances of another entry, such as 'move' for an 'or'
1812         with a zero operand.
1813         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1814         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1815
1816 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1817
1818         * mips.h (CPU_RM9000): Define.
1819         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1820
1821 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1822
1823         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1824         to/from test registers are illegal in 64-bit mode. Add missing
1825         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1826         (previously one had to explicitly encode a rex64 prefix). Re-enable
1827         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1828         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1829
1830 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1831
1832         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1833         available only with SSE2. Change the MMX additions introduced by SSE
1834         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1835         instructions by their now designated identifier (since combining i686
1836         and 3DNow! does not really imply 3DNow!A).
1837
1838 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1839
1840         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1841         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1842
1843 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1844             Vineet Sharma      <vineets@noida.hcltech.com>
1845
1846         * maxq.h: New file: Disassembly information for the maxq port.
1847
1848 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1849
1850         * i386.h (i386_optab): Put back "movzb".
1851
1852 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1853
1854         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1855         comments.  Remove member cris_ver_sim.  Add members
1856         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1857         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1858         (struct cris_support_reg, struct cris_cond15): New types.
1859         (cris_conds15): Declare.
1860         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1861         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1862         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1863         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1864         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1865         SIZE_FIELD_UNSIGNED.
1866
1867 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1868
1869         * i386.h (sldx_Suf): Remove.
1870         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1871         (q_FP): Define, implying no REX64.
1872         (x_FP, sl_FP): Imply FloatMF.
1873         (i386_optab): Split reg and mem forms of moving from segment registers
1874         so that the memory forms can ignore the 16-/32-bit operand size
1875         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1876         all non-floating-point instructions. Unite 32- and 64-bit forms of
1877         movsx, movzx, and movd. Adjust floating point operations for the above
1878         changes to the *FP macros. Add DefaultSize to floating point control
1879         insns operating on larger memory ranges. Remove left over comments
1880         hinting at certain insns being Intel-syntax ones where the ones
1881         actually meant are already gone.
1882
1883 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1884
1885         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1886         instruction type.
1887
1888 2004-09-30  Paul Brook  <paul@codesourcery.com>
1889
1890         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1891         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1892
1893 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1894
1895         * avr.h: Add support for
1896         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1897
1898 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1899
1900         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1901
1902 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1903
1904         * msp430.h (msp430_opc): Add new instructions.
1905         (msp430_rcodes): Declare new instructions.
1906         (msp430_hcodes): Likewise..
1907
1908 2004-08-13  Nick Clifton  <nickc@redhat.com>
1909
1910         PR/301
1911         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1912         processors.
1913
1914 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1915
1916         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1917
1918 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1919
1920         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1921
1922 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1923
1924         * i386.h: Adjust instruction descriptions to better match the
1925         specification.
1926
1927 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1928
1929         * arm.h: Remove all old content.  Replace with architecture defines
1930         from gas/config/tc-arm.c.
1931
1932 2004-07-09  Andreas Schwab  <schwab@suse.de>
1933
1934         * m68k.h: Fix comment.
1935
1936 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1937
1938         * crx.h: New file.
1939
1940 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1941
1942         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1943
1944 2004-05-24  Peter Barada  <peter@the-baradas.com>
1945
1946         * m68k.h: Add 'size' to m68k_opcode.
1947
1948 2004-05-05  Peter Barada  <peter@the-baradas.com>
1949
1950         * m68k.h: Switch from ColdFire chip name to core variant.
1951
1952 2004-04-22  Peter Barada  <peter@the-baradas.com>
1953
1954         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1955         descriptions for new EMAC cases.
1956         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1957         handle Motorola MAC syntax.
1958         Allow disassembly of ColdFire V4e object files.
1959
1960 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1961
1962         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1963
1964 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1965
1966         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1967
1968 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1969
1970         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1971
1972 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1973
1974         * i386.h (i386_optab): Added xstore/xcrypt insns.
1975
1976 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1977
1978         * h8300.h (32bit ldc/stc): Add relaxing support.
1979
1980 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1981
1982         * h8300.h (BITOP): Pass MEMRELAX flag.
1983
1984 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1985
1986         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1987         except for the H8S.
1988
1989 For older changes see ChangeLog-9103
1990 \f
1991 Copyright (C) 2004-2014 Free Software Foundation, Inc.
1992
1993 Copying and distribution of this file, with or without modification,
1994 are permitted in any medium without royalty provided the copyright
1995 notice and this notice are preserved.
1996
1997 Local Variables:
1998 mode: change-log
1999 left-margin: 8
2000 fill-column: 74
2001 version-control: never
2002 End: