include/opcode/ChangeLog

   1 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386.h (i386_optab): Update comment for 64bit NOP.
   4
   5 2006-06-06  Ben Elliston  <bje@au.ibm.com>
   6             Anton Blanchard  <anton@samba.org>
   7
   8         * ppc.h (PPC_OPCODE_POWER6): Define.
   9         Adjust whitespace.
  10
  11 2006-06-05  Thiemo Seufer  <ths@mips.com>
  12
  13         * mips.h: Improve description of MT flags.
  14
  15 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  16
  17         * m68k.h (mcf_mask): Define.
  18
  19 2006-05-05  Thiemo Seufer  <ths@mips.com>
  20             David Ung  <davidu@mips.com>
  21
  22         * mips.h (enum): Add macro M_CACHE_AB.
  23
  24 2006-05-04  Thiemo Seufer  <ths@mips.com>
  25             Nigel Stephens  <nigel@mips.com>
  26             David Ung  <davidu@mips.com>
  27
  28         * mips.h: Add INSN_SMARTMIPS define.
  29
  30 2006-04-30  Thiemo Seufer  <ths@mips.com>
  31             David Ung  <davidu@mips.com>
  32
  33         * mips.h: Defines udi bits and masks.  Add description of
  34         characters which may appear in the args field of udi
  35         instructions.
  36
  37 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  38
  39         * mips.h: Improve comments describing the bitfield instruction
  40         fields.
  41
  42 2006-04-26  Julian Brown  <julian@codesourcery.com>
  43
  44         * arm.h (FPU_VFP_EXT_V3): Define constant.
  45         (FPU_NEON_EXT_V1): Likewise.
  46         (FPU_VFP_HARD): Update.
  47         (FPU_VFP_V3): Define macro.
  48         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  49
  50 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
  51
  52         * avr.h (AVR_ISA_PWMx): New.
  53
  54 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
  55
  56         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
  57         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
  58         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  59         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
  60         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
  61
  62 2006-03-10  Paul Brook  <paul@codesourcery.com>
  63
  64         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  65
  66 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  67
  68         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
  69         first.  Correct mask of bb "B" opcode.
  70
  71 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  72
  73         * i386.h (i386_optab): Support Intel Merom New Instructions.
  74
  75 2006-02-24  Paul Brook  <paul@codesourcery.com>
  76
  77         * arm.h: Add V7 feature bits.
  78
  79 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  82
  83 2006-01-31  Paul Brook  <paul@codesourcery.com>
  84         Richard Earnshaw <rearnsha@arm.com>
  85
  86         * arm.h: Use ARM_CPU_FEATURE.
  87         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
  88         (arm_feature_set): Change to a structure.
  89         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
  90         ARM_FEATURE): New macros.
  91
  92 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
  93
  94         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
  95         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
  96         (ADD_PC_INCR_OPCODE): Don't define.
  97
  98 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
  99
 100         PR gas/1874
 101         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 102
 103 2005-11-14  David Ung  <davidu@mips.com>
 104
 105         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 106         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 107         save/restore encoding of the args field.
 108
 109 2005-10-28  Dave Brolley  <brolley@redhat.com>
 110
 111         Contribute the following changes:
 112         2005-02-16  Dave Brolley  <brolley@redhat.com>
 113
 114         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 115         cgen_isa_mask_* to cgen_bitset_*.
 116         * cgen.h: Likewise.
 117
 118         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 119
 120         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 121         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 122         (CGEN_CPU_TABLE): Make isas a ponter.
 123
 124         2003-09-29  Dave Brolley  <brolley@redhat.com>
 125
 126         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 127         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 128         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 129
 130         2002-12-13  Dave Brolley  <brolley@redhat.com>
 131
 132         * cgen.h (symcat.h): #include it.
 133         (cgen-bitset.h): #include it.
 134         (CGEN_ATTR_VALUE_TYPE): Now a union.
 135         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 136         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 137         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 138         * cgen-bitset.h: New file.
 139
 140 2005-09-30  Catherine Moore  <clm@cm00re.com>
 141
 142         * bfin.h: New file.
 143
 144 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 145
 146         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 147         indirect operands.
 148
 149 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 150
 151         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 152         Add FLAG_STRICT to pa10 ftest opcode.
 153
 154 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 155
 156         * hppa.h (pa_opcodes): Remove lha entries.
 157
 158 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 159
 160         * hppa.h (FLAG_STRICT): Revise comment.
 161         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 162         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 163         entries for "fdc".
 164
 165 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 166
 167         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 168
 169 2005-09-06  Chao-ying Fu  <fu@mips.com>
 170
 171         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 172         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 173         define.
 174         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 175         (INSN_ASE_MASK): Update to include INSN_MT.
 176         (INSN_MT): New define for MT ASE.
 177
 178 2005-08-25  Chao-ying Fu  <fu@mips.com>
 179
 180         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 181         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 182         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 183         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 184         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 185         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 186         instructions.
 187         (INSN_DSP): New define for DSP ASE.
 188
 189 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 190
 191         * a29k.h: Delete.
 192
 193 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 194
 195         * ppc.h (PPC_OPCODE_E300): Define.
 196
 197 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 198
 199         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 200
 201 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 202
 203         PR gas/336
 204         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 205         and pitlb.
 206
 207 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 208
 209         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 210         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 211         Add movq-s as 64-bit variants of movd-s.
 212
 213 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 214
 215         * hppa.h: Fix punctuation in comment.
 216
 217         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 218         implicit space-register addressing.  Set space-register bits on opcodes
 219         using implicit space-register addressing.  Add various missing pa20
 220         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 221         space-register addressing.  Use "fE" instead of "fe" in various
 222         fstw opcodes.
 223
 224 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 225
 226         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 227
 228 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 229
 230         * i386.h (i386_optab): Support Intel VMX Instructions.
 231
 232 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 233
 234         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 235
 236 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 237
 238         * i386.h (i386_optab): Add new insns.
 239
 240 2005-07-01  Nick Clifton  <nickc@redhat.com>
 241
 242         * sparc.h: Add typedefs to structure declarations.
 243
 244 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         PR 1013
 247         * i386.h (i386_optab): Update comments for 64bit addressing on
 248         mov. Allow 64bit addressing for mov and movq.
 249
 250 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 251
 252         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 253         respectively, in various floating-point load and store patterns.
 254
 255 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 256
 257         * hppa.h (FLAG_STRICT): Correct comment.
 258         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 259         PA 2.0 mneumonics when equivalent.  Entries with cache control
 260         completers now require PA 1.1.  Adjust whitespace.
 261
 262 2005-05-19  Anton Blanchard  <anton@samba.org>
 263
 264         * ppc.h (PPC_OPCODE_POWER5): Define.
 265
 266 2005-05-10  Nick Clifton  <nickc@redhat.com>
 267
 268         * Update the address and phone number of the FSF organization in
 269         the GPL notices in the following files:
 270         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 271         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 272         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 273         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 274         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 275         tic54x.h, tic80.h, v850.h, vax.h
 276
 277 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 278
 279         * i386.h (i386_optab): Add ht and hnt.
 280
 281 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 282
 283         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 284         Add xcrypt-ctr.  Provide aliases without hyphens.
 285
 286 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 287
 288         Moved from ../ChangeLog
 289
 290         2005-04-12  Paul Brook  <paul@codesourcery.com>
 291         * m88k.h: Rename psr macros to avoid conflicts.
 292
 293         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 294         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 295         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 296         and ARM_ARCH_V6ZKT2.
 297
 298         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 299         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 300         Remove redundant instruction types.
 301         (struct argument): X_op - new field.
 302         (struct cst4_entry): Remove.
 303         (no_op_insn): Declare.
 304
 305         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 306         * crx.h (enum argtype): Rename types, remove unused types.
 307
 308         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 309         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 310         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 311         (enum operand_type): Rearrange operands, edit comments.
 312         replace us<N> with ui<N> for unsigned immediate.
 313         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 314         displacements (respectively).
 315         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 316         (instruction type): Add NO_TYPE_INS.
 317         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 318         (operand_entry): New field - 'flags'.
 319         (operand flags): New.
 320
 321         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 322         * crx.h (operand_type): Remove redundant types i3, i4,
 323         i5, i8, i12.
 324         Add new unsigned immediate types us3, us4, us5, us16.
 325
 326 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 327
 328         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 329         adjust them accordingly.
 330
 331 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 332
 333         * i386.h (i386_optab): Add rdtscp.
 334
 335 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 338         between memory and segment register. Allow movq for moving between
 339         general-purpose register and segment register.
 340
 341 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 342
 343         PR gas/707
 344         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 345         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 346         fnstsw.
 347
 348 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 349
 350         * m68k.h (m68008, m68ec030, m68882): Remove.
 351         (m68k_mask): New.
 352         (cpu_m68k, cpu_cf): New.
 353         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 354         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 355
 356 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 357
 358         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 359         * cgen.h (enum cgen_parse_operand_type): Add
 360         CGEN_PARSE_OPERAND_SYMBOLIC.
 361
 362 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 363
 364         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 365         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 366         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 367
 368 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 369
 370         * mips.h (struct mips_opcode): Add new pinfo2 member.
 371         (INSN_ALIAS): New define for opcode table entries that are
 372         specific instances of another entry, such as 'move' for an 'or'
 373         with a zero operand.
 374         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 375         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 376
 377 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 378
 379         * mips.h (CPU_RM9000): Define.
 380         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 381
 382 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 383
 384         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 385         to/from test registers are illegal in 64-bit mode. Add missing
 386         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 387         (previously one had to explicitly encode a rex64 prefix). Re-enable
 388         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 389         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 390
 391 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 392
 393         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 394         available only with SSE2. Change the MMX additions introduced by SSE
 395         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 396         instructions by their now designated identifier (since combining i686
 397         and 3DNow! does not really imply 3DNow!A).
 398
 399 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 400
 401         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 402         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 403
 404 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 405             Vineet Sharma      <vineets@noida.hcltech.com>
 406
 407         * maxq.h: New file: Disassembly information for the maxq port.
 408
 409 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 410
 411         * i386.h (i386_optab): Put back "movzb".
 412
 413 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 414
 415         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 416         comments.  Remove member cris_ver_sim.  Add members
 417         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 418         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 419         (struct cris_support_reg, struct cris_cond15): New types.
 420         (cris_conds15): Declare.
 421         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 422         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 423         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 424         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 425         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 426         SIZE_FIELD_UNSIGNED.
 427
 428 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 429
 430         * i386.h (sldx_Suf): Remove.
 431         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 432         (q_FP): Define, implying no REX64.
 433         (x_FP, sl_FP): Imply FloatMF.
 434         (i386_optab): Split reg and mem forms of moving from segment registers
 435         so that the memory forms can ignore the 16-/32-bit operand size
 436         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 437         all non-floating-point instructions. Unite 32- and 64-bit forms of
 438         movsx, movzx, and movd. Adjust floating point operations for the above
 439         changes to the *FP macros. Add DefaultSize to floating point control
 440         insns operating on larger memory ranges. Remove left over comments
 441         hinting at certain insns being Intel-syntax ones where the ones
 442         actually meant are already gone.
 443
 444 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 445
 446         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 447         instruction type.
 448
 449 2004-09-30  Paul Brook  <paul@codesourcery.com>
 450
 451         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 452         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 453
 454 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 455
 456         * avr.h: Add support for
 457         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 458
 459 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 460
 461         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 462
 463 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 464
 465         * msp430.h (msp430_opc): Add new instructions.
 466         (msp430_rcodes): Declare new instructions.
 467         (msp430_hcodes): Likewise..
 468
 469 2004-08-13  Nick Clifton  <nickc@redhat.com>
 470
 471         PR/301
 472         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 473         processors.
 474
 475 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 476
 477         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 478
 479 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 480
 481         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 482
 483 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 484
 485         * i386.h: Adjust instruction descriptions to better match the
 486         specification.
 487
 488 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 489
 490         * arm.h: Remove all old content.  Replace with architecture defines
 491         from gas/config/tc-arm.c.
 492
 493 2004-07-09  Andreas Schwab  <schwab@suse.de>
 494
 495         * m68k.h: Fix comment.
 496
 497 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 498
 499         * crx.h: New file.
 500
 501 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 502
 503         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 504
 505 2004-05-24  Peter Barada  <peter@the-baradas.com>
 506
 507         * m68k.h: Add 'size' to m68k_opcode.
 508
 509 2004-05-05  Peter Barada  <peter@the-baradas.com>
 510
 511         * m68k.h: Switch from ColdFire chip name to core variant.
 512
 513 2004-04-22  Peter Barada  <peter@the-baradas.com>
 514
 515         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 516         descriptions for new EMAC cases.
 517         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 518         handle Motorola MAC syntax.
 519         Allow disassembly of ColdFire V4e object files.
 520
 521 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 522
 523         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 524
 525 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 526
 527         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 528
 529 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 530
 531         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 532
 533 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 534
 535         * i386.h (i386_optab): Added xstore/xcrypt insns.
 536
 537 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 538
 539         * h8300.h (32bit ldc/stc): Add relaxing support.
 540
 541 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 542
 543         * h8300.h (BITOP): Pass MEMRELAX flag.
 544
 545 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 546
 547         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 548         except for the H8S.
 549
 550 For older changes see ChangeLog-9103
 551 \f
 552 Local Variables:
 553 mode: change-log
 554 left-margin: 8
 555 fill-column: 74
 556 version-control: never
 557 End: