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* mem-break.c: Remove obsolete comment.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
1 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc.h (PPC_OPCODE_POWER8): New define.
4 (PPC_OPCODE_HTM): Likewise.
5
6 2013-01-10 Will Newton <will.newton@imgtec.com>
7
8 * metag.h: New file.
9
10 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
11
12 * cr16.h (make_instruction): Rename to cr16_make_instruction.
13 (match_opcode): Rename to cr16_match_opcode.
14
15 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
16
17 * mips.h: Add support for r5900 instructions including lq and sq.
18
19 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
20
21 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
22 (make_instruction,match_opcode): Added function prototypes.
23 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
24
25 2012-11-23 Alan Modra <amodra@gmail.com>
26
27 * ppc.h (ppc_parse_cpu): Update prototype.
28
29 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
30
31 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
32 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
33
34 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
35
36 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
37
38 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
39
40 * ia64.h (ia64_opnd): Add new operand types.
41
42 2012-08-21 David S. Miller <davem@davemloft.net>
43
44 * sparc.h (F3F4): New macro.
45
46 2012-08-13 Ian Bolton <ian.bolton@arm.com>
47 Laurent Desnogues <laurent.desnogues@arm.com>
48 Jim MacArthur <jim.macarthur@arm.com>
49 Marcus Shawcroft <marcus.shawcroft@arm.com>
50 Nigel Stephens <nigel.stephens@arm.com>
51 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
52 Richard Earnshaw <rearnsha@arm.com>
53 Sofiane Naci <sofiane.naci@arm.com>
54 Tejas Belagod <tejas.belagod@arm.com>
55 Yufeng Zhang <yufeng.zhang@arm.com>
56
57 * aarch64.h: New file.
58
59 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
60 Maciej W. Rozycki <macro@codesourcery.com>
61
62 * mips.h (mips_opcode): Add the exclusions field.
63 (OPCODE_IS_MEMBER): Remove macro.
64 (cpu_is_member): New inline function.
65 (opcode_is_member): Likewise.
66
67 2012-07-31 Chao-Ying Fu <fu@mips.com>
68 Catherine Moore <clm@codesourcery.com>
69 Maciej W. Rozycki <macro@codesourcery.com>
70
71 * mips.h: Document microMIPS DSP ASE usage.
72 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
73 microMIPS DSP ASE support.
74 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
75 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
76 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
77 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
78 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
79 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
80 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
81
82 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
83
84 * mips.h: Fix a typo in description.
85
86 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
87
88 * avr.h: (AVR_ISA_XCH): New define.
89 (AVR_ISA_XMEGA): Use it.
90 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
91
92 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
93
94 * m68hc11.h: Add XGate definitions.
95 (struct m68hc11_opcode): Add xg_mask field.
96
97 2012-05-14 Catherine Moore <clm@codesourcery.com>
98 Maciej W. Rozycki <macro@codesourcery.com>
99 Rhonda Wittels <rhonda@codesourcery.com>
100
101 * ppc.h (PPC_OPCODE_VLE): New definition.
102 (PPC_OP_SA): New macro.
103 (PPC_OP_SE_VLE): New macro.
104 (PPC_OP): Use a variable shift amount.
105 (powerpc_operand): Update comments.
106 (PPC_OPSHIFT_INV): New macro.
107 (PPC_OPERAND_CR): Replace with...
108 (PPC_OPERAND_CR_BIT): ...this and
109 (PPC_OPERAND_CR_REG): ...this.
110
111
112 2012-05-03 Sean Keys <skeys@ipdatasys.com>
113
114 * xgate.h: Header file for XGATE assembler.
115
116 2012-04-27 David S. Miller <davem@davemloft.net>
117
118 * sparc.h: Document new arg code' )' for crypto RS3
119 immediates.
120
121 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
122 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
123 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
124 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
125 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
126 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
127 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
128 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
129 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
130 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
131 HWCAP_CBCOND, HWCAP_CRC32): New defines.
132
133 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
134
135 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
136
137 2012-02-27 Alan Modra <amodra@gmail.com>
138
139 * crx.h (cst4_map): Update declaration.
140
141 2012-02-25 Walter Lee <walt@tilera.com>
142
143 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
144 TILEGX_OPC_LD_TLS.
145 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
146 TILEPRO_OPC_LW_TLS_SN.
147
148 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
149
150 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
151 (XRELEASE_PREFIX_OPCODE): Likewise.
152
153 2011-12-08 Andrew Pinski <apinski@cavium.com>
154 Adam Nemet <anemet@caviumnetworks.com>
155
156 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
157 (INSN_OCTEON2): New macro.
158 (CPU_OCTEON2): New macro.
159 (OPCODE_IS_MEMBER): Add Octeon2.
160
161 2011-11-29 Andrew Pinski <apinski@cavium.com>
162
163 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
164 (INSN_OCTEONP): New macro.
165 (CPU_OCTEONP): New macro.
166 (OPCODE_IS_MEMBER): Add Octeon+.
167 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
168
169 2011-11-01 DJ Delorie <dj@redhat.com>
170
171 * rl78.h: New file.
172
173 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
174
175 * mips.h: Fix a typo in description.
176
177 2011-09-21 David S. Miller <davem@davemloft.net>
178
179 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
180 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
181 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
182 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
183
184 2011-08-09 Chao-ying Fu <fu@mips.com>
185 Maciej W. Rozycki <macro@codesourcery.com>
186
187 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
188 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
189 (INSN_ASE_MASK): Add the MCU bit.
190 (INSN_MCU): New macro.
191 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
192 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
193
194 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
195
196 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
197 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
198 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
199 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
200 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
201 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
202 (INSN2_READ_GPR_MMN): Likewise.
203 (INSN2_READ_FPR_D): Change the bit used.
204 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
205 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
206 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
207 (INSN2_COND_BRANCH): Likewise.
208 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
209 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
210 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
211 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
212 (INSN2_MOD_GPR_MN): Likewise.
213
214 2011-08-05 David S. Miller <davem@davemloft.net>
215
216 * sparc.h: Document new format codes '4', '5', and '('.
217 (OPF_LOW4, RS3): New macros.
218
219 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
220
221 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
222 order of flags documented.
223
224 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
225
226 * mips.h: Clarify the description of microMIPS instruction
227 manipulation macros.
228 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
229
230 2011-07-24 Chao-ying Fu <fu@mips.com>
231 Maciej W. Rozycki <macro@codesourcery.com>
232
233 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
234 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
235 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
236 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
237 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
238 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
239 (OP_MASK_RS3, OP_SH_RS3): Likewise.
240 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
241 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
242 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
243 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
244 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
245 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
246 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
247 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
248 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
249 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
250 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
251 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
252 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
253 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
254 (INSN_WRITE_GPR_S): New macro.
255 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
256 (INSN2_READ_FPR_D): Likewise.
257 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
258 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
259 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
260 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
261 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
262 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
263 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
264 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
265 (CPU_MICROMIPS): New macro.
266 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
267 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
268 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
269 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
270 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
271 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
272 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
273 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
274 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
275 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
276 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
277 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
278 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
279 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
280 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
281 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
282 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
283 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
284 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
285 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
286 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
287 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
288 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
289 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
290 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
291 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
292 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
293 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
294 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
295 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
296 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
297 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
298 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
299 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
300 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
301 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
302 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
303 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
304 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
305 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
306 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
307 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
308 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
309 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
310 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
311 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
312 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
313 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
314 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
315 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
316 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
317 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
318 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
319 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
320 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
321 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
322 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
323 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
324 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
325 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
326 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
327 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
328 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
329 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
330 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
331 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
332 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
333 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
334 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
335 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
336 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
337 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
338 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
339 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
340 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
341 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
342 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
343 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
344 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
345 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
346 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
347 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
348 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
349 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
350 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
351 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
352 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
353 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
354 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
355 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
356 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
357 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
358 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
359 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
360 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
361 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
362 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
363 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
364 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
365 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
366 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
367 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
368 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
369 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
370 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
371 (micromips_opcodes): New declaration.
372 (bfd_micromips_num_opcodes): Likewise.
373
374 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
375
376 * mips.h (INSN_TRAP): Rename to...
377 (INSN_NO_DELAY_SLOT): ... this.
378 (INSN_SYNC): Remove macro.
379
380 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
381
382 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
383 a duplicate of AVR_ISA_SPM.
384
385 2011-07-01 Nick Clifton <nickc@redhat.com>
386
387 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
388
389 2011-06-18 Robin Getz <robin.getz@analog.com>
390
391 * bfin.h (is_macmod_signed): New func
392
393 2011-06-18 Mike Frysinger <vapier@gentoo.org>
394
395 * bfin.h (is_macmod_pmove): Add missing space before func args.
396 (is_macmod_hmove): Likewise.
397
398 2011-06-13 Walter Lee <walt@tilera.com>
399
400 * tilegx.h: New file.
401 * tilepro.h: New file.
402
403 2011-05-31 Paul Brook <paul@codesourcery.com>
404
405 * arm.h (ARM_ARCH_V7R_IDIV): Define.
406
407 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
408
409 * s390.h: Replace S390_OPERAND_REG_EVEN with
410 S390_OPERAND_REG_PAIR.
411
412 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
413
414 * s390.h: Add S390_OPCODE_REG_EVEN flag.
415
416 2011-04-18 Julian Brown <julian@codesourcery.com>
417
418 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
419
420 2011-04-11 Dan McDonald <dan@wellkeeper.com>
421
422 PR gas/12296
423 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
424
425 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
426
427 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
428 New instruction set flags.
429 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
430
431 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
432
433 * mips.h (M_PREF_AB): New enum value.
434
435 2011-02-12 Mike Frysinger <vapier@gentoo.org>
436
437 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
438 M_IU): Define.
439 (is_macmod_pmove, is_macmod_hmove): New functions.
440
441 2011-02-11 Mike Frysinger <vapier@gentoo.org>
442
443 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
444
445 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
446
447 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
448 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
449
450 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
451
452 PR gas/11395
453 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
454 "bb" entries.
455
456 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
457
458 PR gas/11395
459 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
460
461 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
462
463 * mips.h: Update commentary after last commit.
464
465 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
466
467 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
468 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
469 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
470
471 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
472
473 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
474
475 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
476
477 * mips.h: Fix previous commit.
478
479 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
480
481 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
482 (INSN_LOONGSON_3A): Clear bit 31.
483
484 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
485
486 PR gas/12198
487 * arm.h (ARM_AEXT_V6M_ONLY): New define.
488 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
489 (ARM_ARCH_V6M_ONLY): New define.
490
491 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
492
493 * mips.h (INSN_LOONGSON_3A): Defined.
494 (CPU_LOONGSON_3A): Defined.
495 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
496
497 2010-10-09 Matt Rice <ratmice@gmail.com>
498
499 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
500 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
501
502 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
503
504 * arm.h (ARM_EXT_VIRT): New define.
505 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
506 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
507 Extensions.
508
509 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
510
511 * arm.h (ARM_AEXT_ADIV): New define.
512 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
513
514 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
515
516 * arm.h (ARM_EXT_OS): New define.
517 (ARM_AEXT_V6SM): Likewise.
518 (ARM_ARCH_V6SM): Likewise.
519
520 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
521
522 * arm.h (ARM_EXT_MP): Add.
523 (ARM_ARCH_V7A_MP): Likewise.
524
525 2010-09-22 Mike Frysinger <vapier@gentoo.org>
526
527 * bfin.h: Declare pseudoChr structs/defines.
528
529 2010-09-21 Mike Frysinger <vapier@gentoo.org>
530
531 * bfin.h: Strip trailing whitespace.
532
533 2010-07-29 DJ Delorie <dj@redhat.com>
534
535 * rx.h (RX_Operand_Type): Add TwoReg.
536 (RX_Opcode_ID): Remove ediv and ediv2.
537
538 2010-07-27 DJ Delorie <dj@redhat.com>
539
540 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
541
542 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
543 Ina Pandit <ina.pandit@kpitcummins.com>
544
545 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
546 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
547 PROCESSOR_V850E2_ALL.
548 Remove PROCESSOR_V850EA support.
549 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
550 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
551 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
552 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
553 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
554 V850_OPERAND_PERCENT.
555 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
556 V850_NOT_R0.
557 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
558 and V850E_PUSH_POP
559
560 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
561
562 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
563 (MIPS16_INSN_BRANCH): Rename to...
564 (MIPS16_INSN_COND_BRANCH): ... this.
565
566 2010-07-03 Alan Modra <amodra@gmail.com>
567
568 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
569 Renumber other PPC_OPCODE defines.
570
571 2010-07-03 Alan Modra <amodra@gmail.com>
572
573 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
574
575 2010-06-29 Alan Modra <amodra@gmail.com>
576
577 * maxq.h: Delete file.
578
579 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
580
581 * ppc.h (PPC_OPCODE_E500): Define.
582
583 2010-05-26 Catherine Moore <clm@codesourcery.com>
584
585 * opcode/mips.h (INSN_MIPS16): Remove.
586
587 2010-04-21 Joseph Myers <joseph@codesourcery.com>
588
589 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
590
591 2010-04-15 Nick Clifton <nickc@redhat.com>
592
593 * alpha.h: Update copyright notice to use GPLv3.
594 * arc.h: Likewise.
595 * arm.h: Likewise.
596 * avr.h: Likewise.
597 * bfin.h: Likewise.
598 * cgen.h: Likewise.
599 * convex.h: Likewise.
600 * cr16.h: Likewise.
601 * cris.h: Likewise.
602 * crx.h: Likewise.
603 * d10v.h: Likewise.
604 * d30v.h: Likewise.
605 * dlx.h: Likewise.
606 * h8300.h: Likewise.
607 * hppa.h: Likewise.
608 * i370.h: Likewise.
609 * i386.h: Likewise.
610 * i860.h: Likewise.
611 * i960.h: Likewise.
612 * ia64.h: Likewise.
613 * m68hc11.h: Likewise.
614 * m68k.h: Likewise.
615 * m88k.h: Likewise.
616 * maxq.h: Likewise.
617 * mips.h: Likewise.
618 * mmix.h: Likewise.
619 * mn10200.h: Likewise.
620 * mn10300.h: Likewise.
621 * msp430.h: Likewise.
622 * np1.h: Likewise.
623 * ns32k.h: Likewise.
624 * or32.h: Likewise.
625 * pdp11.h: Likewise.
626 * pj.h: Likewise.
627 * pn.h: Likewise.
628 * ppc.h: Likewise.
629 * pyr.h: Likewise.
630 * rx.h: Likewise.
631 * s390.h: Likewise.
632 * score-datadep.h: Likewise.
633 * score-inst.h: Likewise.
634 * sparc.h: Likewise.
635 * spu-insns.h: Likewise.
636 * spu.h: Likewise.
637 * tic30.h: Likewise.
638 * tic4x.h: Likewise.
639 * tic54x.h: Likewise.
640 * tic80.h: Likewise.
641 * v850.h: Likewise.
642 * vax.h: Likewise.
643
644 2010-03-25 Joseph Myers <joseph@codesourcery.com>
645
646 * tic6x-control-registers.h, tic6x-insn-formats.h,
647 tic6x-opcode-table.h, tic6x.h: New.
648
649 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
650
651 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
652
653 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
654
655 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
656
657 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
658
659 * ia64.h (ia64_find_opcode): Remove argument name.
660 (ia64_find_next_opcode): Likewise.
661 (ia64_dis_opcode): Likewise.
662 (ia64_free_opcode): Likewise.
663 (ia64_find_dependency): Likewise.
664
665 2009-11-22 Doug Evans <dje@sebabeach.org>
666
667 * cgen.h: Include bfd_stdint.h.
668 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
669
670 2009-11-18 Paul Brook <paul@codesourcery.com>
671
672 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
673
674 2009-11-17 Paul Brook <paul@codesourcery.com>
675 Daniel Jacobowitz <dan@codesourcery.com>
676
677 * arm.h (ARM_EXT_V6_DSP): Define.
678 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
679 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
680
681 2009-11-04 DJ Delorie <dj@redhat.com>
682
683 * rx.h (rx_decode_opcode) (mvtipl): Add.
684 (mvtcp, mvfcp, opecp): Remove.
685
686 2009-11-02 Paul Brook <paul@codesourcery.com>
687
688 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
689 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
690 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
691 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
692 FPU_ARCH_NEON_VFP_V4): Define.
693
694 2009-10-23 Doug Evans <dje@sebabeach.org>
695
696 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
697 * cgen.h: Update. Improve multi-inclusion macro name.
698
699 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
700
701 * ppc.h (PPC_OPCODE_476): Define.
702
703 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
704
705 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
706
707 2009-09-29 DJ Delorie <dj@redhat.com>
708
709 * rx.h: New file.
710
711 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
712
713 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
714
715 2009-09-21 Ben Elliston <bje@au.ibm.com>
716
717 * ppc.h (PPC_OPCODE_PPCA2): New.
718
719 2009-09-05 Martin Thuresson <martin@mtme.org>
720
721 * ia64.h (struct ia64_operand): Renamed member class to op_class.
722
723 2009-08-29 Martin Thuresson <martin@mtme.org>
724
725 * tic30.h (template): Rename type template to
726 insn_template. Updated code to use new name.
727 * tic54x.h (template): Rename type template to
728 insn_template.
729
730 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
731
732 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
733
734 2009-06-11 Anthony Green <green@moxielogic.com>
735
736 * moxie.h (MOXIE_F3_PCREL): Define.
737 (moxie_form3_opc_info): Grow.
738
739 2009-06-06 Anthony Green <green@moxielogic.com>
740
741 * moxie.h (MOXIE_F1_M): Define.
742
743 2009-04-15 Anthony Green <green@moxielogic.com>
744
745 * moxie.h: Created.
746
747 2009-04-06 DJ Delorie <dj@redhat.com>
748
749 * h8300.h: Add relaxation attributes to MOVA opcodes.
750
751 2009-03-10 Alan Modra <amodra@bigpond.net.au>
752
753 * ppc.h (ppc_parse_cpu): Declare.
754
755 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
756
757 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
758 and _IMM11 for mbitclr and mbitset.
759 * score-datadep.h: Update dependency information.
760
761 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
762
763 * ppc.h (PPC_OPCODE_POWER7): New.
764
765 2009-02-06 Doug Evans <dje@google.com>
766
767 * i386.h: Add comment regarding sse* insns and prefixes.
768
769 2009-02-03 Sandip Matte <sandip@rmicorp.com>
770
771 * mips.h (INSN_XLR): Define.
772 (INSN_CHIP_MASK): Update.
773 (CPU_XLR): Define.
774 (OPCODE_IS_MEMBER): Update.
775 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
776
777 2009-01-28 Doug Evans <dje@google.com>
778
779 * opcode/i386.h: Add multiple inclusion protection.
780 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
781 (EDI_REG_NUM): New macros.
782 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
783 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
784 (REX_PREFIX_P): New macro.
785
786 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
787
788 * ppc.h (struct powerpc_opcode): New field "deprecated".
789 (PPC_OPCODE_NOPOWER4): Delete.
790
791 2008-11-28 Joshua Kinard <kumba@gentoo.org>
792
793 * mips.h: Define CPU_R14000, CPU_R16000.
794 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
795
796 2008-11-18 Catherine Moore <clm@codesourcery.com>
797
798 * arm.h (FPU_NEON_FP16): New.
799 (FPU_ARCH_NEON_FP16): New.
800
801 2008-11-06 Chao-ying Fu <fu@mips.com>
802
803 * mips.h: Doucument '1' for 5-bit sync type.
804
805 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
806
807 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
808 IA64_RS_CR.
809
810 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
811
812 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
813
814 2008-07-30 Michael J. Eager <eager@eagercon.com>
815
816 * ppc.h (PPC_OPCODE_405): Define.
817 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
818
819 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
820
821 * ppc.h (ppc_cpu_t): New typedef.
822 (struct powerpc_opcode <flags>): Use it.
823 (struct powerpc_operand <insert, extract>): Likewise.
824 (struct powerpc_macro <flags>): Likewise.
825
826 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
827
828 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
829 Update comment before MIPS16 field descriptors to mention MIPS16.
830 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
831 BBIT.
832 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
833 New bit masks and shift counts for cins and exts.
834
835 * mips.h: Document new field descriptors +Q.
836 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
837
838 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
839
840 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
841 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
842
843 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
844
845 * ppc.h: (PPC_OPCODE_E500MC): New.
846
847 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
848
849 * i386.h (MAX_OPERANDS): Set to 5.
850 (MAX_MNEM_SIZE): Changed to 20.
851
852 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
853
854 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
855
856 2008-03-09 Paul Brook <paul@codesourcery.com>
857
858 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
859
860 2008-03-04 Paul Brook <paul@codesourcery.com>
861
862 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
863 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
864 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
865
866 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
867 Nick Clifton <nickc@redhat.com>
868
869 PR 3134
870 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
871 with a 32-bit displacement but without the top bit of the 4th byte
872 set.
873
874 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
875
876 * cr16.h (cr16_num_optab): Declared.
877
878 2008-02-14 Hakan Ardo <hakan@debian.org>
879
880 PR gas/2626
881 * avr.h (AVR_ISA_2xxe): Define.
882
883 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
884
885 * mips.h: Update copyright.
886 (INSN_CHIP_MASK): New macro.
887 (INSN_OCTEON): New macro.
888 (CPU_OCTEON): New macro.
889 (OPCODE_IS_MEMBER): Handle Octeon instructions.
890
891 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
892
893 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
894
895 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
896
897 * avr.h (AVR_ISA_USB162): Add new opcode set.
898 (AVR_ISA_AVR3): Likewise.
899
900 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
901
902 * mips.h (INSN_LOONGSON_2E): New.
903 (INSN_LOONGSON_2F): New.
904 (CPU_LOONGSON_2E): New.
905 (CPU_LOONGSON_2F): New.
906 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
907
908 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
909
910 * mips.h (INSN_ISA*): Redefine certain values as an
911 enumeration. Update comments.
912 (mips_isa_table): New.
913 (ISA_MIPS*): Redefine to match enumeration.
914 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
915 values.
916
917 2007-08-08 Ben Elliston <bje@au.ibm.com>
918
919 * ppc.h (PPC_OPCODE_PPCPS): New.
920
921 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
922
923 * m68k.h: Document j K & E.
924
925 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
926
927 * cr16.h: New file for CR16 target.
928
929 2007-05-02 Alan Modra <amodra@bigpond.net.au>
930
931 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
932
933 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
934
935 * m68k.h (mcfisa_c): New.
936 (mcfusp, mcf_mask): Adjust.
937
938 2007-04-20 Alan Modra <amodra@bigpond.net.au>
939
940 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
941 (num_powerpc_operands): Declare.
942 (PPC_OPERAND_SIGNED et al): Redefine as hex.
943 (PPC_OPERAND_PLUS1): Define.
944
945 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
946
947 * i386.h (REX_MODE64): Renamed to ...
948 (REX_W): This.
949 (REX_EXTX): Renamed to ...
950 (REX_R): This.
951 (REX_EXTY): Renamed to ...
952 (REX_X): This.
953 (REX_EXTZ): Renamed to ...
954 (REX_B): This.
955
956 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
957
958 * i386.h: Add entries from config/tc-i386.h and move tables
959 to opcodes/i386-opc.h.
960
961 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
962
963 * i386.h (FloatDR): Removed.
964 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
965
966 2007-03-01 Alan Modra <amodra@bigpond.net.au>
967
968 * spu-insns.h: Add soma double-float insns.
969
970 2007-02-20 Thiemo Seufer <ths@mips.com>
971 Chao-Ying Fu <fu@mips.com>
972
973 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
974 (INSN_DSPR2): Add flag for DSP R2 instructions.
975 (M_BALIGN): New macro.
976
977 2007-02-14 Alan Modra <amodra@bigpond.net.au>
978
979 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
980 and Seg3ShortFrom with Shortform.
981
982 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
983
984 PR gas/4027
985 * i386.h (i386_optab): Put the real "test" before the pseudo
986 one.
987
988 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
989
990 * m68k.h (m68010up): OR fido_a.
991
992 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
993
994 * m68k.h (fido_a): New.
995
996 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
997
998 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
999 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1000 values.
1001
1002 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1003
1004 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1005
1006 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1007
1008 * score-inst.h (enum score_insn_type): Add Insn_internal.
1009
1010 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1011 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1012 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1013 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1014 Alan Modra <amodra@bigpond.net.au>
1015
1016 * spu-insns.h: New file.
1017 * spu.h: New file.
1018
1019 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1020
1021 * ppc.h (PPC_OPCODE_CELL): Define.
1022
1023 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1024
1025 * i386.h : Modify opcode to support for the change in POPCNT opcode
1026 in amdfam10 architecture.
1027
1028 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1029
1030 * i386.h: Replace CpuMNI with CpuSSSE3.
1031
1032 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1033 Joseph Myers <joseph@codesourcery.com>
1034 Ian Lance Taylor <ian@wasabisystems.com>
1035 Ben Elliston <bje@wasabisystems.com>
1036
1037 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1038
1039 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1040
1041 * score-datadep.h: New file.
1042 * score-inst.h: New file.
1043
1044 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1045
1046 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1047 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1048 movdq2q and movq2dq.
1049
1050 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1051 Michael Meissner <michael.meissner@amd.com>
1052
1053 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1054
1055 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1056
1057 * i386.h (i386_optab): Add "nop" with memory reference.
1058
1059 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1060
1061 * i386.h (i386_optab): Update comment for 64bit NOP.
1062
1063 2006-06-06 Ben Elliston <bje@au.ibm.com>
1064 Anton Blanchard <anton@samba.org>
1065
1066 * ppc.h (PPC_OPCODE_POWER6): Define.
1067 Adjust whitespace.
1068
1069 2006-06-05 Thiemo Seufer <ths@mips.com>
1070
1071 * mips.h: Improve description of MT flags.
1072
1073 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1074
1075 * m68k.h (mcf_mask): Define.
1076
1077 2006-05-05 Thiemo Seufer <ths@mips.com>
1078 David Ung <davidu@mips.com>
1079
1080 * mips.h (enum): Add macro M_CACHE_AB.
1081
1082 2006-05-04 Thiemo Seufer <ths@mips.com>
1083 Nigel Stephens <nigel@mips.com>
1084 David Ung <davidu@mips.com>
1085
1086 * mips.h: Add INSN_SMARTMIPS define.
1087
1088 2006-04-30 Thiemo Seufer <ths@mips.com>
1089 David Ung <davidu@mips.com>
1090
1091 * mips.h: Defines udi bits and masks. Add description of
1092 characters which may appear in the args field of udi
1093 instructions.
1094
1095 2006-04-26 Thiemo Seufer <ths@networkno.de>
1096
1097 * mips.h: Improve comments describing the bitfield instruction
1098 fields.
1099
1100 2006-04-26 Julian Brown <julian@codesourcery.com>
1101
1102 * arm.h (FPU_VFP_EXT_V3): Define constant.
1103 (FPU_NEON_EXT_V1): Likewise.
1104 (FPU_VFP_HARD): Update.
1105 (FPU_VFP_V3): Define macro.
1106 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1107
1108 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1109
1110 * avr.h (AVR_ISA_PWMx): New.
1111
1112 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1113
1114 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1115 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1116 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1117 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1118 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1119
1120 2006-03-10 Paul Brook <paul@codesourcery.com>
1121
1122 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1123
1124 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1125
1126 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1127 first. Correct mask of bb "B" opcode.
1128
1129 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1130
1131 * i386.h (i386_optab): Support Intel Merom New Instructions.
1132
1133 2006-02-24 Paul Brook <paul@codesourcery.com>
1134
1135 * arm.h: Add V7 feature bits.
1136
1137 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1138
1139 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1140
1141 2006-01-31 Paul Brook <paul@codesourcery.com>
1142 Richard Earnshaw <rearnsha@arm.com>
1143
1144 * arm.h: Use ARM_CPU_FEATURE.
1145 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1146 (arm_feature_set): Change to a structure.
1147 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1148 ARM_FEATURE): New macros.
1149
1150 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1151
1152 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1153 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1154 (ADD_PC_INCR_OPCODE): Don't define.
1155
1156 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1157
1158 PR gas/1874
1159 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1160
1161 2005-11-14 David Ung <davidu@mips.com>
1162
1163 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1164 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1165 save/restore encoding of the args field.
1166
1167 2005-10-28 Dave Brolley <brolley@redhat.com>
1168
1169 Contribute the following changes:
1170 2005-02-16 Dave Brolley <brolley@redhat.com>
1171
1172 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1173 cgen_isa_mask_* to cgen_bitset_*.
1174 * cgen.h: Likewise.
1175
1176 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1177
1178 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1179 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1180 (CGEN_CPU_TABLE): Make isas a ponter.
1181
1182 2003-09-29 Dave Brolley <brolley@redhat.com>
1183
1184 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1185 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1186 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1187
1188 2002-12-13 Dave Brolley <brolley@redhat.com>
1189
1190 * cgen.h (symcat.h): #include it.
1191 (cgen-bitset.h): #include it.
1192 (CGEN_ATTR_VALUE_TYPE): Now a union.
1193 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1194 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1195 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1196 * cgen-bitset.h: New file.
1197
1198 2005-09-30 Catherine Moore <clm@cm00re.com>
1199
1200 * bfin.h: New file.
1201
1202 2005-10-24 Jan Beulich <jbeulich@novell.com>
1203
1204 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1205 indirect operands.
1206
1207 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1208
1209 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1210 Add FLAG_STRICT to pa10 ftest opcode.
1211
1212 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1213
1214 * hppa.h (pa_opcodes): Remove lha entries.
1215
1216 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1217
1218 * hppa.h (FLAG_STRICT): Revise comment.
1219 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1220 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1221 entries for "fdc".
1222
1223 2005-09-30 Catherine Moore <clm@cm00re.com>
1224
1225 * bfin.h: New file.
1226
1227 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1228
1229 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1230
1231 2005-09-06 Chao-ying Fu <fu@mips.com>
1232
1233 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1234 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1235 define.
1236 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1237 (INSN_ASE_MASK): Update to include INSN_MT.
1238 (INSN_MT): New define for MT ASE.
1239
1240 2005-08-25 Chao-ying Fu <fu@mips.com>
1241
1242 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1243 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1244 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1245 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1246 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1247 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1248 instructions.
1249 (INSN_DSP): New define for DSP ASE.
1250
1251 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1252
1253 * a29k.h: Delete.
1254
1255 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1256
1257 * ppc.h (PPC_OPCODE_E300): Define.
1258
1259 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1260
1261 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1262
1263 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1264
1265 PR gas/336
1266 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1267 and pitlb.
1268
1269 2005-07-27 Jan Beulich <jbeulich@novell.com>
1270
1271 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1272 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1273 Add movq-s as 64-bit variants of movd-s.
1274
1275 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1276
1277 * hppa.h: Fix punctuation in comment.
1278
1279 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1280 implicit space-register addressing. Set space-register bits on opcodes
1281 using implicit space-register addressing. Add various missing pa20
1282 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1283 space-register addressing. Use "fE" instead of "fe" in various
1284 fstw opcodes.
1285
1286 2005-07-18 Jan Beulich <jbeulich@novell.com>
1287
1288 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1289
1290 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1291
1292 * i386.h (i386_optab): Support Intel VMX Instructions.
1293
1294 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1295
1296 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1297
1298 2005-07-05 Jan Beulich <jbeulich@novell.com>
1299
1300 * i386.h (i386_optab): Add new insns.
1301
1302 2005-07-01 Nick Clifton <nickc@redhat.com>
1303
1304 * sparc.h: Add typedefs to structure declarations.
1305
1306 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1307
1308 PR 1013
1309 * i386.h (i386_optab): Update comments for 64bit addressing on
1310 mov. Allow 64bit addressing for mov and movq.
1311
1312 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1313
1314 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1315 respectively, in various floating-point load and store patterns.
1316
1317 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1318
1319 * hppa.h (FLAG_STRICT): Correct comment.
1320 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1321 PA 2.0 mneumonics when equivalent. Entries with cache control
1322 completers now require PA 1.1. Adjust whitespace.
1323
1324 2005-05-19 Anton Blanchard <anton@samba.org>
1325
1326 * ppc.h (PPC_OPCODE_POWER5): Define.
1327
1328 2005-05-10 Nick Clifton <nickc@redhat.com>
1329
1330 * Update the address and phone number of the FSF organization in
1331 the GPL notices in the following files:
1332 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1333 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1334 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1335 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1336 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1337 tic54x.h, tic80.h, v850.h, vax.h
1338
1339 2005-05-09 Jan Beulich <jbeulich@novell.com>
1340
1341 * i386.h (i386_optab): Add ht and hnt.
1342
1343 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1344
1345 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1346 Add xcrypt-ctr. Provide aliases without hyphens.
1347
1348 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1349
1350 Moved from ../ChangeLog
1351
1352 2005-04-12 Paul Brook <paul@codesourcery.com>
1353 * m88k.h: Rename psr macros to avoid conflicts.
1354
1355 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1356 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1357 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1358 and ARM_ARCH_V6ZKT2.
1359
1360 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1361 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1362 Remove redundant instruction types.
1363 (struct argument): X_op - new field.
1364 (struct cst4_entry): Remove.
1365 (no_op_insn): Declare.
1366
1367 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1368 * crx.h (enum argtype): Rename types, remove unused types.
1369
1370 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1371 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1372 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1373 (enum operand_type): Rearrange operands, edit comments.
1374 replace us<N> with ui<N> for unsigned immediate.
1375 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1376 displacements (respectively).
1377 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1378 (instruction type): Add NO_TYPE_INS.
1379 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1380 (operand_entry): New field - 'flags'.
1381 (operand flags): New.
1382
1383 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1384 * crx.h (operand_type): Remove redundant types i3, i4,
1385 i5, i8, i12.
1386 Add new unsigned immediate types us3, us4, us5, us16.
1387
1388 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1389
1390 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1391 adjust them accordingly.
1392
1393 2005-04-01 Jan Beulich <jbeulich@novell.com>
1394
1395 * i386.h (i386_optab): Add rdtscp.
1396
1397 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1398
1399 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1400 between memory and segment register. Allow movq for moving between
1401 general-purpose register and segment register.
1402
1403 2005-02-09 Jan Beulich <jbeulich@novell.com>
1404
1405 PR gas/707
1406 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1407 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1408 fnstsw.
1409
1410 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1411
1412 * m68k.h (m68008, m68ec030, m68882): Remove.
1413 (m68k_mask): New.
1414 (cpu_m68k, cpu_cf): New.
1415 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1416 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1417
1418 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1419
1420 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1421 * cgen.h (enum cgen_parse_operand_type): Add
1422 CGEN_PARSE_OPERAND_SYMBOLIC.
1423
1424 2005-01-21 Fred Fish <fnf@specifixinc.com>
1425
1426 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1427 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1428 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1429
1430 2005-01-19 Fred Fish <fnf@specifixinc.com>
1431
1432 * mips.h (struct mips_opcode): Add new pinfo2 member.
1433 (INSN_ALIAS): New define for opcode table entries that are
1434 specific instances of another entry, such as 'move' for an 'or'
1435 with a zero operand.
1436 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1437 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1438
1439 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1440
1441 * mips.h (CPU_RM9000): Define.
1442 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1443
1444 2004-11-25 Jan Beulich <jbeulich@novell.com>
1445
1446 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1447 to/from test registers are illegal in 64-bit mode. Add missing
1448 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1449 (previously one had to explicitly encode a rex64 prefix). Re-enable
1450 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1451 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1452
1453 2004-11-23 Jan Beulich <jbeulich@novell.com>
1454
1455 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1456 available only with SSE2. Change the MMX additions introduced by SSE
1457 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1458 instructions by their now designated identifier (since combining i686
1459 and 3DNow! does not really imply 3DNow!A).
1460
1461 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1462
1463 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1464 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1465
1466 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1467 Vineet Sharma <vineets@noida.hcltech.com>
1468
1469 * maxq.h: New file: Disassembly information for the maxq port.
1470
1471 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1472
1473 * i386.h (i386_optab): Put back "movzb".
1474
1475 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1476
1477 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1478 comments. Remove member cris_ver_sim. Add members
1479 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1480 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1481 (struct cris_support_reg, struct cris_cond15): New types.
1482 (cris_conds15): Declare.
1483 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1484 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1485 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1486 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1487 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1488 SIZE_FIELD_UNSIGNED.
1489
1490 2004-11-04 Jan Beulich <jbeulich@novell.com>
1491
1492 * i386.h (sldx_Suf): Remove.
1493 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1494 (q_FP): Define, implying no REX64.
1495 (x_FP, sl_FP): Imply FloatMF.
1496 (i386_optab): Split reg and mem forms of moving from segment registers
1497 so that the memory forms can ignore the 16-/32-bit operand size
1498 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1499 all non-floating-point instructions. Unite 32- and 64-bit forms of
1500 movsx, movzx, and movd. Adjust floating point operations for the above
1501 changes to the *FP macros. Add DefaultSize to floating point control
1502 insns operating on larger memory ranges. Remove left over comments
1503 hinting at certain insns being Intel-syntax ones where the ones
1504 actually meant are already gone.
1505
1506 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1507
1508 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1509 instruction type.
1510
1511 2004-09-30 Paul Brook <paul@codesourcery.com>
1512
1513 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1514 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1515
1516 2004-09-11 Theodore A. Roth <troth@openavr.org>
1517
1518 * avr.h: Add support for
1519 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1520
1521 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1522
1523 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1524
1525 2004-08-24 Dmitry Diky <diwil@spec.ru>
1526
1527 * msp430.h (msp430_opc): Add new instructions.
1528 (msp430_rcodes): Declare new instructions.
1529 (msp430_hcodes): Likewise..
1530
1531 2004-08-13 Nick Clifton <nickc@redhat.com>
1532
1533 PR/301
1534 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1535 processors.
1536
1537 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1538
1539 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1540
1541 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1542
1543 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1544
1545 2004-07-21 Jan Beulich <jbeulich@novell.com>
1546
1547 * i386.h: Adjust instruction descriptions to better match the
1548 specification.
1549
1550 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1551
1552 * arm.h: Remove all old content. Replace with architecture defines
1553 from gas/config/tc-arm.c.
1554
1555 2004-07-09 Andreas Schwab <schwab@suse.de>
1556
1557 * m68k.h: Fix comment.
1558
1559 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1560
1561 * crx.h: New file.
1562
1563 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1564
1565 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1566
1567 2004-05-24 Peter Barada <peter@the-baradas.com>
1568
1569 * m68k.h: Add 'size' to m68k_opcode.
1570
1571 2004-05-05 Peter Barada <peter@the-baradas.com>
1572
1573 * m68k.h: Switch from ColdFire chip name to core variant.
1574
1575 2004-04-22 Peter Barada <peter@the-baradas.com>
1576
1577 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1578 descriptions for new EMAC cases.
1579 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1580 handle Motorola MAC syntax.
1581 Allow disassembly of ColdFire V4e object files.
1582
1583 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1584
1585 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1586
1587 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1588
1589 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1590
1591 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1592
1593 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1594
1595 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1596
1597 * i386.h (i386_optab): Added xstore/xcrypt insns.
1598
1599 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1600
1601 * h8300.h (32bit ldc/stc): Add relaxing support.
1602
1603 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1604
1605 * h8300.h (BITOP): Pass MEMRELAX flag.
1606
1607 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1608
1609 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1610 except for the H8S.
1611
1612 For older changes see ChangeLog-9103
1613 \f
1614 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1615
1616 Copying and distribution of this file, with or without modification,
1617 are permitted in any medium without royalty provided the copyright
1618 notice and this notice are preserved.
1619
1620 Local Variables:
1621 mode: change-log
1622 left-margin: 8
1623 fill-column: 74
1624 version-control: never
1625 End:
GDB Binutils - Deliverables
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