1 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
3 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
5 2015-01-01 Alan Modra <amodra@gmail.com>
7 Update year range in copyright notice of all files.
9 2014-12-27 Anthony Green <green@moxielogic.com>
11 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
12 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
14 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
18 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
20 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
21 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
22 (NIOS2_INSN_OPTARG): Renumber.
24 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
26 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
27 declaration. Fix obsolete comment.
29 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
31 * nios2.h (enum iw_format_type): New.
32 (struct nios2_opcode): Update comments. Add size and format fields.
33 (NIOS2_INSN_OPTARG): New.
34 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
35 (struct nios2_reg): Add regtype field.
36 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
37 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
38 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
39 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
40 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
41 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
42 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
43 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
44 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
45 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
46 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
47 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
48 (OP_MASK_OP, OP_SH_OP): Delete.
49 (OP_MASK_IOP, OP_SH_IOP): Delete.
50 (OP_MASK_IRD, OP_SH_IRD): Delete.
51 (OP_MASK_IRT, OP_SH_IRT): Delete.
52 (OP_MASK_IRS, OP_SH_IRS): Delete.
53 (OP_MASK_ROP, OP_SH_ROP): Delete.
54 (OP_MASK_RRD, OP_SH_RRD): Delete.
55 (OP_MASK_RRT, OP_SH_RRT): Delete.
56 (OP_MASK_RRS, OP_SH_RRS): Delete.
57 (OP_MASK_JOP, OP_SH_JOP): Delete.
58 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
59 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
60 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
61 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
62 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
63 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
64 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
65 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
66 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
67 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
68 (OP_MASK_<insn>, OP_MASK): Delete.
69 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
70 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
71 Include nios2r1.h to define new instruction opcode constants
73 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
74 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
75 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
76 (NUMOPCODES, NUMREGISTERS): Delete.
77 * nios2r1.h: New file.
79 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
81 * sparc.h (HWCAP2_VIS3B): Documentation improved.
83 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
85 * sparc.h (sparc_opcode): new field `hwcaps2'.
86 (HWCAP2_FJATHPLUS): New define.
87 (HWCAP2_VIS3B): Likewise.
88 (HWCAP2_ADP): Likewise.
89 (HWCAP2_SPARC5): Likewise.
90 (HWCAP2_MWAIT): Likewise.
91 (HWCAP2_XMPMUL): Likewise.
92 (HWCAP2_XMONT): Likewise.
93 (HWCAP2_NSEC): Likewise.
94 (HWCAP2_FJATHHPC): Likewise.
95 (HWCAP2_FJDES): Likewise.
96 (HWCAP2_FJAES): Likewise.
97 Document the new operand kind `{', corresponding to the mcdper
98 ancillary state register.
99 Document the new operand kind }, which represents frsd floating
100 point registers (double precision) which must be the same than
101 frs1 in its containing instruction.
103 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
105 * nds32.h: Add new opcode declaration.
107 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
108 Matthew Fortune <matthew.fortune@imgtec.com>
110 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
111 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
112 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
113 +I, +O, +R, +:, +\, +", +;
114 (mips_check_prev_operand): New struct.
115 (INSN2_FORBIDDEN_SLOT): New define.
116 (INSN_ISA32R6): New define.
117 (INSN_ISA64R6): New define.
118 (INSN_UPTO32R6): New define.
119 (INSN_UPTO64R6): New define.
120 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
121 (ISA_MIPS32R6): New define.
122 (ISA_MIPS64R6): New define.
123 (CPU_MIPS32R6): New define.
124 (CPU_MIPS64R6): New define.
125 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
127 2014-09-03 Jiong Wang <jiong.wang@arm.com>
129 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
130 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
131 (aarch64_insn_class): Add lse_atomic.
132 (F_LSE_SZ): New field added.
133 (opcode_has_special_coder): Recognize F_LSE_SZ.
135 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
137 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
140 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
142 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
143 (INSN_LOAD_COPROC): New define.
144 (INSN_COPROC_MOVE_DELAY): Rename to...
145 (INSN_COPROC_MOVE): New define.
147 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
148 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
149 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
150 Soundararajan <Sounderarajan.D@atmel.com>
152 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
153 (AVR_ISA_2xxxa): Define ISA without LPM.
154 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
155 Add doc for contraint used in 16 bit lds/sts.
156 Adjust ISA group for icall, ijmp, pop and push.
157 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
159 2014-05-19 Nick Clifton <nickc@redhat.com>
161 * msp430.h (struct msp430_operand_s): Add vshift field.
163 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
165 * mips.h (INSN_ISA_MASK): Updated.
166 (INSN_ISA32R3): New define.
167 (INSN_ISA32R5): New define.
168 (INSN_ISA64R3): New define.
169 (INSN_ISA64R5): New define.
170 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
171 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
172 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
174 (INSN_UPTO32R3): New define.
175 (INSN_UPTO32R5): New define.
176 (INSN_UPTO64R3): New define.
177 (INSN_UPTO64R5): New define.
178 (ISA_MIPS32R3): New define.
179 (ISA_MIPS32R5): New define.
180 (ISA_MIPS64R3): New define.
181 (ISA_MIPS64R5): New define.
182 (CPU_MIPS32R3): New define.
183 (CPU_MIPS32R5): New define.
184 (CPU_MIPS64R3): New define.
185 (CPU_MIPS64R5): New define.
187 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
189 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
191 2014-04-22 Christian Svensson <blue@cmd.nu>
195 2014-03-05 Alan Modra <amodra@gmail.com>
197 Update copyright years.
199 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
201 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
204 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
205 Wei-Cheng Wang <cole945@gmail.com>
207 * nds32.h: New file for Andes NDS32.
209 2013-12-07 Mike Frysinger <vapier@gentoo.org>
211 * bfin.h: Remove +x file mode.
213 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
215 * aarch64.h (aarch64_pstatefields): Change element type to
218 2013-11-18 Renlin Li <Renlin.Li@arm.com>
220 * arm.h (ARM_AEXT_V7VE): New define.
221 (ARM_ARCH_V7VE): New define.
222 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
224 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
228 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
230 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
231 (aarch64_sys_reg_writeonly_p): Ditto.
233 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
235 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
236 (aarch64_sys_reg_writeonly_p): Ditto.
238 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
240 * aarch64.h (aarch64_sys_reg): New typedef.
241 (aarch64_sys_regs): Change to define with the new type.
242 (aarch64_sys_reg_deprecated_p): Declare.
244 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
246 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
247 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
249 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
251 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
252 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
253 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
254 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
255 For MIPS, update extension character sequences after +.
256 (ASE_MSA): New define.
257 (ASE_MSA64): New define.
258 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
259 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
260 For microMIPS, update extension character sequences after +.
262 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
267 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
269 * mips.h: Remove references to "+I" and imm2_expr.
271 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
273 * mips.h (M_DEXT, M_DINS): Delete.
275 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
277 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
278 (mips_optional_operand_p): New function.
280 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
281 Richard Sandiford <rdsandiford@googlemail.com>
283 * mips.h: Document new VU0 operand characters.
284 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
285 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
286 (OP_REG_R5900_ACC): New mips_reg_operand_types.
287 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
288 (mips_vu0_channel_mask): Declare.
290 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
292 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
293 (mips_int_operand_min, mips_int_operand_max): New functions.
294 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
296 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
298 * mips.h (mips_decode_reg_operand): New function.
299 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
300 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
301 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
303 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
304 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
305 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
306 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
307 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
308 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
309 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
310 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
311 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
312 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
313 macros to cover the gaps.
314 (INSN2_MOD_SP): Replace with...
315 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
316 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
317 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
318 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
319 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
322 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
324 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
325 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
326 (MIPS16_INSN_COND_BRANCH): Delete.
328 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
329 Kirill Yukhin <kirill.yukhin@intel.com>
330 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
332 * i386.h (BND_PREFIX_OPCODE): New.
334 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
336 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
337 OP_SAVE_RESTORE_LIST.
338 (decode_mips16_operand): Declare.
340 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
342 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
343 (mips_operand, mips_int_operand, mips_mapped_int_operand)
344 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
345 (mips_pcrel_operand): New structures.
346 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
347 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
348 (decode_mips_operand, decode_micromips_operand): Declare.
350 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
352 * mips.h: Document MIPS16 "I" opcode.
354 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
356 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
357 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
358 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
359 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
360 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
361 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
362 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
363 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
364 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
365 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
366 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
367 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
368 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
370 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
371 (M_USD_AB): ...these.
373 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
375 * mips.h: Remove documentation of "[" and "]". Update documentation
376 of "k" and the MDMX formats.
378 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
380 * mips.h: Update documentation of "+s" and "+S".
382 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
384 * mips.h: Document "+i".
386 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
388 * mips.h: Remove "mi" documentation. Update "mh" documentation.
389 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
391 (INSN2_WRITE_GPR_MHI): Rename to...
392 (INSN2_WRITE_GPR_MH): ...this.
394 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
396 * mips.h: Remove documentation of "+D" and "+T".
398 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
400 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
401 Use "source" rather than "destination" for microMIPS "G".
403 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
405 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
408 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
410 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
412 2013-06-17 Catherine Moore <clm@codesourcery.com>
413 Maciej W. Rozycki <macro@codesourcery.com>
414 Chao-Ying Fu <fu@mips.com>
416 * mips.h (OP_SH_EVAOFFSET): Define.
417 (OP_MASK_EVAOFFSET): Define.
418 (INSN_ASE_MASK): Delete.
420 (M_CACHEE_AB, M_CACHEE_OB): New.
421 (M_LBE_OB, M_LBE_AB): New.
422 (M_LBUE_OB, M_LBUE_AB): New.
423 (M_LHE_OB, M_LHE_AB): New.
424 (M_LHUE_OB, M_LHUE_AB): New.
425 (M_LLE_AB, M_LLE_OB): New.
426 (M_LWE_OB, M_LWE_AB): New.
427 (M_LWLE_AB, M_LWLE_OB): New.
428 (M_LWRE_AB, M_LWRE_OB): New.
429 (M_PREFE_AB, M_PREFE_OB): New.
430 (M_SCE_AB, M_SCE_OB): New.
431 (M_SBE_OB, M_SBE_AB): New.
432 (M_SHE_OB, M_SHE_AB): New.
433 (M_SWE_OB, M_SWE_AB): New.
434 (M_SWLE_AB, M_SWLE_OB): New.
435 (M_SWRE_AB, M_SWRE_OB): New.
436 (MICROMIPSOP_SH_EVAOFFSET): Define.
437 (MICROMIPSOP_MASK_EVAOFFSET): Define.
439 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
441 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
443 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
445 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
447 2013-05-09 Andrew Pinski <apinski@cavium.com>
449 * mips.h (OP_MASK_CODE10): Correct definition.
450 (OP_SH_CODE10): Likewise.
451 Add a comment that "+J" is used now for OP_*CODE10.
452 (INSN_ASE_MASK): Update.
453 (INSN_VIRT): New macro.
454 (INSN_VIRT64): New macro
456 2013-05-02 Nick Clifton <nickc@redhat.com>
458 * msp430.h: Add patterns for MSP430X instructions.
460 2013-04-06 David S. Miller <davem@davemloft.net>
462 * sparc.h (F_PREFERRED): Define.
463 (F_PREF_ALIAS): Define.
465 2013-04-03 Nick Clifton <nickc@redhat.com>
467 * v850.h (V850_INVERSE_PCREL): Define.
469 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
472 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
474 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
477 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
479 * tic6xc-opcode-table.h: Add 16-bit insns.
480 * tic6x.h: Add support for 16-bit insns.
482 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
484 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
485 and mov.b/w/l Rs,@(d:32,ERd).
487 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
490 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
491 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
492 tic6x_operand_xregpair operand coding type.
493 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
494 opcode field, usu ORXREGD1324 for the src2 operand and remove the
497 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
500 * tic6x.h (enum tic6x_coding_method): Add
501 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
502 separately the msb and lsb of a register pair. This is needed to
503 encode the opcodes in the same way as TI assembler does.
504 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
505 and rsqrdp opcodes to use the new field coding types.
507 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
509 * arm.h (CRC_EXT_ARMV8): New constant.
510 (ARCH_CRC_ARMV8): New macro.
512 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
514 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
516 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
517 Andrew Jenner <andrew@codesourcery.com>
519 Based on patches from Altera Corporation.
523 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
525 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
527 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
530 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
532 2013-01-24 Nick Clifton <nickc@redhat.com>
534 * v850.h: Add e3v5 support.
536 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
538 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
540 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
542 * ppc.h (PPC_OPCODE_POWER8): New define.
543 (PPC_OPCODE_HTM): Likewise.
545 2013-01-10 Will Newton <will.newton@imgtec.com>
549 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
551 * cr16.h (make_instruction): Rename to cr16_make_instruction.
552 (match_opcode): Rename to cr16_match_opcode.
554 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
556 * mips.h: Add support for r5900 instructions including lq and sq.
558 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
560 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
561 (make_instruction,match_opcode): Added function prototypes.
562 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
564 2012-11-23 Alan Modra <amodra@gmail.com>
566 * ppc.h (ppc_parse_cpu): Update prototype.
568 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
570 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
571 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
573 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
575 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
577 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
579 * ia64.h (ia64_opnd): Add new operand types.
581 2012-08-21 David S. Miller <davem@davemloft.net>
583 * sparc.h (F3F4): New macro.
585 2012-08-13 Ian Bolton <ian.bolton@arm.com>
586 Laurent Desnogues <laurent.desnogues@arm.com>
587 Jim MacArthur <jim.macarthur@arm.com>
588 Marcus Shawcroft <marcus.shawcroft@arm.com>
589 Nigel Stephens <nigel.stephens@arm.com>
590 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
591 Richard Earnshaw <rearnsha@arm.com>
592 Sofiane Naci <sofiane.naci@arm.com>
593 Tejas Belagod <tejas.belagod@arm.com>
594 Yufeng Zhang <yufeng.zhang@arm.com>
596 * aarch64.h: New file.
598 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
599 Maciej W. Rozycki <macro@codesourcery.com>
601 * mips.h (mips_opcode): Add the exclusions field.
602 (OPCODE_IS_MEMBER): Remove macro.
603 (cpu_is_member): New inline function.
604 (opcode_is_member): Likewise.
606 2012-07-31 Chao-Ying Fu <fu@mips.com>
607 Catherine Moore <clm@codesourcery.com>
608 Maciej W. Rozycki <macro@codesourcery.com>
610 * mips.h: Document microMIPS DSP ASE usage.
611 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
612 microMIPS DSP ASE support.
613 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
614 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
615 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
616 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
617 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
618 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
619 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
621 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
623 * mips.h: Fix a typo in description.
625 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
627 * avr.h: (AVR_ISA_XCH): New define.
628 (AVR_ISA_XMEGA): Use it.
629 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
631 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
633 * m68hc11.h: Add XGate definitions.
634 (struct m68hc11_opcode): Add xg_mask field.
636 2012-05-14 Catherine Moore <clm@codesourcery.com>
637 Maciej W. Rozycki <macro@codesourcery.com>
638 Rhonda Wittels <rhonda@codesourcery.com>
640 * ppc.h (PPC_OPCODE_VLE): New definition.
641 (PPC_OP_SA): New macro.
642 (PPC_OP_SE_VLE): New macro.
643 (PPC_OP): Use a variable shift amount.
644 (powerpc_operand): Update comments.
645 (PPC_OPSHIFT_INV): New macro.
646 (PPC_OPERAND_CR): Replace with...
647 (PPC_OPERAND_CR_BIT): ...this and
648 (PPC_OPERAND_CR_REG): ...this.
651 2012-05-03 Sean Keys <skeys@ipdatasys.com>
653 * xgate.h: Header file for XGATE assembler.
655 2012-04-27 David S. Miller <davem@davemloft.net>
657 * sparc.h: Document new arg code' )' for crypto RS3
660 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
661 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
662 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
663 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
664 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
665 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
666 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
667 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
668 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
669 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
670 HWCAP_CBCOND, HWCAP_CRC32): New defines.
672 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
674 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
676 2012-02-27 Alan Modra <amodra@gmail.com>
678 * crx.h (cst4_map): Update declaration.
680 2012-02-25 Walter Lee <walt@tilera.com>
682 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
684 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
685 TILEPRO_OPC_LW_TLS_SN.
687 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
689 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
690 (XRELEASE_PREFIX_OPCODE): Likewise.
692 2011-12-08 Andrew Pinski <apinski@cavium.com>
693 Adam Nemet <anemet@caviumnetworks.com>
695 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
696 (INSN_OCTEON2): New macro.
697 (CPU_OCTEON2): New macro.
698 (OPCODE_IS_MEMBER): Add Octeon2.
700 2011-11-29 Andrew Pinski <apinski@cavium.com>
702 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
703 (INSN_OCTEONP): New macro.
704 (CPU_OCTEONP): New macro.
705 (OPCODE_IS_MEMBER): Add Octeon+.
706 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
708 2011-11-01 DJ Delorie <dj@redhat.com>
712 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
714 * mips.h: Fix a typo in description.
716 2011-09-21 David S. Miller <davem@davemloft.net>
718 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
719 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
720 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
721 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
723 2011-08-09 Chao-ying Fu <fu@mips.com>
724 Maciej W. Rozycki <macro@codesourcery.com>
726 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
727 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
728 (INSN_ASE_MASK): Add the MCU bit.
729 (INSN_MCU): New macro.
730 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
731 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
733 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
735 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
736 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
737 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
738 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
739 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
740 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
741 (INSN2_READ_GPR_MMN): Likewise.
742 (INSN2_READ_FPR_D): Change the bit used.
743 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
744 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
745 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
746 (INSN2_COND_BRANCH): Likewise.
747 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
748 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
749 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
750 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
751 (INSN2_MOD_GPR_MN): Likewise.
753 2011-08-05 David S. Miller <davem@davemloft.net>
755 * sparc.h: Document new format codes '4', '5', and '('.
756 (OPF_LOW4, RS3): New macros.
758 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
760 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
761 order of flags documented.
763 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
765 * mips.h: Clarify the description of microMIPS instruction
767 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
769 2011-07-24 Chao-ying Fu <fu@mips.com>
770 Maciej W. Rozycki <macro@codesourcery.com>
772 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
773 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
774 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
775 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
776 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
777 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
778 (OP_MASK_RS3, OP_SH_RS3): Likewise.
779 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
780 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
781 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
782 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
783 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
784 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
785 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
786 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
787 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
788 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
789 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
790 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
791 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
792 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
793 (INSN_WRITE_GPR_S): New macro.
794 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
795 (INSN2_READ_FPR_D): Likewise.
796 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
797 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
798 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
799 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
800 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
801 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
802 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
803 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
804 (CPU_MICROMIPS): New macro.
805 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
806 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
807 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
808 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
809 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
810 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
811 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
812 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
813 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
814 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
815 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
816 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
817 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
818 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
819 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
820 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
821 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
822 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
823 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
824 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
825 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
826 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
827 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
828 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
829 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
830 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
831 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
832 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
833 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
834 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
835 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
836 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
837 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
838 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
839 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
840 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
841 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
842 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
843 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
844 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
845 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
846 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
847 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
848 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
849 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
850 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
851 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
852 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
853 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
854 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
855 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
856 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
857 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
858 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
859 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
860 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
861 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
862 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
863 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
864 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
865 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
866 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
867 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
868 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
869 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
870 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
871 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
872 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
873 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
874 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
875 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
876 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
877 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
878 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
879 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
880 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
881 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
882 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
883 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
884 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
885 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
886 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
887 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
888 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
889 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
890 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
891 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
892 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
893 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
894 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
895 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
896 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
897 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
898 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
899 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
900 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
901 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
902 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
903 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
904 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
905 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
906 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
907 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
908 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
909 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
910 (micromips_opcodes): New declaration.
911 (bfd_micromips_num_opcodes): Likewise.
913 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
915 * mips.h (INSN_TRAP): Rename to...
916 (INSN_NO_DELAY_SLOT): ... this.
917 (INSN_SYNC): Remove macro.
919 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
921 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
922 a duplicate of AVR_ISA_SPM.
924 2011-07-01 Nick Clifton <nickc@redhat.com>
926 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
928 2011-06-18 Robin Getz <robin.getz@analog.com>
930 * bfin.h (is_macmod_signed): New func
932 2011-06-18 Mike Frysinger <vapier@gentoo.org>
934 * bfin.h (is_macmod_pmove): Add missing space before func args.
935 (is_macmod_hmove): Likewise.
937 2011-06-13 Walter Lee <walt@tilera.com>
939 * tilegx.h: New file.
940 * tilepro.h: New file.
942 2011-05-31 Paul Brook <paul@codesourcery.com>
944 * arm.h (ARM_ARCH_V7R_IDIV): Define.
946 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
948 * s390.h: Replace S390_OPERAND_REG_EVEN with
949 S390_OPERAND_REG_PAIR.
951 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
953 * s390.h: Add S390_OPCODE_REG_EVEN flag.
955 2011-04-18 Julian Brown <julian@codesourcery.com>
957 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
959 2011-04-11 Dan McDonald <dan@wellkeeper.com>
962 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
964 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
966 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
967 New instruction set flags.
968 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
970 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
972 * mips.h (M_PREF_AB): New enum value.
974 2011-02-12 Mike Frysinger <vapier@gentoo.org>
976 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
978 (is_macmod_pmove, is_macmod_hmove): New functions.
980 2011-02-11 Mike Frysinger <vapier@gentoo.org>
982 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
984 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
986 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
987 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
989 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
992 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
995 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
998 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1000 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1002 * mips.h: Update commentary after last commit.
1004 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1006 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1007 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1008 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1010 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1012 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1014 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1016 * mips.h: Fix previous commit.
1018 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1020 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1021 (INSN_LOONGSON_3A): Clear bit 31.
1023 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1026 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1027 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1028 (ARM_ARCH_V6M_ONLY): New define.
1030 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1032 * mips.h (INSN_LOONGSON_3A): Defined.
1033 (CPU_LOONGSON_3A): Defined.
1034 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1036 2010-10-09 Matt Rice <ratmice@gmail.com>
1038 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1039 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1041 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1043 * arm.h (ARM_EXT_VIRT): New define.
1044 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1045 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1048 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1050 * arm.h (ARM_AEXT_ADIV): New define.
1051 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1053 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1055 * arm.h (ARM_EXT_OS): New define.
1056 (ARM_AEXT_V6SM): Likewise.
1057 (ARM_ARCH_V6SM): Likewise.
1059 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1061 * arm.h (ARM_EXT_MP): Add.
1062 (ARM_ARCH_V7A_MP): Likewise.
1064 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1066 * bfin.h: Declare pseudoChr structs/defines.
1068 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1070 * bfin.h: Strip trailing whitespace.
1072 2010-07-29 DJ Delorie <dj@redhat.com>
1074 * rx.h (RX_Operand_Type): Add TwoReg.
1075 (RX_Opcode_ID): Remove ediv and ediv2.
1077 2010-07-27 DJ Delorie <dj@redhat.com>
1079 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1081 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1082 Ina Pandit <ina.pandit@kpitcummins.com>
1084 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1085 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1086 PROCESSOR_V850E2_ALL.
1087 Remove PROCESSOR_V850EA support.
1088 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1089 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1090 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1091 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1092 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1093 V850_OPERAND_PERCENT.
1094 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1096 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1099 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1101 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1102 (MIPS16_INSN_BRANCH): Rename to...
1103 (MIPS16_INSN_COND_BRANCH): ... this.
1105 2010-07-03 Alan Modra <amodra@gmail.com>
1107 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1108 Renumber other PPC_OPCODE defines.
1110 2010-07-03 Alan Modra <amodra@gmail.com>
1112 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1114 2010-06-29 Alan Modra <amodra@gmail.com>
1116 * maxq.h: Delete file.
1118 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1120 * ppc.h (PPC_OPCODE_E500): Define.
1122 2010-05-26 Catherine Moore <clm@codesourcery.com>
1124 * opcode/mips.h (INSN_MIPS16): Remove.
1126 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1128 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1130 2010-04-15 Nick Clifton <nickc@redhat.com>
1132 * alpha.h: Update copyright notice to use GPLv3.
1138 * convex.h: Likewise.
1145 * h8300.h: Likewise.
1152 * m68hc11.h: Likewise.
1158 * mn10200.h: Likewise.
1159 * mn10300.h: Likewise.
1160 * msp430.h: Likewise.
1162 * ns32k.h: Likewise.
1164 * pdp11.h: Likewise.
1171 * score-datadep.h: Likewise.
1172 * score-inst.h: Likewise.
1173 * sparc.h: Likewise.
1174 * spu-insns.h: Likewise.
1176 * tic30.h: Likewise.
1177 * tic4x.h: Likewise.
1178 * tic54x.h: Likewise.
1179 * tic80.h: Likewise.
1183 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1185 * tic6x-control-registers.h, tic6x-insn-formats.h,
1186 tic6x-opcode-table.h, tic6x.h: New.
1188 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1190 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1192 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1194 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1196 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1198 * ia64.h (ia64_find_opcode): Remove argument name.
1199 (ia64_find_next_opcode): Likewise.
1200 (ia64_dis_opcode): Likewise.
1201 (ia64_free_opcode): Likewise.
1202 (ia64_find_dependency): Likewise.
1204 2009-11-22 Doug Evans <dje@sebabeach.org>
1206 * cgen.h: Include bfd_stdint.h.
1207 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1209 2009-11-18 Paul Brook <paul@codesourcery.com>
1211 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1213 2009-11-17 Paul Brook <paul@codesourcery.com>
1214 Daniel Jacobowitz <dan@codesourcery.com>
1216 * arm.h (ARM_EXT_V6_DSP): Define.
1217 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1218 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1220 2009-11-04 DJ Delorie <dj@redhat.com>
1222 * rx.h (rx_decode_opcode) (mvtipl): Add.
1223 (mvtcp, mvfcp, opecp): Remove.
1225 2009-11-02 Paul Brook <paul@codesourcery.com>
1227 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1228 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1229 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1230 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1231 FPU_ARCH_NEON_VFP_V4): Define.
1233 2009-10-23 Doug Evans <dje@sebabeach.org>
1235 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1236 * cgen.h: Update. Improve multi-inclusion macro name.
1238 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1240 * ppc.h (PPC_OPCODE_476): Define.
1242 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1244 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1246 2009-09-29 DJ Delorie <dj@redhat.com>
1250 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1252 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1254 2009-09-21 Ben Elliston <bje@au.ibm.com>
1256 * ppc.h (PPC_OPCODE_PPCA2): New.
1258 2009-09-05 Martin Thuresson <martin@mtme.org>
1260 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1262 2009-08-29 Martin Thuresson <martin@mtme.org>
1264 * tic30.h (template): Rename type template to
1265 insn_template. Updated code to use new name.
1266 * tic54x.h (template): Rename type template to
1269 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1271 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1273 2009-06-11 Anthony Green <green@moxielogic.com>
1275 * moxie.h (MOXIE_F3_PCREL): Define.
1276 (moxie_form3_opc_info): Grow.
1278 2009-06-06 Anthony Green <green@moxielogic.com>
1280 * moxie.h (MOXIE_F1_M): Define.
1282 2009-04-15 Anthony Green <green@moxielogic.com>
1286 2009-04-06 DJ Delorie <dj@redhat.com>
1288 * h8300.h: Add relaxation attributes to MOVA opcodes.
1290 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1292 * ppc.h (ppc_parse_cpu): Declare.
1294 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1296 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1297 and _IMM11 for mbitclr and mbitset.
1298 * score-datadep.h: Update dependency information.
1300 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1302 * ppc.h (PPC_OPCODE_POWER7): New.
1304 2009-02-06 Doug Evans <dje@google.com>
1306 * i386.h: Add comment regarding sse* insns and prefixes.
1308 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1310 * mips.h (INSN_XLR): Define.
1311 (INSN_CHIP_MASK): Update.
1313 (OPCODE_IS_MEMBER): Update.
1314 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1316 2009-01-28 Doug Evans <dje@google.com>
1318 * opcode/i386.h: Add multiple inclusion protection.
1319 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1320 (EDI_REG_NUM): New macros.
1321 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1322 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1323 (REX_PREFIX_P): New macro.
1325 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1327 * ppc.h (struct powerpc_opcode): New field "deprecated".
1328 (PPC_OPCODE_NOPOWER4): Delete.
1330 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1332 * mips.h: Define CPU_R14000, CPU_R16000.
1333 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1335 2008-11-18 Catherine Moore <clm@codesourcery.com>
1337 * arm.h (FPU_NEON_FP16): New.
1338 (FPU_ARCH_NEON_FP16): New.
1340 2008-11-06 Chao-ying Fu <fu@mips.com>
1342 * mips.h: Doucument '1' for 5-bit sync type.
1344 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1346 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1349 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1351 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1353 2008-07-30 Michael J. Eager <eager@eagercon.com>
1355 * ppc.h (PPC_OPCODE_405): Define.
1356 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1358 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1360 * ppc.h (ppc_cpu_t): New typedef.
1361 (struct powerpc_opcode <flags>): Use it.
1362 (struct powerpc_operand <insert, extract>): Likewise.
1363 (struct powerpc_macro <flags>): Likewise.
1365 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1367 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1368 Update comment before MIPS16 field descriptors to mention MIPS16.
1369 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1371 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1372 New bit masks and shift counts for cins and exts.
1374 * mips.h: Document new field descriptors +Q.
1375 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1377 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1379 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1380 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1382 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1384 * ppc.h: (PPC_OPCODE_E500MC): New.
1386 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1388 * i386.h (MAX_OPERANDS): Set to 5.
1389 (MAX_MNEM_SIZE): Changed to 20.
1391 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1393 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1395 2008-03-09 Paul Brook <paul@codesourcery.com>
1397 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1399 2008-03-04 Paul Brook <paul@codesourcery.com>
1401 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1402 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1403 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1405 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1406 Nick Clifton <nickc@redhat.com>
1409 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1410 with a 32-bit displacement but without the top bit of the 4th byte
1413 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1415 * cr16.h (cr16_num_optab): Declared.
1417 2008-02-14 Hakan Ardo <hakan@debian.org>
1420 * avr.h (AVR_ISA_2xxe): Define.
1422 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1424 * mips.h: Update copyright.
1425 (INSN_CHIP_MASK): New macro.
1426 (INSN_OCTEON): New macro.
1427 (CPU_OCTEON): New macro.
1428 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1430 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1432 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1434 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1436 * avr.h (AVR_ISA_USB162): Add new opcode set.
1437 (AVR_ISA_AVR3): Likewise.
1439 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1441 * mips.h (INSN_LOONGSON_2E): New.
1442 (INSN_LOONGSON_2F): New.
1443 (CPU_LOONGSON_2E): New.
1444 (CPU_LOONGSON_2F): New.
1445 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1447 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1449 * mips.h (INSN_ISA*): Redefine certain values as an
1450 enumeration. Update comments.
1451 (mips_isa_table): New.
1452 (ISA_MIPS*): Redefine to match enumeration.
1453 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1456 2007-08-08 Ben Elliston <bje@au.ibm.com>
1458 * ppc.h (PPC_OPCODE_PPCPS): New.
1460 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1462 * m68k.h: Document j K & E.
1464 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1466 * cr16.h: New file for CR16 target.
1468 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1470 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1472 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1474 * m68k.h (mcfisa_c): New.
1475 (mcfusp, mcf_mask): Adjust.
1477 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1479 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1480 (num_powerpc_operands): Declare.
1481 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1482 (PPC_OPERAND_PLUS1): Define.
1484 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1486 * i386.h (REX_MODE64): Renamed to ...
1488 (REX_EXTX): Renamed to ...
1490 (REX_EXTY): Renamed to ...
1492 (REX_EXTZ): Renamed to ...
1495 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1497 * i386.h: Add entries from config/tc-i386.h and move tables
1498 to opcodes/i386-opc.h.
1500 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1502 * i386.h (FloatDR): Removed.
1503 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1505 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1507 * spu-insns.h: Add soma double-float insns.
1509 2007-02-20 Thiemo Seufer <ths@mips.com>
1510 Chao-Ying Fu <fu@mips.com>
1512 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1513 (INSN_DSPR2): Add flag for DSP R2 instructions.
1514 (M_BALIGN): New macro.
1516 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1518 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1519 and Seg3ShortFrom with Shortform.
1521 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1524 * i386.h (i386_optab): Put the real "test" before the pseudo
1527 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1529 * m68k.h (m68010up): OR fido_a.
1531 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1533 * m68k.h (fido_a): New.
1535 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1537 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1538 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1541 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1543 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1545 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1547 * score-inst.h (enum score_insn_type): Add Insn_internal.
1549 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1550 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1551 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1552 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1553 Alan Modra <amodra@bigpond.net.au>
1555 * spu-insns.h: New file.
1558 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1560 * ppc.h (PPC_OPCODE_CELL): Define.
1562 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1564 * i386.h : Modify opcode to support for the change in POPCNT opcode
1565 in amdfam10 architecture.
1567 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1569 * i386.h: Replace CpuMNI with CpuSSSE3.
1571 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1572 Joseph Myers <joseph@codesourcery.com>
1573 Ian Lance Taylor <ian@wasabisystems.com>
1574 Ben Elliston <bje@wasabisystems.com>
1576 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1578 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1580 * score-datadep.h: New file.
1581 * score-inst.h: New file.
1583 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1585 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1586 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1587 movdq2q and movq2dq.
1589 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1590 Michael Meissner <michael.meissner@amd.com>
1592 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1594 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1596 * i386.h (i386_optab): Add "nop" with memory reference.
1598 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1600 * i386.h (i386_optab): Update comment for 64bit NOP.
1602 2006-06-06 Ben Elliston <bje@au.ibm.com>
1603 Anton Blanchard <anton@samba.org>
1605 * ppc.h (PPC_OPCODE_POWER6): Define.
1608 2006-06-05 Thiemo Seufer <ths@mips.com>
1610 * mips.h: Improve description of MT flags.
1612 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1614 * m68k.h (mcf_mask): Define.
1616 2006-05-05 Thiemo Seufer <ths@mips.com>
1617 David Ung <davidu@mips.com>
1619 * mips.h (enum): Add macro M_CACHE_AB.
1621 2006-05-04 Thiemo Seufer <ths@mips.com>
1622 Nigel Stephens <nigel@mips.com>
1623 David Ung <davidu@mips.com>
1625 * mips.h: Add INSN_SMARTMIPS define.
1627 2006-04-30 Thiemo Seufer <ths@mips.com>
1628 David Ung <davidu@mips.com>
1630 * mips.h: Defines udi bits and masks. Add description of
1631 characters which may appear in the args field of udi
1634 2006-04-26 Thiemo Seufer <ths@networkno.de>
1636 * mips.h: Improve comments describing the bitfield instruction
1639 2006-04-26 Julian Brown <julian@codesourcery.com>
1641 * arm.h (FPU_VFP_EXT_V3): Define constant.
1642 (FPU_NEON_EXT_V1): Likewise.
1643 (FPU_VFP_HARD): Update.
1644 (FPU_VFP_V3): Define macro.
1645 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1647 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1649 * avr.h (AVR_ISA_PWMx): New.
1651 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1653 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1654 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1655 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1656 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1657 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1659 2006-03-10 Paul Brook <paul@codesourcery.com>
1661 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1663 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1665 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1666 first. Correct mask of bb "B" opcode.
1668 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1670 * i386.h (i386_optab): Support Intel Merom New Instructions.
1672 2006-02-24 Paul Brook <paul@codesourcery.com>
1674 * arm.h: Add V7 feature bits.
1676 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1678 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1680 2006-01-31 Paul Brook <paul@codesourcery.com>
1681 Richard Earnshaw <rearnsha@arm.com>
1683 * arm.h: Use ARM_CPU_FEATURE.
1684 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1685 (arm_feature_set): Change to a structure.
1686 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1687 ARM_FEATURE): New macros.
1689 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1691 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1692 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1693 (ADD_PC_INCR_OPCODE): Don't define.
1695 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1698 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1700 2005-11-14 David Ung <davidu@mips.com>
1702 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1703 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1704 save/restore encoding of the args field.
1706 2005-10-28 Dave Brolley <brolley@redhat.com>
1708 Contribute the following changes:
1709 2005-02-16 Dave Brolley <brolley@redhat.com>
1711 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1712 cgen_isa_mask_* to cgen_bitset_*.
1715 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1717 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1718 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1719 (CGEN_CPU_TABLE): Make isas a ponter.
1721 2003-09-29 Dave Brolley <brolley@redhat.com>
1723 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1724 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1725 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1727 2002-12-13 Dave Brolley <brolley@redhat.com>
1729 * cgen.h (symcat.h): #include it.
1730 (cgen-bitset.h): #include it.
1731 (CGEN_ATTR_VALUE_TYPE): Now a union.
1732 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1733 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1734 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1735 * cgen-bitset.h: New file.
1737 2005-09-30 Catherine Moore <clm@cm00re.com>
1741 2005-10-24 Jan Beulich <jbeulich@novell.com>
1743 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1746 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1748 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1749 Add FLAG_STRICT to pa10 ftest opcode.
1751 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1753 * hppa.h (pa_opcodes): Remove lha entries.
1755 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1757 * hppa.h (FLAG_STRICT): Revise comment.
1758 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1759 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1762 2005-09-30 Catherine Moore <clm@cm00re.com>
1766 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1768 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1770 2005-09-06 Chao-ying Fu <fu@mips.com>
1772 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1773 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1775 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1776 (INSN_ASE_MASK): Update to include INSN_MT.
1777 (INSN_MT): New define for MT ASE.
1779 2005-08-25 Chao-ying Fu <fu@mips.com>
1781 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1782 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1783 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1784 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1785 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1786 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1788 (INSN_DSP): New define for DSP ASE.
1790 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1794 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1796 * ppc.h (PPC_OPCODE_E300): Define.
1798 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1800 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1802 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1805 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1808 2005-07-27 Jan Beulich <jbeulich@novell.com>
1810 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1811 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1812 Add movq-s as 64-bit variants of movd-s.
1814 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1816 * hppa.h: Fix punctuation in comment.
1818 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1819 implicit space-register addressing. Set space-register bits on opcodes
1820 using implicit space-register addressing. Add various missing pa20
1821 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1822 space-register addressing. Use "fE" instead of "fe" in various
1825 2005-07-18 Jan Beulich <jbeulich@novell.com>
1827 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1829 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1831 * i386.h (i386_optab): Support Intel VMX Instructions.
1833 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1835 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1837 2005-07-05 Jan Beulich <jbeulich@novell.com>
1839 * i386.h (i386_optab): Add new insns.
1841 2005-07-01 Nick Clifton <nickc@redhat.com>
1843 * sparc.h: Add typedefs to structure declarations.
1845 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1848 * i386.h (i386_optab): Update comments for 64bit addressing on
1849 mov. Allow 64bit addressing for mov and movq.
1851 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1853 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1854 respectively, in various floating-point load and store patterns.
1856 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1858 * hppa.h (FLAG_STRICT): Correct comment.
1859 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1860 PA 2.0 mneumonics when equivalent. Entries with cache control
1861 completers now require PA 1.1. Adjust whitespace.
1863 2005-05-19 Anton Blanchard <anton@samba.org>
1865 * ppc.h (PPC_OPCODE_POWER5): Define.
1867 2005-05-10 Nick Clifton <nickc@redhat.com>
1869 * Update the address and phone number of the FSF organization in
1870 the GPL notices in the following files:
1871 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1872 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1873 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1874 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1875 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1876 tic54x.h, tic80.h, v850.h, vax.h
1878 2005-05-09 Jan Beulich <jbeulich@novell.com>
1880 * i386.h (i386_optab): Add ht and hnt.
1882 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1884 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1885 Add xcrypt-ctr. Provide aliases without hyphens.
1887 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1889 Moved from ../ChangeLog
1891 2005-04-12 Paul Brook <paul@codesourcery.com>
1892 * m88k.h: Rename psr macros to avoid conflicts.
1894 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1895 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1896 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1897 and ARM_ARCH_V6ZKT2.
1899 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1900 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1901 Remove redundant instruction types.
1902 (struct argument): X_op - new field.
1903 (struct cst4_entry): Remove.
1904 (no_op_insn): Declare.
1906 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1907 * crx.h (enum argtype): Rename types, remove unused types.
1909 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1910 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1911 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1912 (enum operand_type): Rearrange operands, edit comments.
1913 replace us<N> with ui<N> for unsigned immediate.
1914 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1915 displacements (respectively).
1916 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1917 (instruction type): Add NO_TYPE_INS.
1918 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1919 (operand_entry): New field - 'flags'.
1920 (operand flags): New.
1922 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1923 * crx.h (operand_type): Remove redundant types i3, i4,
1925 Add new unsigned immediate types us3, us4, us5, us16.
1927 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1929 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1930 adjust them accordingly.
1932 2005-04-01 Jan Beulich <jbeulich@novell.com>
1934 * i386.h (i386_optab): Add rdtscp.
1936 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1938 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1939 between memory and segment register. Allow movq for moving between
1940 general-purpose register and segment register.
1942 2005-02-09 Jan Beulich <jbeulich@novell.com>
1945 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1946 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1949 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1951 * m68k.h (m68008, m68ec030, m68882): Remove.
1953 (cpu_m68k, cpu_cf): New.
1954 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1955 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1957 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1959 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1960 * cgen.h (enum cgen_parse_operand_type): Add
1961 CGEN_PARSE_OPERAND_SYMBOLIC.
1963 2005-01-21 Fred Fish <fnf@specifixinc.com>
1965 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1966 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1967 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1969 2005-01-19 Fred Fish <fnf@specifixinc.com>
1971 * mips.h (struct mips_opcode): Add new pinfo2 member.
1972 (INSN_ALIAS): New define for opcode table entries that are
1973 specific instances of another entry, such as 'move' for an 'or'
1974 with a zero operand.
1975 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1976 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1978 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1980 * mips.h (CPU_RM9000): Define.
1981 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1983 2004-11-25 Jan Beulich <jbeulich@novell.com>
1985 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1986 to/from test registers are illegal in 64-bit mode. Add missing
1987 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1988 (previously one had to explicitly encode a rex64 prefix). Re-enable
1989 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1990 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1992 2004-11-23 Jan Beulich <jbeulich@novell.com>
1994 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1995 available only with SSE2. Change the MMX additions introduced by SSE
1996 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1997 instructions by their now designated identifier (since combining i686
1998 and 3DNow! does not really imply 3DNow!A).
2000 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2002 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2003 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2005 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2006 Vineet Sharma <vineets@noida.hcltech.com>
2008 * maxq.h: New file: Disassembly information for the maxq port.
2010 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2012 * i386.h (i386_optab): Put back "movzb".
2014 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2016 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2017 comments. Remove member cris_ver_sim. Add members
2018 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2019 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2020 (struct cris_support_reg, struct cris_cond15): New types.
2021 (cris_conds15): Declare.
2022 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2023 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2024 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2025 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2026 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2027 SIZE_FIELD_UNSIGNED.
2029 2004-11-04 Jan Beulich <jbeulich@novell.com>
2031 * i386.h (sldx_Suf): Remove.
2032 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2033 (q_FP): Define, implying no REX64.
2034 (x_FP, sl_FP): Imply FloatMF.
2035 (i386_optab): Split reg and mem forms of moving from segment registers
2036 so that the memory forms can ignore the 16-/32-bit operand size
2037 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2038 all non-floating-point instructions. Unite 32- and 64-bit forms of
2039 movsx, movzx, and movd. Adjust floating point operations for the above
2040 changes to the *FP macros. Add DefaultSize to floating point control
2041 insns operating on larger memory ranges. Remove left over comments
2042 hinting at certain insns being Intel-syntax ones where the ones
2043 actually meant are already gone.
2045 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2047 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2050 2004-09-30 Paul Brook <paul@codesourcery.com>
2052 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2053 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2055 2004-09-11 Theodore A. Roth <troth@openavr.org>
2057 * avr.h: Add support for
2058 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2060 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2062 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2064 2004-08-24 Dmitry Diky <diwil@spec.ru>
2066 * msp430.h (msp430_opc): Add new instructions.
2067 (msp430_rcodes): Declare new instructions.
2068 (msp430_hcodes): Likewise..
2070 2004-08-13 Nick Clifton <nickc@redhat.com>
2073 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2076 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2078 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2080 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2082 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2084 2004-07-21 Jan Beulich <jbeulich@novell.com>
2086 * i386.h: Adjust instruction descriptions to better match the
2089 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2091 * arm.h: Remove all old content. Replace with architecture defines
2092 from gas/config/tc-arm.c.
2094 2004-07-09 Andreas Schwab <schwab@suse.de>
2096 * m68k.h: Fix comment.
2098 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2102 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2104 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2106 2004-05-24 Peter Barada <peter@the-baradas.com>
2108 * m68k.h: Add 'size' to m68k_opcode.
2110 2004-05-05 Peter Barada <peter@the-baradas.com>
2112 * m68k.h: Switch from ColdFire chip name to core variant.
2114 2004-04-22 Peter Barada <peter@the-baradas.com>
2116 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2117 descriptions for new EMAC cases.
2118 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2119 handle Motorola MAC syntax.
2120 Allow disassembly of ColdFire V4e object files.
2122 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2124 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2126 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2128 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2130 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2132 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2134 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2136 * i386.h (i386_optab): Added xstore/xcrypt insns.
2138 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2140 * h8300.h (32bit ldc/stc): Add relaxing support.
2142 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2144 * h8300.h (BITOP): Pass MEMRELAX flag.
2146 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2148 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2151 For older changes see ChangeLog-9103
2153 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2155 Copying and distribution of this file, with or without modification,
2156 are permitted in any medium without royalty provided the copyright
2157 notice and this notice are preserved.
2163 version-control: never
projects / deliverable / binutils-gdb.git / blob