include/opcode/ChangeLog

   1 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * ia64.h (ia64_find_opcode): Remove argument name.
   4         (ia64_find_next_opcode): Likewise.
   5         (ia64_dis_opcode): Likewise.
   6         (ia64_free_opcode): Likewise.
   7         (ia64_find_dependency): Likewise.
   8
   9 2009-11-22  Doug Evans  <dje@sebabeach.org>
  10
  11         * cgen.h: Include bfd_stdint.h.
  12         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
  13
  14 2009-11-18  Paul Brook  <paul@codesourcery.com>
  15
  16         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
  17
  18 2009-11-17  Paul Brook  <paul@codesourcery.com>
  19         Daniel Jacobowitz  <dan@codesourcery.com>
  20
  21         * arm.h (ARM_EXT_V6_DSP): Define.
  22         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
  23         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
  24
  25 2009-11-04  DJ Delorie  <dj@redhat.com>
  26
  27         * rx.h (rx_decode_opcode) (mvtipl): Add.
  28         (mvtcp, mvfcp, opecp): Remove.
  29
  30 2009-11-02  Paul Brook  <paul@codesourcery.com>
  31
  32         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
  33         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
  34         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
  35         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
  36         FPU_ARCH_NEON_VFP_V4): Define.
  37
  38 2009-10-23  Doug Evans  <dje@sebabeach.org>
  39
  40         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
  41         * cgen.h: Update.  Improve multi-inclusion macro name.
  42
  43 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
  44
  45         * ppc.h (PPC_OPCODE_476): Define.
  46
  47 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
  48
  49         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
  50
  51 2009-09-29  DJ Delorie  <dj@redhat.com>
  52
  53         * rx.h: New file.
  54
  55 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
  56
  57         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
  58
  59 2009-09-21  Ben Elliston  <bje@au.ibm.com>
  60
  61         * ppc.h (PPC_OPCODE_PPCA2): New.
  62
  63 2009-09-05  Martin Thuresson  <martin@mtme.org>
  64
  65         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  66
  67 2009-08-29  Martin Thuresson  <martin@mtme.org>
  68
  69         * tic30.h (template): Rename type template to
  70         insn_template. Updated code to use new name.
  71         * tic54x.h (template): Rename type template to
  72         insn_template.
  73
  74 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  75
  76         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  77
  78 2009-06-11  Anthony Green  <green@moxielogic.com>
  79
  80         * moxie.h (MOXIE_F3_PCREL): Define.
  81         (moxie_form3_opc_info): Grow.
  82
  83 2009-06-06  Anthony Green  <green@moxielogic.com>
  84
  85         * moxie.h (MOXIE_F1_M): Define.
  86
  87 2009-04-15  Anthony Green  <green@moxielogic.com>
  88
  89         * moxie.h: Created.
  90
  91 2009-04-06  DJ Delorie  <dj@redhat.com>
  92
  93         * h8300.h: Add relaxation attributes to MOVA opcodes.
  94
  95 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  96
  97         * ppc.h (ppc_parse_cpu): Declare.
  98
  99 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 100
 101         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 102         and _IMM11 for mbitclr and mbitset.
 103         * score-datadep.h: Update dependency information.
 104
 105 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 106
 107         * ppc.h (PPC_OPCODE_POWER7): New.
 108
 109 2009-02-06  Doug Evans  <dje@google.com>
 110
 111         * i386.h: Add comment regarding sse* insns and prefixes.
 112
 113 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 114
 115         * mips.h (INSN_XLR): Define.
 116         (INSN_CHIP_MASK): Update.
 117         (CPU_XLR): Define.
 118         (OPCODE_IS_MEMBER): Update.
 119         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 120
 121 2009-01-28  Doug Evans  <dje@google.com>
 122
 123         * opcode/i386.h: Add multiple inclusion protection.
 124         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 125         (EDI_REG_NUM): New macros.
 126         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 127         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 128         (REX_PREFIX_P): New macro.
 129
 130 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 131
 132         * ppc.h (struct powerpc_opcode): New field "deprecated".
 133         (PPC_OPCODE_NOPOWER4): Delete.
 134
 135 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 136
 137         * mips.h: Define CPU_R14000, CPU_R16000.
 138         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 139
 140 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 141
 142         * arm.h (FPU_NEON_FP16): New.
 143         (FPU_ARCH_NEON_FP16): New.
 144
 145 2008-11-06  Chao-ying Fu  <fu@mips.com>
 146
 147         * mips.h: Doucument '1' for 5-bit sync type.
 148
 149 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 152         IA64_RS_CR.
 153
 154 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 155
 156         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 157
 158 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 159
 160         * ppc.h (PPC_OPCODE_405): Define.
 161         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 162
 163 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 164
 165         * ppc.h (ppc_cpu_t): New typedef.
 166         (struct powerpc_opcode <flags>): Use it.
 167         (struct powerpc_operand <insert, extract>): Likewise.
 168         (struct powerpc_macro <flags>): Likewise.
 169
 170 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 171
 172         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 173         Update comment before MIPS16 field descriptors to mention MIPS16.
 174         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 175         BBIT.
 176         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 177         New bit masks and shift counts for cins and exts.
 178
 179         * mips.h: Document new field descriptors +Q.
 180         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 181
 182 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 183
 184         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 185         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 186
 187 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 188
 189         * ppc.h: (PPC_OPCODE_E500MC): New.
 190
 191 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386.h (MAX_OPERANDS): Set to 5.
 194         (MAX_MNEM_SIZE): Changed to 20.
 195
 196 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 197
 198         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 199
 200 2008-03-09  Paul Brook  <paul@codesourcery.com>
 201
 202         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 203
 204 2008-03-04  Paul Brook  <paul@codesourcery.com>
 205
 206         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 207         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 208         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 209
 210 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 211             Nick Clifton  <nickc@redhat.com>
 212
 213         PR 3134
 214         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 215         with a 32-bit displacement but without the top bit of the 4th byte
 216         set.
 217
 218 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 219
 220         * cr16.h (cr16_num_optab): Declared.
 221
 222 2008-02-14  Hakan Ardo  <hakan@debian.org>
 223
 224         PR gas/2626
 225         * avr.h (AVR_ISA_2xxe): Define.
 226
 227 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 228
 229         * mips.h: Update copyright.
 230         (INSN_CHIP_MASK): New macro.
 231         (INSN_OCTEON): New macro.
 232         (CPU_OCTEON): New macro.
 233         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 234
 235 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 236
 237         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 238
 239 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 240
 241         * avr.h (AVR_ISA_USB162): Add new opcode set.
 242         (AVR_ISA_AVR3): Likewise.
 243
 244 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 245
 246         * mips.h (INSN_LOONGSON_2E): New.
 247         (INSN_LOONGSON_2F): New.
 248         (CPU_LOONGSON_2E): New.
 249         (CPU_LOONGSON_2F): New.
 250         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 251
 252 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 253
 254         * mips.h (INSN_ISA*): Redefine certain values as an
 255         enumeration.  Update comments.
 256         (mips_isa_table): New.
 257         (ISA_MIPS*): Redefine to match enumeration.
 258         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 259         values.
 260
 261 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 262
 263         * ppc.h (PPC_OPCODE_PPCPS): New.
 264
 265 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 266
 267         * m68k.h: Document j K & E.
 268
 269 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 270
 271         * cr16.h: New file for CR16 target.
 272
 273 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 274
 275         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 276
 277 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 278
 279         * m68k.h (mcfisa_c): New.
 280         (mcfusp, mcf_mask): Adjust.
 281
 282 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 283
 284         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 285         (num_powerpc_operands): Declare.
 286         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 287         (PPC_OPERAND_PLUS1): Define.
 288
 289 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 290
 291         * i386.h (REX_MODE64): Renamed to ...
 292         (REX_W): This.
 293         (REX_EXTX): Renamed to ...
 294         (REX_R): This.
 295         (REX_EXTY): Renamed to ...
 296         (REX_X): This.
 297         (REX_EXTZ): Renamed to ...
 298         (REX_B): This.
 299
 300 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * i386.h: Add entries from config/tc-i386.h and move tables
 303         to opcodes/i386-opc.h.
 304
 305 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         * i386.h (FloatDR): Removed.
 308         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 309
 310 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 311
 312         * spu-insns.h: Add soma double-float insns.
 313
 314 2007-02-20  Thiemo Seufer  <ths@mips.com>
 315             Chao-Ying Fu  <fu@mips.com>
 316
 317         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 318         (INSN_DSPR2): Add flag for DSP R2 instructions.
 319         (M_BALIGN): New macro.
 320
 321 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 322
 323         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 324         and Seg3ShortFrom with Shortform.
 325
 326 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         PR gas/4027
 329         * i386.h (i386_optab): Put the real "test" before the pseudo
 330         one.
 331
 332 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 333
 334         * m68k.h (m68010up): OR fido_a.
 335
 336 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 337
 338         * m68k.h (fido_a): New.
 339
 340 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 341
 342         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 343         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 344         values.
 345
 346 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 347
 348         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 349
 350 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 351
 352         * score-inst.h (enum score_insn_type): Add Insn_internal.
 353
 354 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 355             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 356             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 357             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 358             Alan Modra  <amodra@bigpond.net.au>
 359
 360         * spu-insns.h: New file.
 361         * spu.h: New file.
 362
 363 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 364
 365         * ppc.h (PPC_OPCODE_CELL): Define.
 366
 367 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 368
 369         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 370         in amdfam10 architecture.
 371
 372 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         * i386.h: Replace CpuMNI with CpuSSSE3.
 375
 376 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 377             Joseph Myers  <joseph@codesourcery.com>
 378             Ian Lance Taylor  <ian@wasabisystems.com>
 379             Ben Elliston  <bje@wasabisystems.com>
 380
 381         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 382
 383 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 384
 385         * score-datadep.h: New file.
 386         * score-inst.h: New file.
 387
 388 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 389
 390         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 391         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 392         movdq2q and movq2dq.
 393
 394 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 395            Michael Meissner             <michael.meissner@amd.com>
 396
 397         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 398
 399 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 400
 401         * i386.h (i386_optab): Add "nop" with memory reference.
 402
 403 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 404
 405         * i386.h (i386_optab): Update comment for 64bit NOP.
 406
 407 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 408             Anton Blanchard  <anton@samba.org>
 409
 410         * ppc.h (PPC_OPCODE_POWER6): Define.
 411         Adjust whitespace.
 412
 413 2006-06-05  Thiemo Seufer  <ths@mips.com>
 414
 415         * mips.h: Improve description of MT flags.
 416
 417 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 418
 419         * m68k.h (mcf_mask): Define.
 420
 421 2006-05-05  Thiemo Seufer  <ths@mips.com>
 422             David Ung  <davidu@mips.com>
 423
 424         * mips.h (enum): Add macro M_CACHE_AB.
 425
 426 2006-05-04  Thiemo Seufer  <ths@mips.com>
 427             Nigel Stephens  <nigel@mips.com>
 428             David Ung  <davidu@mips.com>
 429
 430         * mips.h: Add INSN_SMARTMIPS define.
 431
 432 2006-04-30  Thiemo Seufer  <ths@mips.com>
 433             David Ung  <davidu@mips.com>
 434
 435         * mips.h: Defines udi bits and masks.  Add description of
 436         characters which may appear in the args field of udi
 437         instructions.
 438
 439 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 440
 441         * mips.h: Improve comments describing the bitfield instruction
 442         fields.
 443
 444 2006-04-26  Julian Brown  <julian@codesourcery.com>
 445
 446         * arm.h (FPU_VFP_EXT_V3): Define constant.
 447         (FPU_NEON_EXT_V1): Likewise.
 448         (FPU_VFP_HARD): Update.
 449         (FPU_VFP_V3): Define macro.
 450         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 451
 452 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 453
 454         * avr.h (AVR_ISA_PWMx): New.
 455
 456 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 457
 458         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 459         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 460         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 461         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 462         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 463
 464 2006-03-10  Paul Brook  <paul@codesourcery.com>
 465
 466         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 467
 468 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 469
 470         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 471         first.  Correct mask of bb "B" opcode.
 472
 473 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 474
 475         * i386.h (i386_optab): Support Intel Merom New Instructions.
 476
 477 2006-02-24  Paul Brook  <paul@codesourcery.com>
 478
 479         * arm.h: Add V7 feature bits.
 480
 481 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 482
 483         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 484
 485 2006-01-31  Paul Brook  <paul@codesourcery.com>
 486         Richard Earnshaw <rearnsha@arm.com>
 487
 488         * arm.h: Use ARM_CPU_FEATURE.
 489         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 490         (arm_feature_set): Change to a structure.
 491         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 492         ARM_FEATURE): New macros.
 493
 494 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 495
 496         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 497         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 498         (ADD_PC_INCR_OPCODE): Don't define.
 499
 500 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 501
 502         PR gas/1874
 503         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 504
 505 2005-11-14  David Ung  <davidu@mips.com>
 506
 507         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 508         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 509         save/restore encoding of the args field.
 510
 511 2005-10-28  Dave Brolley  <brolley@redhat.com>
 512
 513         Contribute the following changes:
 514         2005-02-16  Dave Brolley  <brolley@redhat.com>
 515
 516         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 517         cgen_isa_mask_* to cgen_bitset_*.
 518         * cgen.h: Likewise.
 519
 520         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 521
 522         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 523         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 524         (CGEN_CPU_TABLE): Make isas a ponter.
 525
 526         2003-09-29  Dave Brolley  <brolley@redhat.com>
 527
 528         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 529         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 530         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 531
 532         2002-12-13  Dave Brolley  <brolley@redhat.com>
 533
 534         * cgen.h (symcat.h): #include it.
 535         (cgen-bitset.h): #include it.
 536         (CGEN_ATTR_VALUE_TYPE): Now a union.
 537         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 538         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 539         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 540         * cgen-bitset.h: New file.
 541
 542 2005-09-30  Catherine Moore  <clm@cm00re.com>
 543
 544         * bfin.h: New file.
 545
 546 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 547
 548         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 549         indirect operands.
 550
 551 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 552
 553         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 554         Add FLAG_STRICT to pa10 ftest opcode.
 555
 556 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 557
 558         * hppa.h (pa_opcodes): Remove lha entries.
 559
 560 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 561
 562         * hppa.h (FLAG_STRICT): Revise comment.
 563         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 564         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 565         entries for "fdc".
 566
 567 2005-09-30  Catherine Moore  <clm@cm00re.com>
 568
 569         * bfin.h: New file.
 570
 571 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 572
 573         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 574
 575 2005-09-06  Chao-ying Fu  <fu@mips.com>
 576
 577         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 578         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 579         define.
 580         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 581         (INSN_ASE_MASK): Update to include INSN_MT.
 582         (INSN_MT): New define for MT ASE.
 583
 584 2005-08-25  Chao-ying Fu  <fu@mips.com>
 585
 586         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 587         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 588         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 589         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 590         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 591         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 592         instructions.
 593         (INSN_DSP): New define for DSP ASE.
 594
 595 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 596
 597         * a29k.h: Delete.
 598
 599 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 600
 601         * ppc.h (PPC_OPCODE_E300): Define.
 602
 603 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 604
 605         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 606
 607 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 608
 609         PR gas/336
 610         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 611         and pitlb.
 612
 613 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 614
 615         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 616         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 617         Add movq-s as 64-bit variants of movd-s.
 618
 619 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 620
 621         * hppa.h: Fix punctuation in comment.
 622
 623         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 624         implicit space-register addressing.  Set space-register bits on opcodes
 625         using implicit space-register addressing.  Add various missing pa20
 626         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 627         space-register addressing.  Use "fE" instead of "fe" in various
 628         fstw opcodes.
 629
 630 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 631
 632         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 633
 634 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 635
 636         * i386.h (i386_optab): Support Intel VMX Instructions.
 637
 638 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 639
 640         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 641
 642 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 643
 644         * i386.h (i386_optab): Add new insns.
 645
 646 2005-07-01  Nick Clifton  <nickc@redhat.com>
 647
 648         * sparc.h: Add typedefs to structure declarations.
 649
 650 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 651
 652         PR 1013
 653         * i386.h (i386_optab): Update comments for 64bit addressing on
 654         mov. Allow 64bit addressing for mov and movq.
 655
 656 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 657
 658         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 659         respectively, in various floating-point load and store patterns.
 660
 661 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 662
 663         * hppa.h (FLAG_STRICT): Correct comment.
 664         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 665         PA 2.0 mneumonics when equivalent.  Entries with cache control
 666         completers now require PA 1.1.  Adjust whitespace.
 667
 668 2005-05-19  Anton Blanchard  <anton@samba.org>
 669
 670         * ppc.h (PPC_OPCODE_POWER5): Define.
 671
 672 2005-05-10  Nick Clifton  <nickc@redhat.com>
 673
 674         * Update the address and phone number of the FSF organization in
 675         the GPL notices in the following files:
 676         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 677         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 678         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 679         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 680         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 681         tic54x.h, tic80.h, v850.h, vax.h
 682
 683 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 684
 685         * i386.h (i386_optab): Add ht and hnt.
 686
 687 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 688
 689         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 690         Add xcrypt-ctr.  Provide aliases without hyphens.
 691
 692 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 693
 694         Moved from ../ChangeLog
 695
 696         2005-04-12  Paul Brook  <paul@codesourcery.com>
 697         * m88k.h: Rename psr macros to avoid conflicts.
 698
 699         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 700         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 701         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 702         and ARM_ARCH_V6ZKT2.
 703
 704         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 705         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 706         Remove redundant instruction types.
 707         (struct argument): X_op - new field.
 708         (struct cst4_entry): Remove.
 709         (no_op_insn): Declare.
 710
 711         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 712         * crx.h (enum argtype): Rename types, remove unused types.
 713
 714         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 715         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 716         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 717         (enum operand_type): Rearrange operands, edit comments.
 718         replace us<N> with ui<N> for unsigned immediate.
 719         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 720         displacements (respectively).
 721         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 722         (instruction type): Add NO_TYPE_INS.
 723         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 724         (operand_entry): New field - 'flags'.
 725         (operand flags): New.
 726
 727         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 728         * crx.h (operand_type): Remove redundant types i3, i4,
 729         i5, i8, i12.
 730         Add new unsigned immediate types us3, us4, us5, us16.
 731
 732 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 733
 734         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 735         adjust them accordingly.
 736
 737 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 738
 739         * i386.h (i386_optab): Add rdtscp.
 740
 741 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 742
 743         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 744         between memory and segment register. Allow movq for moving between
 745         general-purpose register and segment register.
 746
 747 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 748
 749         PR gas/707
 750         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 751         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 752         fnstsw.
 753
 754 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 755
 756         * m68k.h (m68008, m68ec030, m68882): Remove.
 757         (m68k_mask): New.
 758         (cpu_m68k, cpu_cf): New.
 759         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 760         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 761
 762 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 763
 764         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 765         * cgen.h (enum cgen_parse_operand_type): Add
 766         CGEN_PARSE_OPERAND_SYMBOLIC.
 767
 768 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 769
 770         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 771         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 772         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 773
 774 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 775
 776         * mips.h (struct mips_opcode): Add new pinfo2 member.
 777         (INSN_ALIAS): New define for opcode table entries that are
 778         specific instances of another entry, such as 'move' for an 'or'
 779         with a zero operand.
 780         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 781         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 782
 783 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 784
 785         * mips.h (CPU_RM9000): Define.
 786         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 787
 788 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 789
 790         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 791         to/from test registers are illegal in 64-bit mode. Add missing
 792         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 793         (previously one had to explicitly encode a rex64 prefix). Re-enable
 794         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 795         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 796
 797 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 798
 799         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 800         available only with SSE2. Change the MMX additions introduced by SSE
 801         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 802         instructions by their now designated identifier (since combining i686
 803         and 3DNow! does not really imply 3DNow!A).
 804
 805 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 806
 807         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 808         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 809
 810 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 811             Vineet Sharma      <vineets@noida.hcltech.com>
 812
 813         * maxq.h: New file: Disassembly information for the maxq port.
 814
 815 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 816
 817         * i386.h (i386_optab): Put back "movzb".
 818
 819 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 820
 821         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 822         comments.  Remove member cris_ver_sim.  Add members
 823         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 824         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 825         (struct cris_support_reg, struct cris_cond15): New types.
 826         (cris_conds15): Declare.
 827         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 828         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 829         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 830         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 831         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 832         SIZE_FIELD_UNSIGNED.
 833
 834 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 835
 836         * i386.h (sldx_Suf): Remove.
 837         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 838         (q_FP): Define, implying no REX64.
 839         (x_FP, sl_FP): Imply FloatMF.
 840         (i386_optab): Split reg and mem forms of moving from segment registers
 841         so that the memory forms can ignore the 16-/32-bit operand size
 842         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 843         all non-floating-point instructions. Unite 32- and 64-bit forms of
 844         movsx, movzx, and movd. Adjust floating point operations for the above
 845         changes to the *FP macros. Add DefaultSize to floating point control
 846         insns operating on larger memory ranges. Remove left over comments
 847         hinting at certain insns being Intel-syntax ones where the ones
 848         actually meant are already gone.
 849
 850 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 851
 852         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 853         instruction type.
 854
 855 2004-09-30  Paul Brook  <paul@codesourcery.com>
 856
 857         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 858         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 859
 860 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 861
 862         * avr.h: Add support for
 863         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 864
 865 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 866
 867         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 868
 869 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 870
 871         * msp430.h (msp430_opc): Add new instructions.
 872         (msp430_rcodes): Declare new instructions.
 873         (msp430_hcodes): Likewise..
 874
 875 2004-08-13  Nick Clifton  <nickc@redhat.com>
 876
 877         PR/301
 878         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 879         processors.
 880
 881 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 882
 883         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 884
 885 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 886
 887         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 888
 889 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 890
 891         * i386.h: Adjust instruction descriptions to better match the
 892         specification.
 893
 894 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 895
 896         * arm.h: Remove all old content.  Replace with architecture defines
 897         from gas/config/tc-arm.c.
 898
 899 2004-07-09  Andreas Schwab  <schwab@suse.de>
 900
 901         * m68k.h: Fix comment.
 902
 903 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 904
 905         * crx.h: New file.
 906
 907 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 908
 909         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 910
 911 2004-05-24  Peter Barada  <peter@the-baradas.com>
 912
 913         * m68k.h: Add 'size' to m68k_opcode.
 914
 915 2004-05-05  Peter Barada  <peter@the-baradas.com>
 916
 917         * m68k.h: Switch from ColdFire chip name to core variant.
 918
 919 2004-04-22  Peter Barada  <peter@the-baradas.com>
 920
 921         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 922         descriptions for new EMAC cases.
 923         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 924         handle Motorola MAC syntax.
 925         Allow disassembly of ColdFire V4e object files.
 926
 927 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 928
 929         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 930
 931 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 932
 933         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 934
 935 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 936
 937         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 938
 939 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 940
 941         * i386.h (i386_optab): Added xstore/xcrypt insns.
 942
 943 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 944
 945         * h8300.h (32bit ldc/stc): Add relaxing support.
 946
 947 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 948
 949         * h8300.h (BITOP): Pass MEMRELAX flag.
 950
 951 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 952
 953         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 954         except for the H8S.
 955
 956 For older changes see ChangeLog-9103
 957 \f
 958 Local Variables:
 959 mode: change-log
 960 left-margin: 8
 961 fill-column: 74
 962 version-control: never
 963 End: