1 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
3 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
5 (ARM_ARCH_V8_1A_FP): New.
6 (ARM_ARCH_V8_1A_SIMD): New.
7 (ARM_ARCH_V8_1A_CRYPTOV1): New.
8 (ARM_FEATURE_CORE): New.
10 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
12 * arm.h (ARM_EXT2_PAN): New.
13 (ARM_FEATURE_CORE_HIGH): New.
15 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
17 * arm.h (ARM_FEATURE_ALL): New.
19 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
21 * aarch64.h (AARCH64_FEATURE_RDMA): New.
23 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
25 * aarch64.h (AARCH64_FEATURE_LOR): New.
27 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
29 * aarch64.h (AARCH64_FEATURE_PAN): New.
30 (aarch64_sys_reg_supported_p): Declare.
31 (aarch64_pstatefield_supported_p): Declare.
33 2015-04-30 DJ Delorie <dj@redhat.com>
35 * rl78.h (RL78_Dis_Isa): New.
36 (rl78_decode_opcode): Add ISA parameter.
38 2015-03-24 Terry Guo <terry.guo@arm.com>
40 * arm.h (arm_feature_set): Extended to provide more available bits.
41 (ARM_ANY): Updated to follow above new definition.
42 (ARM_CPU_HAS_FEATURE): Likewise.
43 (ARM_CPU_IS_ANY): Likewise.
44 (ARM_MERGE_FEATURE_SETS): Likewise.
45 (ARM_CLEAR_FEATURE): Likewise.
46 (ARM_FEATURE): Likewise.
47 (ARM_FEATURE_COPY): New macro.
48 (ARM_FEATURE_EQUAL): Likewise.
49 (ARM_FEATURE_ZERO): Likewise.
50 (ARM_FEATURE_CORE_EQUAL): Likewise.
51 (ARM_FEATURE_LOW): Likewise.
52 (ARM_FEATURE_CORE_LOW): Likewise.
53 (ARM_FEATURE_CORE_COPROC): Likewise.
55 2015-02-19 Pedro Alves <palves@redhat.com>
57 * cgen.h [__cplusplus]: Wrap in extern "C".
58 * msp430-decode.h [__cplusplus]: Likewise.
59 * nios2.h [__cplusplus]: Likewise.
60 * rl78.h [__cplusplus]: Likewise.
61 * rx.h [__cplusplus]: Likewise.
62 * tilegx.h [__cplusplus]: Likewise.
64 2015-01-28 James Bowman <james.bowman@ftdichip.com>
68 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
70 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
72 2015-01-01 Alan Modra <amodra@gmail.com>
74 Update year range in copyright notice of all files.
76 2014-12-27 Anthony Green <green@moxielogic.com>
78 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
79 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
81 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
85 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
87 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
88 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
89 (NIOS2_INSN_OPTARG): Renumber.
91 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
93 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
94 declaration. Fix obsolete comment.
96 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
98 * nios2.h (enum iw_format_type): New.
99 (struct nios2_opcode): Update comments. Add size and format fields.
100 (NIOS2_INSN_OPTARG): New.
101 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
102 (struct nios2_reg): Add regtype field.
103 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
104 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
105 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
106 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
107 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
108 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
109 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
110 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
111 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
112 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
113 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
114 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
115 (OP_MASK_OP, OP_SH_OP): Delete.
116 (OP_MASK_IOP, OP_SH_IOP): Delete.
117 (OP_MASK_IRD, OP_SH_IRD): Delete.
118 (OP_MASK_IRT, OP_SH_IRT): Delete.
119 (OP_MASK_IRS, OP_SH_IRS): Delete.
120 (OP_MASK_ROP, OP_SH_ROP): Delete.
121 (OP_MASK_RRD, OP_SH_RRD): Delete.
122 (OP_MASK_RRT, OP_SH_RRT): Delete.
123 (OP_MASK_RRS, OP_SH_RRS): Delete.
124 (OP_MASK_JOP, OP_SH_JOP): Delete.
125 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
126 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
127 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
128 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
129 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
130 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
131 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
132 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
133 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
134 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
135 (OP_MASK_<insn>, OP_MASK): Delete.
136 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
137 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
138 Include nios2r1.h to define new instruction opcode constants
140 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
141 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
142 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
143 (NUMOPCODES, NUMREGISTERS): Delete.
144 * nios2r1.h: New file.
146 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
148 * sparc.h (HWCAP2_VIS3B): Documentation improved.
150 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
152 * sparc.h (sparc_opcode): new field `hwcaps2'.
153 (HWCAP2_FJATHPLUS): New define.
154 (HWCAP2_VIS3B): Likewise.
155 (HWCAP2_ADP): Likewise.
156 (HWCAP2_SPARC5): Likewise.
157 (HWCAP2_MWAIT): Likewise.
158 (HWCAP2_XMPMUL): Likewise.
159 (HWCAP2_XMONT): Likewise.
160 (HWCAP2_NSEC): Likewise.
161 (HWCAP2_FJATHHPC): Likewise.
162 (HWCAP2_FJDES): Likewise.
163 (HWCAP2_FJAES): Likewise.
164 Document the new operand kind `{', corresponding to the mcdper
165 ancillary state register.
166 Document the new operand kind }, which represents frsd floating
167 point registers (double precision) which must be the same than
168 frs1 in its containing instruction.
170 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
172 * nds32.h: Add new opcode declaration.
174 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
175 Matthew Fortune <matthew.fortune@imgtec.com>
177 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
178 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
179 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
180 +I, +O, +R, +:, +\, +", +;
181 (mips_check_prev_operand): New struct.
182 (INSN2_FORBIDDEN_SLOT): New define.
183 (INSN_ISA32R6): New define.
184 (INSN_ISA64R6): New define.
185 (INSN_UPTO32R6): New define.
186 (INSN_UPTO64R6): New define.
187 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
188 (ISA_MIPS32R6): New define.
189 (ISA_MIPS64R6): New define.
190 (CPU_MIPS32R6): New define.
191 (CPU_MIPS64R6): New define.
192 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
194 2014-09-03 Jiong Wang <jiong.wang@arm.com>
196 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
197 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
198 (aarch64_insn_class): Add lse_atomic.
199 (F_LSE_SZ): New field added.
200 (opcode_has_special_coder): Recognize F_LSE_SZ.
202 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
204 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
207 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
209 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
210 (INSN_LOAD_COPROC): New define.
211 (INSN_COPROC_MOVE_DELAY): Rename to...
212 (INSN_COPROC_MOVE): New define.
214 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
215 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
216 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
217 Soundararajan <Sounderarajan.D@atmel.com>
219 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
220 (AVR_ISA_2xxxa): Define ISA without LPM.
221 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
222 Add doc for contraint used in 16 bit lds/sts.
223 Adjust ISA group for icall, ijmp, pop and push.
224 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
226 2014-05-19 Nick Clifton <nickc@redhat.com>
228 * msp430.h (struct msp430_operand_s): Add vshift field.
230 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
232 * mips.h (INSN_ISA_MASK): Updated.
233 (INSN_ISA32R3): New define.
234 (INSN_ISA32R5): New define.
235 (INSN_ISA64R3): New define.
236 (INSN_ISA64R5): New define.
237 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
238 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
239 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
241 (INSN_UPTO32R3): New define.
242 (INSN_UPTO32R5): New define.
243 (INSN_UPTO64R3): New define.
244 (INSN_UPTO64R5): New define.
245 (ISA_MIPS32R3): New define.
246 (ISA_MIPS32R5): New define.
247 (ISA_MIPS64R3): New define.
248 (ISA_MIPS64R5): New define.
249 (CPU_MIPS32R3): New define.
250 (CPU_MIPS32R5): New define.
251 (CPU_MIPS64R3): New define.
252 (CPU_MIPS64R5): New define.
254 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
256 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
258 2014-04-22 Christian Svensson <blue@cmd.nu>
262 2014-03-05 Alan Modra <amodra@gmail.com>
264 Update copyright years.
266 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
268 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
271 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
272 Wei-Cheng Wang <cole945@gmail.com>
274 * nds32.h: New file for Andes NDS32.
276 2013-12-07 Mike Frysinger <vapier@gentoo.org>
278 * bfin.h: Remove +x file mode.
280 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
282 * aarch64.h (aarch64_pstatefields): Change element type to
285 2013-11-18 Renlin Li <Renlin.Li@arm.com>
287 * arm.h (ARM_AEXT_V7VE): New define.
288 (ARM_ARCH_V7VE): New define.
289 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
291 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
295 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
297 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
298 (aarch64_sys_reg_writeonly_p): Ditto.
300 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
302 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
303 (aarch64_sys_reg_writeonly_p): Ditto.
305 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
307 * aarch64.h (aarch64_sys_reg): New typedef.
308 (aarch64_sys_regs): Change to define with the new type.
309 (aarch64_sys_reg_deprecated_p): Declare.
311 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
313 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
314 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
316 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
318 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
319 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
320 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
321 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
322 For MIPS, update extension character sequences after +.
323 (ASE_MSA): New define.
324 (ASE_MSA64): New define.
325 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
326 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
327 For microMIPS, update extension character sequences after +.
329 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
334 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
336 * mips.h: Remove references to "+I" and imm2_expr.
338 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
340 * mips.h (M_DEXT, M_DINS): Delete.
342 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
344 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
345 (mips_optional_operand_p): New function.
347 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
348 Richard Sandiford <rdsandiford@googlemail.com>
350 * mips.h: Document new VU0 operand characters.
351 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
352 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
353 (OP_REG_R5900_ACC): New mips_reg_operand_types.
354 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
355 (mips_vu0_channel_mask): Declare.
357 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
359 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
360 (mips_int_operand_min, mips_int_operand_max): New functions.
361 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
363 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
365 * mips.h (mips_decode_reg_operand): New function.
366 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
367 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
368 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
370 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
371 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
372 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
373 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
374 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
375 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
376 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
377 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
378 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
379 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
380 macros to cover the gaps.
381 (INSN2_MOD_SP): Replace with...
382 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
383 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
384 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
385 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
386 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
389 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
391 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
392 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
393 (MIPS16_INSN_COND_BRANCH): Delete.
395 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
396 Kirill Yukhin <kirill.yukhin@intel.com>
397 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
399 * i386.h (BND_PREFIX_OPCODE): New.
401 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
403 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
404 OP_SAVE_RESTORE_LIST.
405 (decode_mips16_operand): Declare.
407 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
409 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
410 (mips_operand, mips_int_operand, mips_mapped_int_operand)
411 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
412 (mips_pcrel_operand): New structures.
413 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
414 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
415 (decode_mips_operand, decode_micromips_operand): Declare.
417 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
419 * mips.h: Document MIPS16 "I" opcode.
421 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
423 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
424 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
425 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
426 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
427 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
428 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
429 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
430 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
431 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
432 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
433 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
434 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
435 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
437 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
438 (M_USD_AB): ...these.
440 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
442 * mips.h: Remove documentation of "[" and "]". Update documentation
443 of "k" and the MDMX formats.
445 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
447 * mips.h: Update documentation of "+s" and "+S".
449 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
451 * mips.h: Document "+i".
453 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
455 * mips.h: Remove "mi" documentation. Update "mh" documentation.
456 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
458 (INSN2_WRITE_GPR_MHI): Rename to...
459 (INSN2_WRITE_GPR_MH): ...this.
461 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
463 * mips.h: Remove documentation of "+D" and "+T".
465 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
467 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
468 Use "source" rather than "destination" for microMIPS "G".
470 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
472 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
475 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
477 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
479 2013-06-17 Catherine Moore <clm@codesourcery.com>
480 Maciej W. Rozycki <macro@codesourcery.com>
481 Chao-Ying Fu <fu@mips.com>
483 * mips.h (OP_SH_EVAOFFSET): Define.
484 (OP_MASK_EVAOFFSET): Define.
485 (INSN_ASE_MASK): Delete.
487 (M_CACHEE_AB, M_CACHEE_OB): New.
488 (M_LBE_OB, M_LBE_AB): New.
489 (M_LBUE_OB, M_LBUE_AB): New.
490 (M_LHE_OB, M_LHE_AB): New.
491 (M_LHUE_OB, M_LHUE_AB): New.
492 (M_LLE_AB, M_LLE_OB): New.
493 (M_LWE_OB, M_LWE_AB): New.
494 (M_LWLE_AB, M_LWLE_OB): New.
495 (M_LWRE_AB, M_LWRE_OB): New.
496 (M_PREFE_AB, M_PREFE_OB): New.
497 (M_SCE_AB, M_SCE_OB): New.
498 (M_SBE_OB, M_SBE_AB): New.
499 (M_SHE_OB, M_SHE_AB): New.
500 (M_SWE_OB, M_SWE_AB): New.
501 (M_SWLE_AB, M_SWLE_OB): New.
502 (M_SWRE_AB, M_SWRE_OB): New.
503 (MICROMIPSOP_SH_EVAOFFSET): Define.
504 (MICROMIPSOP_MASK_EVAOFFSET): Define.
506 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
508 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
510 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
512 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
514 2013-05-09 Andrew Pinski <apinski@cavium.com>
516 * mips.h (OP_MASK_CODE10): Correct definition.
517 (OP_SH_CODE10): Likewise.
518 Add a comment that "+J" is used now for OP_*CODE10.
519 (INSN_ASE_MASK): Update.
520 (INSN_VIRT): New macro.
521 (INSN_VIRT64): New macro
523 2013-05-02 Nick Clifton <nickc@redhat.com>
525 * msp430.h: Add patterns for MSP430X instructions.
527 2013-04-06 David S. Miller <davem@davemloft.net>
529 * sparc.h (F_PREFERRED): Define.
530 (F_PREF_ALIAS): Define.
532 2013-04-03 Nick Clifton <nickc@redhat.com>
534 * v850.h (V850_INVERSE_PCREL): Define.
536 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
539 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
541 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
544 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
546 * tic6xc-opcode-table.h: Add 16-bit insns.
547 * tic6x.h: Add support for 16-bit insns.
549 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
551 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
552 and mov.b/w/l Rs,@(d:32,ERd).
554 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
557 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
558 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
559 tic6x_operand_xregpair operand coding type.
560 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
561 opcode field, usu ORXREGD1324 for the src2 operand and remove the
564 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
567 * tic6x.h (enum tic6x_coding_method): Add
568 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
569 separately the msb and lsb of a register pair. This is needed to
570 encode the opcodes in the same way as TI assembler does.
571 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
572 and rsqrdp opcodes to use the new field coding types.
574 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
576 * arm.h (CRC_EXT_ARMV8): New constant.
577 (ARCH_CRC_ARMV8): New macro.
579 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
581 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
583 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
584 Andrew Jenner <andrew@codesourcery.com>
586 Based on patches from Altera Corporation.
590 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
592 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
594 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
597 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
599 2013-01-24 Nick Clifton <nickc@redhat.com>
601 * v850.h: Add e3v5 support.
603 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
605 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
607 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
609 * ppc.h (PPC_OPCODE_POWER8): New define.
610 (PPC_OPCODE_HTM): Likewise.
612 2013-01-10 Will Newton <will.newton@imgtec.com>
616 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
618 * cr16.h (make_instruction): Rename to cr16_make_instruction.
619 (match_opcode): Rename to cr16_match_opcode.
621 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
623 * mips.h: Add support for r5900 instructions including lq and sq.
625 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
627 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
628 (make_instruction,match_opcode): Added function prototypes.
629 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
631 2012-11-23 Alan Modra <amodra@gmail.com>
633 * ppc.h (ppc_parse_cpu): Update prototype.
635 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
637 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
638 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
640 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
642 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
644 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
646 * ia64.h (ia64_opnd): Add new operand types.
648 2012-08-21 David S. Miller <davem@davemloft.net>
650 * sparc.h (F3F4): New macro.
652 2012-08-13 Ian Bolton <ian.bolton@arm.com>
653 Laurent Desnogues <laurent.desnogues@arm.com>
654 Jim MacArthur <jim.macarthur@arm.com>
655 Marcus Shawcroft <marcus.shawcroft@arm.com>
656 Nigel Stephens <nigel.stephens@arm.com>
657 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
658 Richard Earnshaw <rearnsha@arm.com>
659 Sofiane Naci <sofiane.naci@arm.com>
660 Tejas Belagod <tejas.belagod@arm.com>
661 Yufeng Zhang <yufeng.zhang@arm.com>
663 * aarch64.h: New file.
665 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
666 Maciej W. Rozycki <macro@codesourcery.com>
668 * mips.h (mips_opcode): Add the exclusions field.
669 (OPCODE_IS_MEMBER): Remove macro.
670 (cpu_is_member): New inline function.
671 (opcode_is_member): Likewise.
673 2012-07-31 Chao-Ying Fu <fu@mips.com>
674 Catherine Moore <clm@codesourcery.com>
675 Maciej W. Rozycki <macro@codesourcery.com>
677 * mips.h: Document microMIPS DSP ASE usage.
678 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
679 microMIPS DSP ASE support.
680 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
681 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
682 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
683 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
684 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
685 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
686 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
688 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
690 * mips.h: Fix a typo in description.
692 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
694 * avr.h: (AVR_ISA_XCH): New define.
695 (AVR_ISA_XMEGA): Use it.
696 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
698 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
700 * m68hc11.h: Add XGate definitions.
701 (struct m68hc11_opcode): Add xg_mask field.
703 2012-05-14 Catherine Moore <clm@codesourcery.com>
704 Maciej W. Rozycki <macro@codesourcery.com>
705 Rhonda Wittels <rhonda@codesourcery.com>
707 * ppc.h (PPC_OPCODE_VLE): New definition.
708 (PPC_OP_SA): New macro.
709 (PPC_OP_SE_VLE): New macro.
710 (PPC_OP): Use a variable shift amount.
711 (powerpc_operand): Update comments.
712 (PPC_OPSHIFT_INV): New macro.
713 (PPC_OPERAND_CR): Replace with...
714 (PPC_OPERAND_CR_BIT): ...this and
715 (PPC_OPERAND_CR_REG): ...this.
718 2012-05-03 Sean Keys <skeys@ipdatasys.com>
720 * xgate.h: Header file for XGATE assembler.
722 2012-04-27 David S. Miller <davem@davemloft.net>
724 * sparc.h: Document new arg code' )' for crypto RS3
727 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
728 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
729 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
730 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
731 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
732 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
733 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
734 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
735 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
736 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
737 HWCAP_CBCOND, HWCAP_CRC32): New defines.
739 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
741 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
743 2012-02-27 Alan Modra <amodra@gmail.com>
745 * crx.h (cst4_map): Update declaration.
747 2012-02-25 Walter Lee <walt@tilera.com>
749 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
751 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
752 TILEPRO_OPC_LW_TLS_SN.
754 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
756 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
757 (XRELEASE_PREFIX_OPCODE): Likewise.
759 2011-12-08 Andrew Pinski <apinski@cavium.com>
760 Adam Nemet <anemet@caviumnetworks.com>
762 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
763 (INSN_OCTEON2): New macro.
764 (CPU_OCTEON2): New macro.
765 (OPCODE_IS_MEMBER): Add Octeon2.
767 2011-11-29 Andrew Pinski <apinski@cavium.com>
769 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
770 (INSN_OCTEONP): New macro.
771 (CPU_OCTEONP): New macro.
772 (OPCODE_IS_MEMBER): Add Octeon+.
773 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
775 2011-11-01 DJ Delorie <dj@redhat.com>
779 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
781 * mips.h: Fix a typo in description.
783 2011-09-21 David S. Miller <davem@davemloft.net>
785 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
786 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
787 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
788 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
790 2011-08-09 Chao-ying Fu <fu@mips.com>
791 Maciej W. Rozycki <macro@codesourcery.com>
793 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
794 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
795 (INSN_ASE_MASK): Add the MCU bit.
796 (INSN_MCU): New macro.
797 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
798 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
800 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
802 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
803 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
804 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
805 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
806 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
807 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
808 (INSN2_READ_GPR_MMN): Likewise.
809 (INSN2_READ_FPR_D): Change the bit used.
810 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
811 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
812 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
813 (INSN2_COND_BRANCH): Likewise.
814 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
815 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
816 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
817 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
818 (INSN2_MOD_GPR_MN): Likewise.
820 2011-08-05 David S. Miller <davem@davemloft.net>
822 * sparc.h: Document new format codes '4', '5', and '('.
823 (OPF_LOW4, RS3): New macros.
825 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
827 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
828 order of flags documented.
830 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
832 * mips.h: Clarify the description of microMIPS instruction
834 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
836 2011-07-24 Chao-ying Fu <fu@mips.com>
837 Maciej W. Rozycki <macro@codesourcery.com>
839 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
840 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
841 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
842 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
843 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
844 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
845 (OP_MASK_RS3, OP_SH_RS3): Likewise.
846 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
847 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
848 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
849 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
850 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
851 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
852 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
853 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
854 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
855 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
856 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
857 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
858 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
859 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
860 (INSN_WRITE_GPR_S): New macro.
861 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
862 (INSN2_READ_FPR_D): Likewise.
863 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
864 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
865 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
866 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
867 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
868 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
869 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
870 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
871 (CPU_MICROMIPS): New macro.
872 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
873 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
874 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
875 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
876 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
877 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
878 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
879 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
880 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
881 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
882 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
883 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
884 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
885 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
886 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
887 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
888 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
889 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
890 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
891 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
892 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
893 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
894 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
895 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
896 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
897 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
898 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
899 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
900 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
901 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
902 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
903 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
904 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
905 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
906 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
907 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
908 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
909 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
910 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
911 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
912 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
913 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
914 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
915 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
916 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
917 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
918 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
919 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
920 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
921 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
922 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
923 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
924 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
925 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
926 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
927 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
928 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
929 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
930 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
931 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
932 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
933 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
934 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
935 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
936 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
937 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
938 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
939 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
940 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
941 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
942 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
943 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
944 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
945 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
946 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
947 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
948 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
949 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
950 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
951 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
952 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
953 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
954 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
955 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
956 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
957 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
958 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
959 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
960 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
961 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
962 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
963 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
964 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
965 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
966 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
967 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
968 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
969 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
970 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
971 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
972 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
973 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
974 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
975 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
976 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
977 (micromips_opcodes): New declaration.
978 (bfd_micromips_num_opcodes): Likewise.
980 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
982 * mips.h (INSN_TRAP): Rename to...
983 (INSN_NO_DELAY_SLOT): ... this.
984 (INSN_SYNC): Remove macro.
986 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
988 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
989 a duplicate of AVR_ISA_SPM.
991 2011-07-01 Nick Clifton <nickc@redhat.com>
993 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
995 2011-06-18 Robin Getz <robin.getz@analog.com>
997 * bfin.h (is_macmod_signed): New func
999 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1001 * bfin.h (is_macmod_pmove): Add missing space before func args.
1002 (is_macmod_hmove): Likewise.
1004 2011-06-13 Walter Lee <walt@tilera.com>
1006 * tilegx.h: New file.
1007 * tilepro.h: New file.
1009 2011-05-31 Paul Brook <paul@codesourcery.com>
1011 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1013 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1015 * s390.h: Replace S390_OPERAND_REG_EVEN with
1016 S390_OPERAND_REG_PAIR.
1018 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1020 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1022 2011-04-18 Julian Brown <julian@codesourcery.com>
1024 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1026 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1029 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1031 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1033 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1034 New instruction set flags.
1035 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1037 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1039 * mips.h (M_PREF_AB): New enum value.
1041 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1043 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1045 (is_macmod_pmove, is_macmod_hmove): New functions.
1047 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1049 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1051 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1053 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1054 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1056 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1059 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1062 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1065 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1067 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1069 * mips.h: Update commentary after last commit.
1071 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1073 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1074 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1075 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1077 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1079 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1081 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1083 * mips.h: Fix previous commit.
1085 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1087 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1088 (INSN_LOONGSON_3A): Clear bit 31.
1090 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1093 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1094 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1095 (ARM_ARCH_V6M_ONLY): New define.
1097 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1099 * mips.h (INSN_LOONGSON_3A): Defined.
1100 (CPU_LOONGSON_3A): Defined.
1101 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1103 2010-10-09 Matt Rice <ratmice@gmail.com>
1105 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1106 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1108 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1110 * arm.h (ARM_EXT_VIRT): New define.
1111 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1112 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1115 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1117 * arm.h (ARM_AEXT_ADIV): New define.
1118 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1120 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1122 * arm.h (ARM_EXT_OS): New define.
1123 (ARM_AEXT_V6SM): Likewise.
1124 (ARM_ARCH_V6SM): Likewise.
1126 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1128 * arm.h (ARM_EXT_MP): Add.
1129 (ARM_ARCH_V7A_MP): Likewise.
1131 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1133 * bfin.h: Declare pseudoChr structs/defines.
1135 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1137 * bfin.h: Strip trailing whitespace.
1139 2010-07-29 DJ Delorie <dj@redhat.com>
1141 * rx.h (RX_Operand_Type): Add TwoReg.
1142 (RX_Opcode_ID): Remove ediv and ediv2.
1144 2010-07-27 DJ Delorie <dj@redhat.com>
1146 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1148 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1149 Ina Pandit <ina.pandit@kpitcummins.com>
1151 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1152 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1153 PROCESSOR_V850E2_ALL.
1154 Remove PROCESSOR_V850EA support.
1155 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1156 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1157 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1158 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1159 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1160 V850_OPERAND_PERCENT.
1161 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1163 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1166 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1168 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1169 (MIPS16_INSN_BRANCH): Rename to...
1170 (MIPS16_INSN_COND_BRANCH): ... this.
1172 2010-07-03 Alan Modra <amodra@gmail.com>
1174 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1175 Renumber other PPC_OPCODE defines.
1177 2010-07-03 Alan Modra <amodra@gmail.com>
1179 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1181 2010-06-29 Alan Modra <amodra@gmail.com>
1183 * maxq.h: Delete file.
1185 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1187 * ppc.h (PPC_OPCODE_E500): Define.
1189 2010-05-26 Catherine Moore <clm@codesourcery.com>
1191 * opcode/mips.h (INSN_MIPS16): Remove.
1193 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1195 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1197 2010-04-15 Nick Clifton <nickc@redhat.com>
1199 * alpha.h: Update copyright notice to use GPLv3.
1205 * convex.h: Likewise.
1212 * h8300.h: Likewise.
1219 * m68hc11.h: Likewise.
1225 * mn10200.h: Likewise.
1226 * mn10300.h: Likewise.
1227 * msp430.h: Likewise.
1229 * ns32k.h: Likewise.
1231 * pdp11.h: Likewise.
1238 * score-datadep.h: Likewise.
1239 * score-inst.h: Likewise.
1240 * sparc.h: Likewise.
1241 * spu-insns.h: Likewise.
1243 * tic30.h: Likewise.
1244 * tic4x.h: Likewise.
1245 * tic54x.h: Likewise.
1246 * tic80.h: Likewise.
1250 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1252 * tic6x-control-registers.h, tic6x-insn-formats.h,
1253 tic6x-opcode-table.h, tic6x.h: New.
1255 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1257 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1259 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1261 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1263 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1265 * ia64.h (ia64_find_opcode): Remove argument name.
1266 (ia64_find_next_opcode): Likewise.
1267 (ia64_dis_opcode): Likewise.
1268 (ia64_free_opcode): Likewise.
1269 (ia64_find_dependency): Likewise.
1271 2009-11-22 Doug Evans <dje@sebabeach.org>
1273 * cgen.h: Include bfd_stdint.h.
1274 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1276 2009-11-18 Paul Brook <paul@codesourcery.com>
1278 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1280 2009-11-17 Paul Brook <paul@codesourcery.com>
1281 Daniel Jacobowitz <dan@codesourcery.com>
1283 * arm.h (ARM_EXT_V6_DSP): Define.
1284 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1285 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1287 2009-11-04 DJ Delorie <dj@redhat.com>
1289 * rx.h (rx_decode_opcode) (mvtipl): Add.
1290 (mvtcp, mvfcp, opecp): Remove.
1292 2009-11-02 Paul Brook <paul@codesourcery.com>
1294 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1295 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1296 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1297 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1298 FPU_ARCH_NEON_VFP_V4): Define.
1300 2009-10-23 Doug Evans <dje@sebabeach.org>
1302 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1303 * cgen.h: Update. Improve multi-inclusion macro name.
1305 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1307 * ppc.h (PPC_OPCODE_476): Define.
1309 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1311 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1313 2009-09-29 DJ Delorie <dj@redhat.com>
1317 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1319 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1321 2009-09-21 Ben Elliston <bje@au.ibm.com>
1323 * ppc.h (PPC_OPCODE_PPCA2): New.
1325 2009-09-05 Martin Thuresson <martin@mtme.org>
1327 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1329 2009-08-29 Martin Thuresson <martin@mtme.org>
1331 * tic30.h (template): Rename type template to
1332 insn_template. Updated code to use new name.
1333 * tic54x.h (template): Rename type template to
1336 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1338 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1340 2009-06-11 Anthony Green <green@moxielogic.com>
1342 * moxie.h (MOXIE_F3_PCREL): Define.
1343 (moxie_form3_opc_info): Grow.
1345 2009-06-06 Anthony Green <green@moxielogic.com>
1347 * moxie.h (MOXIE_F1_M): Define.
1349 2009-04-15 Anthony Green <green@moxielogic.com>
1353 2009-04-06 DJ Delorie <dj@redhat.com>
1355 * h8300.h: Add relaxation attributes to MOVA opcodes.
1357 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1359 * ppc.h (ppc_parse_cpu): Declare.
1361 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1363 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1364 and _IMM11 for mbitclr and mbitset.
1365 * score-datadep.h: Update dependency information.
1367 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1369 * ppc.h (PPC_OPCODE_POWER7): New.
1371 2009-02-06 Doug Evans <dje@google.com>
1373 * i386.h: Add comment regarding sse* insns and prefixes.
1375 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1377 * mips.h (INSN_XLR): Define.
1378 (INSN_CHIP_MASK): Update.
1380 (OPCODE_IS_MEMBER): Update.
1381 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1383 2009-01-28 Doug Evans <dje@google.com>
1385 * opcode/i386.h: Add multiple inclusion protection.
1386 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1387 (EDI_REG_NUM): New macros.
1388 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1389 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1390 (REX_PREFIX_P): New macro.
1392 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1394 * ppc.h (struct powerpc_opcode): New field "deprecated".
1395 (PPC_OPCODE_NOPOWER4): Delete.
1397 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1399 * mips.h: Define CPU_R14000, CPU_R16000.
1400 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1402 2008-11-18 Catherine Moore <clm@codesourcery.com>
1404 * arm.h (FPU_NEON_FP16): New.
1405 (FPU_ARCH_NEON_FP16): New.
1407 2008-11-06 Chao-ying Fu <fu@mips.com>
1409 * mips.h: Doucument '1' for 5-bit sync type.
1411 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1413 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1416 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1418 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1420 2008-07-30 Michael J. Eager <eager@eagercon.com>
1422 * ppc.h (PPC_OPCODE_405): Define.
1423 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1425 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1427 * ppc.h (ppc_cpu_t): New typedef.
1428 (struct powerpc_opcode <flags>): Use it.
1429 (struct powerpc_operand <insert, extract>): Likewise.
1430 (struct powerpc_macro <flags>): Likewise.
1432 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1434 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1435 Update comment before MIPS16 field descriptors to mention MIPS16.
1436 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1438 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1439 New bit masks and shift counts for cins and exts.
1441 * mips.h: Document new field descriptors +Q.
1442 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1444 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1446 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1447 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1449 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1451 * ppc.h: (PPC_OPCODE_E500MC): New.
1453 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1455 * i386.h (MAX_OPERANDS): Set to 5.
1456 (MAX_MNEM_SIZE): Changed to 20.
1458 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1460 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1462 2008-03-09 Paul Brook <paul@codesourcery.com>
1464 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1466 2008-03-04 Paul Brook <paul@codesourcery.com>
1468 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1469 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1470 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1472 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1473 Nick Clifton <nickc@redhat.com>
1476 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1477 with a 32-bit displacement but without the top bit of the 4th byte
1480 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1482 * cr16.h (cr16_num_optab): Declared.
1484 2008-02-14 Hakan Ardo <hakan@debian.org>
1487 * avr.h (AVR_ISA_2xxe): Define.
1489 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1491 * mips.h: Update copyright.
1492 (INSN_CHIP_MASK): New macro.
1493 (INSN_OCTEON): New macro.
1494 (CPU_OCTEON): New macro.
1495 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1497 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1499 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1501 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1503 * avr.h (AVR_ISA_USB162): Add new opcode set.
1504 (AVR_ISA_AVR3): Likewise.
1506 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1508 * mips.h (INSN_LOONGSON_2E): New.
1509 (INSN_LOONGSON_2F): New.
1510 (CPU_LOONGSON_2E): New.
1511 (CPU_LOONGSON_2F): New.
1512 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1514 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1516 * mips.h (INSN_ISA*): Redefine certain values as an
1517 enumeration. Update comments.
1518 (mips_isa_table): New.
1519 (ISA_MIPS*): Redefine to match enumeration.
1520 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1523 2007-08-08 Ben Elliston <bje@au.ibm.com>
1525 * ppc.h (PPC_OPCODE_PPCPS): New.
1527 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1529 * m68k.h: Document j K & E.
1531 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1533 * cr16.h: New file for CR16 target.
1535 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1537 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1539 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1541 * m68k.h (mcfisa_c): New.
1542 (mcfusp, mcf_mask): Adjust.
1544 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1546 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1547 (num_powerpc_operands): Declare.
1548 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1549 (PPC_OPERAND_PLUS1): Define.
1551 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1553 * i386.h (REX_MODE64): Renamed to ...
1555 (REX_EXTX): Renamed to ...
1557 (REX_EXTY): Renamed to ...
1559 (REX_EXTZ): Renamed to ...
1562 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1564 * i386.h: Add entries from config/tc-i386.h and move tables
1565 to opcodes/i386-opc.h.
1567 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1569 * i386.h (FloatDR): Removed.
1570 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1572 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1574 * spu-insns.h: Add soma double-float insns.
1576 2007-02-20 Thiemo Seufer <ths@mips.com>
1577 Chao-Ying Fu <fu@mips.com>
1579 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1580 (INSN_DSPR2): Add flag for DSP R2 instructions.
1581 (M_BALIGN): New macro.
1583 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1585 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1586 and Seg3ShortFrom with Shortform.
1588 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1591 * i386.h (i386_optab): Put the real "test" before the pseudo
1594 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1596 * m68k.h (m68010up): OR fido_a.
1598 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1600 * m68k.h (fido_a): New.
1602 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1604 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1605 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1608 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1610 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1612 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1614 * score-inst.h (enum score_insn_type): Add Insn_internal.
1616 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1617 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1618 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1619 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1620 Alan Modra <amodra@bigpond.net.au>
1622 * spu-insns.h: New file.
1625 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1627 * ppc.h (PPC_OPCODE_CELL): Define.
1629 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1631 * i386.h : Modify opcode to support for the change in POPCNT opcode
1632 in amdfam10 architecture.
1634 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1636 * i386.h: Replace CpuMNI with CpuSSSE3.
1638 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1639 Joseph Myers <joseph@codesourcery.com>
1640 Ian Lance Taylor <ian@wasabisystems.com>
1641 Ben Elliston <bje@wasabisystems.com>
1643 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1645 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1647 * score-datadep.h: New file.
1648 * score-inst.h: New file.
1650 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1652 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1653 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1654 movdq2q and movq2dq.
1656 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1657 Michael Meissner <michael.meissner@amd.com>
1659 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1661 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1663 * i386.h (i386_optab): Add "nop" with memory reference.
1665 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1667 * i386.h (i386_optab): Update comment for 64bit NOP.
1669 2006-06-06 Ben Elliston <bje@au.ibm.com>
1670 Anton Blanchard <anton@samba.org>
1672 * ppc.h (PPC_OPCODE_POWER6): Define.
1675 2006-06-05 Thiemo Seufer <ths@mips.com>
1677 * mips.h: Improve description of MT flags.
1679 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1681 * m68k.h (mcf_mask): Define.
1683 2006-05-05 Thiemo Seufer <ths@mips.com>
1684 David Ung <davidu@mips.com>
1686 * mips.h (enum): Add macro M_CACHE_AB.
1688 2006-05-04 Thiemo Seufer <ths@mips.com>
1689 Nigel Stephens <nigel@mips.com>
1690 David Ung <davidu@mips.com>
1692 * mips.h: Add INSN_SMARTMIPS define.
1694 2006-04-30 Thiemo Seufer <ths@mips.com>
1695 David Ung <davidu@mips.com>
1697 * mips.h: Defines udi bits and masks. Add description of
1698 characters which may appear in the args field of udi
1701 2006-04-26 Thiemo Seufer <ths@networkno.de>
1703 * mips.h: Improve comments describing the bitfield instruction
1706 2006-04-26 Julian Brown <julian@codesourcery.com>
1708 * arm.h (FPU_VFP_EXT_V3): Define constant.
1709 (FPU_NEON_EXT_V1): Likewise.
1710 (FPU_VFP_HARD): Update.
1711 (FPU_VFP_V3): Define macro.
1712 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1714 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1716 * avr.h (AVR_ISA_PWMx): New.
1718 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1720 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1721 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1722 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1723 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1724 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1726 2006-03-10 Paul Brook <paul@codesourcery.com>
1728 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1730 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1732 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1733 first. Correct mask of bb "B" opcode.
1735 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1737 * i386.h (i386_optab): Support Intel Merom New Instructions.
1739 2006-02-24 Paul Brook <paul@codesourcery.com>
1741 * arm.h: Add V7 feature bits.
1743 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1745 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1747 2006-01-31 Paul Brook <paul@codesourcery.com>
1748 Richard Earnshaw <rearnsha@arm.com>
1750 * arm.h: Use ARM_CPU_FEATURE.
1751 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1752 (arm_feature_set): Change to a structure.
1753 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1754 ARM_FEATURE): New macros.
1756 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1758 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1759 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1760 (ADD_PC_INCR_OPCODE): Don't define.
1762 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1765 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1767 2005-11-14 David Ung <davidu@mips.com>
1769 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1770 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1771 save/restore encoding of the args field.
1773 2005-10-28 Dave Brolley <brolley@redhat.com>
1775 Contribute the following changes:
1776 2005-02-16 Dave Brolley <brolley@redhat.com>
1778 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1779 cgen_isa_mask_* to cgen_bitset_*.
1782 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1784 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1785 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1786 (CGEN_CPU_TABLE): Make isas a ponter.
1788 2003-09-29 Dave Brolley <brolley@redhat.com>
1790 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1791 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1792 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1794 2002-12-13 Dave Brolley <brolley@redhat.com>
1796 * cgen.h (symcat.h): #include it.
1797 (cgen-bitset.h): #include it.
1798 (CGEN_ATTR_VALUE_TYPE): Now a union.
1799 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1800 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1801 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1802 * cgen-bitset.h: New file.
1804 2005-09-30 Catherine Moore <clm@cm00re.com>
1808 2005-10-24 Jan Beulich <jbeulich@novell.com>
1810 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1813 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1815 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1816 Add FLAG_STRICT to pa10 ftest opcode.
1818 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1820 * hppa.h (pa_opcodes): Remove lha entries.
1822 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1824 * hppa.h (FLAG_STRICT): Revise comment.
1825 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1826 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1829 2005-09-30 Catherine Moore <clm@cm00re.com>
1833 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1835 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1837 2005-09-06 Chao-ying Fu <fu@mips.com>
1839 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1840 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1842 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1843 (INSN_ASE_MASK): Update to include INSN_MT.
1844 (INSN_MT): New define for MT ASE.
1846 2005-08-25 Chao-ying Fu <fu@mips.com>
1848 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1849 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1850 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1851 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1852 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1853 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1855 (INSN_DSP): New define for DSP ASE.
1857 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1861 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1863 * ppc.h (PPC_OPCODE_E300): Define.
1865 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1867 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1869 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1872 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1875 2005-07-27 Jan Beulich <jbeulich@novell.com>
1877 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1878 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1879 Add movq-s as 64-bit variants of movd-s.
1881 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1883 * hppa.h: Fix punctuation in comment.
1885 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1886 implicit space-register addressing. Set space-register bits on opcodes
1887 using implicit space-register addressing. Add various missing pa20
1888 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1889 space-register addressing. Use "fE" instead of "fe" in various
1892 2005-07-18 Jan Beulich <jbeulich@novell.com>
1894 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1896 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1898 * i386.h (i386_optab): Support Intel VMX Instructions.
1900 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1902 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1904 2005-07-05 Jan Beulich <jbeulich@novell.com>
1906 * i386.h (i386_optab): Add new insns.
1908 2005-07-01 Nick Clifton <nickc@redhat.com>
1910 * sparc.h: Add typedefs to structure declarations.
1912 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1915 * i386.h (i386_optab): Update comments for 64bit addressing on
1916 mov. Allow 64bit addressing for mov and movq.
1918 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1920 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1921 respectively, in various floating-point load and store patterns.
1923 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1925 * hppa.h (FLAG_STRICT): Correct comment.
1926 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1927 PA 2.0 mneumonics when equivalent. Entries with cache control
1928 completers now require PA 1.1. Adjust whitespace.
1930 2005-05-19 Anton Blanchard <anton@samba.org>
1932 * ppc.h (PPC_OPCODE_POWER5): Define.
1934 2005-05-10 Nick Clifton <nickc@redhat.com>
1936 * Update the address and phone number of the FSF organization in
1937 the GPL notices in the following files:
1938 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1939 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1940 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1941 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1942 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1943 tic54x.h, tic80.h, v850.h, vax.h
1945 2005-05-09 Jan Beulich <jbeulich@novell.com>
1947 * i386.h (i386_optab): Add ht and hnt.
1949 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1951 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1952 Add xcrypt-ctr. Provide aliases without hyphens.
1954 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1956 Moved from ../ChangeLog
1958 2005-04-12 Paul Brook <paul@codesourcery.com>
1959 * m88k.h: Rename psr macros to avoid conflicts.
1961 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1962 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1963 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1964 and ARM_ARCH_V6ZKT2.
1966 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1967 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1968 Remove redundant instruction types.
1969 (struct argument): X_op - new field.
1970 (struct cst4_entry): Remove.
1971 (no_op_insn): Declare.
1973 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1974 * crx.h (enum argtype): Rename types, remove unused types.
1976 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1977 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1978 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1979 (enum operand_type): Rearrange operands, edit comments.
1980 replace us<N> with ui<N> for unsigned immediate.
1981 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1982 displacements (respectively).
1983 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1984 (instruction type): Add NO_TYPE_INS.
1985 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1986 (operand_entry): New field - 'flags'.
1987 (operand flags): New.
1989 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1990 * crx.h (operand_type): Remove redundant types i3, i4,
1992 Add new unsigned immediate types us3, us4, us5, us16.
1994 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1996 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1997 adjust them accordingly.
1999 2005-04-01 Jan Beulich <jbeulich@novell.com>
2001 * i386.h (i386_optab): Add rdtscp.
2003 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2005 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2006 between memory and segment register. Allow movq for moving between
2007 general-purpose register and segment register.
2009 2005-02-09 Jan Beulich <jbeulich@novell.com>
2012 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2013 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2016 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2018 * m68k.h (m68008, m68ec030, m68882): Remove.
2020 (cpu_m68k, cpu_cf): New.
2021 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2022 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2024 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2026 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2027 * cgen.h (enum cgen_parse_operand_type): Add
2028 CGEN_PARSE_OPERAND_SYMBOLIC.
2030 2005-01-21 Fred Fish <fnf@specifixinc.com>
2032 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2033 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2034 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2036 2005-01-19 Fred Fish <fnf@specifixinc.com>
2038 * mips.h (struct mips_opcode): Add new pinfo2 member.
2039 (INSN_ALIAS): New define for opcode table entries that are
2040 specific instances of another entry, such as 'move' for an 'or'
2041 with a zero operand.
2042 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2043 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2045 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2047 * mips.h (CPU_RM9000): Define.
2048 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2050 2004-11-25 Jan Beulich <jbeulich@novell.com>
2052 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2053 to/from test registers are illegal in 64-bit mode. Add missing
2054 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2055 (previously one had to explicitly encode a rex64 prefix). Re-enable
2056 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2057 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2059 2004-11-23 Jan Beulich <jbeulich@novell.com>
2061 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2062 available only with SSE2. Change the MMX additions introduced by SSE
2063 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2064 instructions by their now designated identifier (since combining i686
2065 and 3DNow! does not really imply 3DNow!A).
2067 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2069 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2070 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2072 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2073 Vineet Sharma <vineets@noida.hcltech.com>
2075 * maxq.h: New file: Disassembly information for the maxq port.
2077 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2079 * i386.h (i386_optab): Put back "movzb".
2081 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2083 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2084 comments. Remove member cris_ver_sim. Add members
2085 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2086 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2087 (struct cris_support_reg, struct cris_cond15): New types.
2088 (cris_conds15): Declare.
2089 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2090 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2091 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2092 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2093 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2094 SIZE_FIELD_UNSIGNED.
2096 2004-11-04 Jan Beulich <jbeulich@novell.com>
2098 * i386.h (sldx_Suf): Remove.
2099 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2100 (q_FP): Define, implying no REX64.
2101 (x_FP, sl_FP): Imply FloatMF.
2102 (i386_optab): Split reg and mem forms of moving from segment registers
2103 so that the memory forms can ignore the 16-/32-bit operand size
2104 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2105 all non-floating-point instructions. Unite 32- and 64-bit forms of
2106 movsx, movzx, and movd. Adjust floating point operations for the above
2107 changes to the *FP macros. Add DefaultSize to floating point control
2108 insns operating on larger memory ranges. Remove left over comments
2109 hinting at certain insns being Intel-syntax ones where the ones
2110 actually meant are already gone.
2112 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2114 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2117 2004-09-30 Paul Brook <paul@codesourcery.com>
2119 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2120 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2122 2004-09-11 Theodore A. Roth <troth@openavr.org>
2124 * avr.h: Add support for
2125 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2127 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2129 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2131 2004-08-24 Dmitry Diky <diwil@spec.ru>
2133 * msp430.h (msp430_opc): Add new instructions.
2134 (msp430_rcodes): Declare new instructions.
2135 (msp430_hcodes): Likewise..
2137 2004-08-13 Nick Clifton <nickc@redhat.com>
2140 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2143 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2145 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2147 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2149 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2151 2004-07-21 Jan Beulich <jbeulich@novell.com>
2153 * i386.h: Adjust instruction descriptions to better match the
2156 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2158 * arm.h: Remove all old content. Replace with architecture defines
2159 from gas/config/tc-arm.c.
2161 2004-07-09 Andreas Schwab <schwab@suse.de>
2163 * m68k.h: Fix comment.
2165 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2169 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2171 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2173 2004-05-24 Peter Barada <peter@the-baradas.com>
2175 * m68k.h: Add 'size' to m68k_opcode.
2177 2004-05-05 Peter Barada <peter@the-baradas.com>
2179 * m68k.h: Switch from ColdFire chip name to core variant.
2181 2004-04-22 Peter Barada <peter@the-baradas.com>
2183 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2184 descriptions for new EMAC cases.
2185 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2186 handle Motorola MAC syntax.
2187 Allow disassembly of ColdFire V4e object files.
2189 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2191 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2193 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2195 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2197 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2199 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2201 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2203 * i386.h (i386_optab): Added xstore/xcrypt insns.
2205 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2207 * h8300.h (32bit ldc/stc): Add relaxing support.
2209 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2211 * h8300.h (BITOP): Pass MEMRELAX flag.
2213 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2215 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2218 For older changes see ChangeLog-9103
2220 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2222 Copying and distribution of this file, with or without modification,
2223 are permitted in any medium without royalty provided the copyright
2224 notice and this notice are preserved.
2230 version-control: never