include/opcode/ChangeLog

   1 2006-06-05  Thiemo Seufer  <ths@mips.com>
   2
   3         * mips.h: Improve description of MT flags.
   4
   5 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
   6
   7         * m68k.h (mcf_mask): Define.
   8
   9 2006-05-05  Thiemo Seufer  <ths@mips.com>
  10             David Ung  <davidu@mips.com>
  11
  12         * mips.h (enum): Add macro M_CACHE_AB.
  13
  14 2006-05-04  Thiemo Seufer  <ths@mips.com>
  15             Nigel Stephens  <nigel@mips.com>
  16             David Ung  <davidu@mips.com>
  17
  18         * mips.h: Add INSN_SMARTMIPS define.
  19
  20 2006-04-30  Thiemo Seufer  <ths@mips.com>
  21             David Ung  <davidu@mips.com>
  22
  23         * mips.h: Defines udi bits and masks.  Add description of
  24         characters which may appear in the args field of udi
  25         instructions.
  26
  27 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  28
  29         * mips.h: Improve comments describing the bitfield instruction
  30         fields.
  31
  32 2006-04-26  Julian Brown  <julian@codesourcery.com>
  33
  34         * arm.h (FPU_VFP_EXT_V3): Define constant.
  35         (FPU_NEON_EXT_V1): Likewise.
  36         (FPU_VFP_HARD): Update.
  37         (FPU_VFP_V3): Define macro.
  38         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  39
  40 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
  41
  42         * avr.h (AVR_ISA_PWMx): New.
  43
  44 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
  45
  46         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
  47         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
  48         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  49         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
  50         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
  51
  52 2006-03-10  Paul Brook  <paul@codesourcery.com>
  53
  54         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  55
  56 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  57
  58         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
  59         first.  Correct mask of bb "B" opcode.
  60
  61 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  62
  63         * i386.h (i386_optab): Support Intel Merom New Instructions.
  64
  65 2006-02-24  Paul Brook  <paul@codesourcery.com>
  66
  67         * arm.h: Add V7 feature bits.
  68
  69 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  70
  71         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  72
  73 2006-01-31  Paul Brook  <paul@codesourcery.com>
  74         Richard Earnshaw <rearnsha@arm.com>
  75
  76         * arm.h: Use ARM_CPU_FEATURE.
  77         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
  78         (arm_feature_set): Change to a structure.
  79         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
  80         ARM_FEATURE): New macros.
  81
  82 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
  83
  84         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
  85         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
  86         (ADD_PC_INCR_OPCODE): Don't define.
  87
  88 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
  89
  90         PR gas/1874
  91         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
  92
  93 2005-11-14  David Ung  <davidu@mips.com>
  94
  95         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
  96         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  97         save/restore encoding of the args field.
  98
  99 2005-10-28  Dave Brolley  <brolley@redhat.com>
 100
 101         Contribute the following changes:
 102         2005-02-16  Dave Brolley  <brolley@redhat.com>
 103
 104         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 105         cgen_isa_mask_* to cgen_bitset_*.
 106         * cgen.h: Likewise.
 107
 108         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 109
 110         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 111         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 112         (CGEN_CPU_TABLE): Make isas a ponter.
 113
 114         2003-09-29  Dave Brolley  <brolley@redhat.com>
 115
 116         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 117         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 118         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 119
 120         2002-12-13  Dave Brolley  <brolley@redhat.com>
 121
 122         * cgen.h (symcat.h): #include it.
 123         (cgen-bitset.h): #include it.
 124         (CGEN_ATTR_VALUE_TYPE): Now a union.
 125         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 126         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 127         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 128         * cgen-bitset.h: New file.
 129
 130 2005-09-30  Catherine Moore  <clm@cm00re.com>
 131
 132         * bfin.h: New file.
 133
 134 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 135
 136         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 137         indirect operands.
 138
 139 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 140
 141         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 142         Add FLAG_STRICT to pa10 ftest opcode.
 143
 144 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 145
 146         * hppa.h (pa_opcodes): Remove lha entries.
 147
 148 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 149
 150         * hppa.h (FLAG_STRICT): Revise comment.
 151         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 152         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 153         entries for "fdc".
 154
 155 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 156
 157         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 158
 159 2005-09-06  Chao-ying Fu  <fu@mips.com>
 160
 161         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 162         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 163         define.
 164         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 165         (INSN_ASE_MASK): Update to include INSN_MT.
 166         (INSN_MT): New define for MT ASE.
 167
 168 2005-08-25  Chao-ying Fu  <fu@mips.com>
 169
 170         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 171         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 172         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 173         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 174         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 175         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 176         instructions.
 177         (INSN_DSP): New define for DSP ASE.
 178
 179 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 180
 181         * a29k.h: Delete.
 182
 183 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 184
 185         * ppc.h (PPC_OPCODE_E300): Define.
 186
 187 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 188
 189         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 190
 191 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 192
 193         PR gas/336
 194         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 195         and pitlb.
 196
 197 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 198
 199         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 200         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 201         Add movq-s as 64-bit variants of movd-s.
 202
 203 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 204
 205         * hppa.h: Fix punctuation in comment.
 206
 207         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 208         implicit space-register addressing.  Set space-register bits on opcodes
 209         using implicit space-register addressing.  Add various missing pa20
 210         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 211         space-register addressing.  Use "fE" instead of "fe" in various
 212         fstw opcodes.
 213
 214 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 215
 216         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 217
 218 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 219
 220         * i386.h (i386_optab): Support Intel VMX Instructions.
 221
 222 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 223
 224         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 225
 226 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 227
 228         * i386.h (i386_optab): Add new insns.
 229
 230 2005-07-01  Nick Clifton  <nickc@redhat.com>
 231
 232         * sparc.h: Add typedefs to structure declarations.
 233
 234 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         PR 1013
 237         * i386.h (i386_optab): Update comments for 64bit addressing on
 238         mov. Allow 64bit addressing for mov and movq.
 239
 240 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 241
 242         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 243         respectively, in various floating-point load and store patterns.
 244
 245 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 246
 247         * hppa.h (FLAG_STRICT): Correct comment.
 248         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 249         PA 2.0 mneumonics when equivalent.  Entries with cache control
 250         completers now require PA 1.1.  Adjust whitespace.
 251
 252 2005-05-19  Anton Blanchard  <anton@samba.org>
 253
 254         * ppc.h (PPC_OPCODE_POWER5): Define.
 255
 256 2005-05-10  Nick Clifton  <nickc@redhat.com>
 257
 258         * Update the address and phone number of the FSF organization in
 259         the GPL notices in the following files:
 260         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 261         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 262         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 263         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 264         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 265         tic54x.h, tic80.h, v850.h, vax.h
 266
 267 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 268
 269         * i386.h (i386_optab): Add ht and hnt.
 270
 271 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 272
 273         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 274         Add xcrypt-ctr.  Provide aliases without hyphens.
 275
 276 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         Moved from ../ChangeLog
 279
 280         2005-04-12  Paul Brook  <paul@codesourcery.com>
 281         * m88k.h: Rename psr macros to avoid conflicts.
 282
 283         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 284         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 285         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 286         and ARM_ARCH_V6ZKT2.
 287
 288         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 289         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 290         Remove redundant instruction types.
 291         (struct argument): X_op - new field.
 292         (struct cst4_entry): Remove.
 293         (no_op_insn): Declare.
 294
 295         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 296         * crx.h (enum argtype): Rename types, remove unused types.
 297
 298         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 299         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 300         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 301         (enum operand_type): Rearrange operands, edit comments.
 302         replace us<N> with ui<N> for unsigned immediate.
 303         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 304         displacements (respectively).
 305         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 306         (instruction type): Add NO_TYPE_INS.
 307         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 308         (operand_entry): New field - 'flags'.
 309         (operand flags): New.
 310
 311         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 312         * crx.h (operand_type): Remove redundant types i3, i4,
 313         i5, i8, i12.
 314         Add new unsigned immediate types us3, us4, us5, us16.
 315
 316 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 317
 318         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 319         adjust them accordingly.
 320
 321 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 322
 323         * i386.h (i386_optab): Add rdtscp.
 324
 325 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 326
 327         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 328         between memory and segment register. Allow movq for moving between
 329         general-purpose register and segment register.
 330
 331 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 332
 333         PR gas/707
 334         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 335         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 336         fnstsw.
 337
 338 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 339
 340         * m68k.h (m68008, m68ec030, m68882): Remove.
 341         (m68k_mask): New.
 342         (cpu_m68k, cpu_cf): New.
 343         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 344         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 345
 346 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 347
 348         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 349         * cgen.h (enum cgen_parse_operand_type): Add
 350         CGEN_PARSE_OPERAND_SYMBOLIC.
 351
 352 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 353
 354         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 355         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 356         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 357
 358 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 359
 360         * mips.h (struct mips_opcode): Add new pinfo2 member.
 361         (INSN_ALIAS): New define for opcode table entries that are
 362         specific instances of another entry, such as 'move' for an 'or'
 363         with a zero operand.
 364         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 365         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 366
 367 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 368
 369         * mips.h (CPU_RM9000): Define.
 370         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 371
 372 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 373
 374         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 375         to/from test registers are illegal in 64-bit mode. Add missing
 376         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 377         (previously one had to explicitly encode a rex64 prefix). Re-enable
 378         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 379         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 380
 381 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 382
 383         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 384         available only with SSE2. Change the MMX additions introduced by SSE
 385         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 386         instructions by their now designated identifier (since combining i686
 387         and 3DNow! does not really imply 3DNow!A).
 388
 389 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 390
 391         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 392         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 393
 394 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 395             Vineet Sharma      <vineets@noida.hcltech.com>
 396
 397         * maxq.h: New file: Disassembly information for the maxq port.
 398
 399 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 400
 401         * i386.h (i386_optab): Put back "movzb".
 402
 403 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 404
 405         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 406         comments.  Remove member cris_ver_sim.  Add members
 407         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 408         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 409         (struct cris_support_reg, struct cris_cond15): New types.
 410         (cris_conds15): Declare.
 411         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 412         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 413         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 414         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 415         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 416         SIZE_FIELD_UNSIGNED.
 417
 418 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 419
 420         * i386.h (sldx_Suf): Remove.
 421         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 422         (q_FP): Define, implying no REX64.
 423         (x_FP, sl_FP): Imply FloatMF.
 424         (i386_optab): Split reg and mem forms of moving from segment registers
 425         so that the memory forms can ignore the 16-/32-bit operand size
 426         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 427         all non-floating-point instructions. Unite 32- and 64-bit forms of
 428         movsx, movzx, and movd. Adjust floating point operations for the above
 429         changes to the *FP macros. Add DefaultSize to floating point control
 430         insns operating on larger memory ranges. Remove left over comments
 431         hinting at certain insns being Intel-syntax ones where the ones
 432         actually meant are already gone.
 433
 434 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 435
 436         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 437         instruction type.
 438
 439 2004-09-30  Paul Brook  <paul@codesourcery.com>
 440
 441         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 442         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 443
 444 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 445
 446         * avr.h: Add support for
 447         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 448
 449 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 450
 451         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 452
 453 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 454
 455         * msp430.h (msp430_opc): Add new instructions.
 456         (msp430_rcodes): Declare new instructions.
 457         (msp430_hcodes): Likewise..
 458
 459 2004-08-13  Nick Clifton  <nickc@redhat.com>
 460
 461         PR/301
 462         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 463         processors.
 464
 465 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 466
 467         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 468
 469 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 470
 471         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 472
 473 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 474
 475         * i386.h: Adjust instruction descriptions to better match the
 476         specification.
 477
 478 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 479
 480         * arm.h: Remove all old content.  Replace with architecture defines
 481         from gas/config/tc-arm.c.
 482
 483 2004-07-09  Andreas Schwab  <schwab@suse.de>
 484
 485         * m68k.h: Fix comment.
 486
 487 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 488
 489         * crx.h: New file.
 490
 491 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 492
 493         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 494
 495 2004-05-24  Peter Barada  <peter@the-baradas.com>
 496
 497         * m68k.h: Add 'size' to m68k_opcode.
 498
 499 2004-05-05  Peter Barada  <peter@the-baradas.com>
 500
 501         * m68k.h: Switch from ColdFire chip name to core variant.
 502
 503 2004-04-22  Peter Barada  <peter@the-baradas.com>
 504
 505         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 506         descriptions for new EMAC cases.
 507         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 508         handle Motorola MAC syntax.
 509         Allow disassembly of ColdFire V4e object files.
 510
 511 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 512
 513         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 514
 515 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 516
 517         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 518
 519 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 520
 521         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 522
 523 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 524
 525         * i386.h (i386_optab): Added xstore/xcrypt insns.
 526
 527 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 528
 529         * h8300.h (32bit ldc/stc): Add relaxing support.
 530
 531 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 532
 533         * h8300.h (BITOP): Pass MEMRELAX flag.
 534
 535 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 536
 537         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 538         except for the H8S.
 539
 540 For older changes see ChangeLog-9103
 541 \f
 542 Local Variables:
 543 mode: change-log
 544 left-margin: 8
 545 fill-column: 74
 546 version-control: never
 547 End: