include/opcode/ChangeLog

   1 2006-04-07  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
   2
   3         * avr.h (AVR_ISA_PWMx): New.
   4
   5 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
   6
   7         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
   8         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
   9         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  10         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
  11         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
  12
  13 2006-03-10  Paul Brook  <paul@codesourcery.com>
  14
  15         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  16
  17 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  18
  19         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
  20         first.  Correct mask of bb "B" opcode.
  21
  22 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  23
  24         * i386.h (i386_optab): Support Intel Merom New Instructions.
  25
  26 2006-02-24  Paul Brook  <paul@codesourcery.com>
  27
  28         * arm.h: Add V7 feature bits.
  29
  30 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  33
  34 2006-01-31  Paul Brook  <paul@codesourcery.com>
  35         Richard Earnshaw <rearnsha@arm.com>
  36
  37         * arm.h: Use ARM_CPU_FEATURE.
  38         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
  39         (arm_feature_set): Change to a structure.
  40         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
  41         ARM_FEATURE): New macros.
  42
  43 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
  44
  45         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
  46         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
  47         (ADD_PC_INCR_OPCODE): Don't define.
  48
  49 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         PR gas/1874
  52         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
  53
  54 2005-11-14  David Ung  <davidu@mips.com>
  55
  56         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
  57         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  58         save/restore encoding of the args field.
  59
  60 2005-10-28  Dave Brolley  <brolley@redhat.com>
  61
  62         Contribute the following changes:
  63         2005-02-16  Dave Brolley  <brolley@redhat.com>
  64
  65         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
  66         cgen_isa_mask_* to cgen_bitset_*.
  67         * cgen.h: Likewise.
  68
  69         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  70
  71         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  72         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  73         (CGEN_CPU_TABLE): Make isas a ponter.
  74
  75         2003-09-29  Dave Brolley  <brolley@redhat.com>
  76
  77         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  78         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  79         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  80
  81         2002-12-13  Dave Brolley  <brolley@redhat.com>
  82
  83         * cgen.h (symcat.h): #include it.
  84         (cgen-bitset.h): #include it.
  85         (CGEN_ATTR_VALUE_TYPE): Now a union.
  86         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  87         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  88         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  89         * cgen-bitset.h: New file.
  90
  91 2005-09-30  Catherine Moore  <clm@cm00re.com>
  92
  93         * bfin.h: New file.
  94
  95 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  96
  97         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  98         indirect operands.
  99
 100 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 101
 102         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 103         Add FLAG_STRICT to pa10 ftest opcode.
 104
 105 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 106
 107         * hppa.h (pa_opcodes): Remove lha entries.
 108
 109 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 110
 111         * hppa.h (FLAG_STRICT): Revise comment.
 112         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 113         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 114         entries for "fdc".
 115
 116 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 117
 118         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 119
 120 2005-09-06  Chao-ying Fu  <fu@mips.com>
 121
 122         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 123         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 124         define.
 125         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 126         (INSN_ASE_MASK): Update to include INSN_MT.
 127         (INSN_MT): New define for MT ASE.
 128
 129 2005-08-25  Chao-ying Fu  <fu@mips.com>
 130
 131         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 132         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 133         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 134         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 135         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 136         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 137         instructions.
 138         (INSN_DSP): New define for DSP ASE.
 139
 140 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 141
 142         * a29k.h: Delete.
 143
 144 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 145
 146         * ppc.h (PPC_OPCODE_E300): Define.
 147
 148 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 149
 150         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 151
 152 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 153
 154         PR gas/336
 155         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 156         and pitlb.
 157
 158 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 159
 160         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 161         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 162         Add movq-s as 64-bit variants of movd-s.
 163
 164 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 165
 166         * hppa.h: Fix punctuation in comment.
 167
 168         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 169         implicit space-register addressing.  Set space-register bits on opcodes
 170         using implicit space-register addressing.  Add various missing pa20
 171         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 172         space-register addressing.  Use "fE" instead of "fe" in various
 173         fstw opcodes.
 174
 175 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 176
 177         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 178
 179 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 180
 181         * i386.h (i386_optab): Support Intel VMX Instructions.
 182
 183 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 184
 185         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 186
 187 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 188
 189         * i386.h (i386_optab): Add new insns.
 190
 191 2005-07-01  Nick Clifton  <nickc@redhat.com>
 192
 193         * sparc.h: Add typedefs to structure declarations.
 194
 195 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         PR 1013
 198         * i386.h (i386_optab): Update comments for 64bit addressing on
 199         mov. Allow 64bit addressing for mov and movq.
 200
 201 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 202
 203         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 204         respectively, in various floating-point load and store patterns.
 205
 206 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 207
 208         * hppa.h (FLAG_STRICT): Correct comment.
 209         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 210         PA 2.0 mneumonics when equivalent.  Entries with cache control
 211         completers now require PA 1.1.  Adjust whitespace.
 212
 213 2005-05-19  Anton Blanchard  <anton@samba.org>
 214
 215         * ppc.h (PPC_OPCODE_POWER5): Define.
 216
 217 2005-05-10  Nick Clifton  <nickc@redhat.com>
 218
 219         * Update the address and phone number of the FSF organization in
 220         the GPL notices in the following files:
 221         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 222         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 223         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 224         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 225         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 226         tic54x.h, tic80.h, v850.h, vax.h
 227
 228 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 229
 230         * i386.h (i386_optab): Add ht and hnt.
 231
 232 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 233
 234         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 235         Add xcrypt-ctr.  Provide aliases without hyphens.
 236
 237 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 238
 239         Moved from ../ChangeLog
 240
 241         2005-04-12  Paul Brook  <paul@codesourcery.com>
 242         * m88k.h: Rename psr macros to avoid conflicts.
 243
 244         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 245         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 246         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 247         and ARM_ARCH_V6ZKT2.
 248
 249         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 250         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 251         Remove redundant instruction types.
 252         (struct argument): X_op - new field.
 253         (struct cst4_entry): Remove.
 254         (no_op_insn): Declare.
 255
 256         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 257         * crx.h (enum argtype): Rename types, remove unused types.
 258
 259         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 260         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 261         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 262         (enum operand_type): Rearrange operands, edit comments.
 263         replace us<N> with ui<N> for unsigned immediate.
 264         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 265         displacements (respectively).
 266         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 267         (instruction type): Add NO_TYPE_INS.
 268         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 269         (operand_entry): New field - 'flags'.
 270         (operand flags): New.
 271
 272         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 273         * crx.h (operand_type): Remove redundant types i3, i4,
 274         i5, i8, i12.
 275         Add new unsigned immediate types us3, us4, us5, us16.
 276
 277 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 278
 279         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 280         adjust them accordingly.
 281
 282 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 283
 284         * i386.h (i386_optab): Add rdtscp.
 285
 286 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 287
 288         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 289         between memory and segment register. Allow movq for moving between
 290         general-purpose register and segment register.
 291
 292 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 293
 294         PR gas/707
 295         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 296         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 297         fnstsw.
 298
 299 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 300
 301         * m68k.h (m68008, m68ec030, m68882): Remove.
 302         (m68k_mask): New.
 303         (cpu_m68k, cpu_cf): New.
 304         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 305         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 306
 307 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 308
 309         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 310         * cgen.h (enum cgen_parse_operand_type): Add
 311         CGEN_PARSE_OPERAND_SYMBOLIC.
 312
 313 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 314
 315         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 316         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 317         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 318
 319 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 320
 321         * mips.h (struct mips_opcode): Add new pinfo2 member.
 322         (INSN_ALIAS): New define for opcode table entries that are
 323         specific instances of another entry, such as 'move' for an 'or'
 324         with a zero operand.
 325         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 326         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 327
 328 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 329
 330         * mips.h (CPU_RM9000): Define.
 331         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 332
 333 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 334
 335         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 336         to/from test registers are illegal in 64-bit mode. Add missing
 337         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 338         (previously one had to explicitly encode a rex64 prefix). Re-enable
 339         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 340         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 341
 342 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 343
 344         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 345         available only with SSE2. Change the MMX additions introduced by SSE
 346         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 347         instructions by their now designated identifier (since combining i686
 348         and 3DNow! does not really imply 3DNow!A).
 349
 350 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 351
 352         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 353         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 354
 355 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 356             Vineet Sharma      <vineets@noida.hcltech.com>
 357
 358         * maxq.h: New file: Disassembly information for the maxq port.
 359
 360 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 361
 362         * i386.h (i386_optab): Put back "movzb".
 363
 364 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 365
 366         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 367         comments.  Remove member cris_ver_sim.  Add members
 368         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 369         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 370         (struct cris_support_reg, struct cris_cond15): New types.
 371         (cris_conds15): Declare.
 372         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 373         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 374         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 375         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 376         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 377         SIZE_FIELD_UNSIGNED.
 378
 379 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 380
 381         * i386.h (sldx_Suf): Remove.
 382         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 383         (q_FP): Define, implying no REX64.
 384         (x_FP, sl_FP): Imply FloatMF.
 385         (i386_optab): Split reg and mem forms of moving from segment registers
 386         so that the memory forms can ignore the 16-/32-bit operand size
 387         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 388         all non-floating-point instructions. Unite 32- and 64-bit forms of
 389         movsx, movzx, and movd. Adjust floating point operations for the above
 390         changes to the *FP macros. Add DefaultSize to floating point control
 391         insns operating on larger memory ranges. Remove left over comments
 392         hinting at certain insns being Intel-syntax ones where the ones
 393         actually meant are already gone.
 394
 395 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 396
 397         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 398         instruction type.
 399
 400 2004-09-30  Paul Brook  <paul@codesourcery.com>
 401
 402         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 403         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 404
 405 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 406
 407         * avr.h: Add support for
 408         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 409
 410 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 411
 412         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 413
 414 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 415
 416         * msp430.h (msp430_opc): Add new instructions.
 417         (msp430_rcodes): Declare new instructions.
 418         (msp430_hcodes): Likewise..
 419
 420 2004-08-13  Nick Clifton  <nickc@redhat.com>
 421
 422         PR/301
 423         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 424         processors.
 425
 426 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 427
 428         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 429
 430 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 431
 432         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 433
 434 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 435
 436         * i386.h: Adjust instruction descriptions to better match the
 437         specification.
 438
 439 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 440
 441         * arm.h: Remove all old content.  Replace with architecture defines
 442         from gas/config/tc-arm.c.
 443
 444 2004-07-09  Andreas Schwab  <schwab@suse.de>
 445
 446         * m68k.h: Fix comment.
 447
 448 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 449
 450         * crx.h: New file.
 451
 452 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 453
 454         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 455
 456 2004-05-24  Peter Barada  <peter@the-baradas.com>
 457
 458         * m68k.h: Add 'size' to m68k_opcode.
 459
 460 2004-05-05  Peter Barada  <peter@the-baradas.com>
 461
 462         * m68k.h: Switch from ColdFire chip name to core variant.
 463
 464 2004-04-22  Peter Barada  <peter@the-baradas.com>
 465
 466         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 467         descriptions for new EMAC cases.
 468         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 469         handle Motorola MAC syntax.
 470         Allow disassembly of ColdFire V4e object files.
 471
 472 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 473
 474         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 475
 476 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 477
 478         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 479
 480 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 481
 482         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 483
 484 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 485
 486         * i386.h (i386_optab): Added xstore/xcrypt insns.
 487
 488 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 489
 490         * h8300.h (32bit ldc/stc): Add relaxing support.
 491
 492 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 493
 494         * h8300.h (BITOP): Pass MEMRELAX flag.
 495
 496 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 497
 498         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 499         except for the H8S.
 500
 501 For older changes see ChangeLog-9103
 502 \f
 503 Local Variables:
 504 mode: change-log
 505 left-margin: 8
 506 fill-column: 74
 507 version-control: never
 508 End: