include/opcode/ChangeLog

   1 2005-05-09  Jan Beulich  <jbeulich@novell.com>
   2
   3         * i386.h (i386_optab): Add ht and hnt.
   4
   5 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
   6
   7         * i386.h: Insert hyphens into selected VIA PadLock extensions.
   8         Add xcrypt-ctr.  Provide aliases without hyphens.
   9
  10 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         Moved from ../ChangeLog
  13
  14         2005-04-12  Paul Brook  <paul@codesourcery.com>
  15         * m88k.h: Rename psr macros to avoid conflicts.
  16
  17         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  18         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  19         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  20         and ARM_ARCH_V6ZKT2.
  21
  22         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  23         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  24         Remove redundant instruction types.
  25         (struct argument): X_op - new field.
  26         (struct cst4_entry): Remove.
  27         (no_op_insn): Declare.
  28
  29         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  30         * crx.h (enum argtype): Rename types, remove unused types.
  31
  32         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  33         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  34         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  35         (enum operand_type): Rearrange operands, edit comments.
  36         replace us<N> with ui<N> for unsigned immediate.
  37         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
  38         displacements (respectively).
  39         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
  40         (instruction type): Add NO_TYPE_INS.
  41         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
  42         (operand_entry): New field - 'flags'.
  43         (operand flags): New.
  44
  45         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  46         * crx.h (operand_type): Remove redundant types i3, i4,
  47         i5, i8, i12.
  48         Add new unsigned immediate types us3, us4, us5, us16.
  49
  50 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
  51
  52         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
  53         adjust them accordingly.
  54
  55 2005-04-01  Jan Beulich  <jbeulich@novell.com>
  56
  57         * i386.h (i386_optab): Add rdtscp.
  58
  59 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
  60
  61         * i386.h (i386_optab): Don't allow the `l' suffix for moving
  62         between memory and segment register. Allow movq for moving between
  63         general-purpose register and segment register.
  64
  65 2005-02-09  Jan Beulich  <jbeulich@novell.com>
  66
  67         PR gas/707
  68         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
  69         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
  70         fnstsw.
  71
  72 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  73
  74         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  75         * cgen.h (enum cgen_parse_operand_type): Add
  76         CGEN_PARSE_OPERAND_SYMBOLIC.
  77
  78 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  79
  80         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  81         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  82         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  83
  84 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  85
  86         * mips.h (struct mips_opcode): Add new pinfo2 member.
  87         (INSN_ALIAS): New define for opcode table entries that are
  88         specific instances of another entry, such as 'move' for an 'or'
  89         with a zero operand.
  90         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
  91         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
  92
  93 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
  94
  95         * mips.h (CPU_RM9000): Define.
  96         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
  97
  98 2004-11-25 Jan Beulich  <jbeulich@novell.com>
  99
 100         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 101         to/from test registers are illegal in 64-bit mode. Add missing
 102         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 103         (previously one had to explicitly encode a rex64 prefix). Re-enable
 104         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 105         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 106
 107 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 108
 109         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 110         available only with SSE2. Change the MMX additions introduced by SSE
 111         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 112         instructions by their now designated identifier (since combining i686
 113         and 3DNow! does not really imply 3DNow!A).
 114
 115 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 116
 117         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 118         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 119
 120 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 121             Vineet Sharma      <vineets@noida.hcltech.com>
 122
 123         * maxq.h: New file: Disassembly information for the maxq port.
 124
 125 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 126
 127         * i386.h (i386_optab): Put back "movzb".
 128
 129 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 130
 131         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 132         comments.  Remove member cris_ver_sim.  Add members
 133         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 134         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 135         (struct cris_support_reg, struct cris_cond15): New types.
 136         (cris_conds15): Declare.
 137         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 138         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 139         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 140         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 141         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 142         SIZE_FIELD_UNSIGNED.
 143
 144 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 145
 146         * i386.h (sldx_Suf): Remove.
 147         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 148         (q_FP): Define, implying no REX64.
 149         (x_FP, sl_FP): Imply FloatMF.
 150         (i386_optab): Split reg and mem forms of moving from segment registers
 151         so that the memory forms can ignore the 16-/32-bit operand size
 152         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 153         all non-floating-point instructions. Unite 32- and 64-bit forms of
 154         movsx, movzx, and movd. Adjust floating point operations for the above
 155         changes to the *FP macros. Add DefaultSize to floating point control
 156         insns operating on larger memory ranges. Remove left over comments
 157         hinting at certain insns being Intel-syntax ones where the ones
 158         actually meant are already gone.
 159
 160 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 161
 162         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 163         instruction type.
 164
 165 2004-09-30  Paul Brook  <paul@codesourcery.com>
 166
 167         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 168         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 169
 170 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 171
 172         * avr.h: Add support for
 173         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 174
 175 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 176
 177         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 178
 179 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 180
 181         * msp430.h (msp430_opc): Add new instructions.
 182         (msp430_rcodes): Declare new instructions.
 183         (msp430_hcodes): Likewise..
 184
 185 2004-08-13  Nick Clifton  <nickc@redhat.com>
 186
 187         PR/301
 188         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 189         processors.
 190
 191 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 192
 193         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 194
 195 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 198
 199 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 200
 201         * i386.h: Adjust instruction descriptions to better match the
 202         specification.
 203
 204 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 205
 206         * arm.h: Remove all old content.  Replace with architecture defines
 207         from gas/config/tc-arm.c.
 208
 209 2004-07-09  Andreas Schwab  <schwab@suse.de>
 210
 211         * m68k.h: Fix comment.
 212
 213 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 214
 215         * crx.h: New file.
 216
 217 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 218
 219         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 220
 221 2004-05-24  Peter Barada  <peter@the-baradas.com>
 222
 223         * m68k.h: Add 'size' to m68k_opcode.
 224
 225 2004-05-05  Peter Barada  <peter@the-baradas.com>
 226
 227         * m68k.h: Switch from ColdFire chip name to core variant.
 228
 229 2004-04-22  Peter Barada  <peter@the-baradas.com>
 230
 231         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 232         descriptions for new EMAC cases.
 233         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 234         handle Motorola MAC syntax.
 235         Allow disassembly of ColdFire V4e object files.
 236
 237 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 238
 239         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 240
 241 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 242
 243         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 244
 245 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 246
 247         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 248
 249 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 250
 251         * i386.h (i386_optab): Added xstore/xcrypt insns.
 252
 253 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 254
 255         * h8300.h (32bit ldc/stc): Add relaxing support.
 256
 257 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 258
 259         * h8300.h (BITOP): Pass MEMRELAX flag.
 260
 261 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 262
 263         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 264         except for the H8S.
 265
 266 For older changes see ChangeLog-9103
 267 \f
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