include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66 #define AARCH64_FEATURE_V8_6    0x00000002      /* ARMv8.6 processors.  */
  67
  68 /* Flag Manipulation insns.  */
  69 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  70 /* FRINT[32,64][Z,X] insns.  */
  71 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  72 /* SB instruction.  */
  73 #define AARCH64_FEATURE_SB              0x10000000000ULL
  74 /* Execution and Data Prediction Restriction instructions.  */
  75 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  76 /* DC CVADP.  */
  77 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  78 /* Random Number instructions.  */
  79 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  80 /* BTI instructions.  */
  81 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  82 /* SCXTNUM_ELx.  */
  83 #define AARCH64_FEATURE_SCXTNUM         0x200000000000ULL
  84 /* ID_PFR2 instructions.  */
  85 #define AARCH64_FEATURE_ID_PFR2         0x400000000000ULL
  86 /* SSBS mechanism enabled.  */
  87 #define AARCH64_FEATURE_SSBS            0x800000000000ULL
  88 /* Memory Tagging Extension.  */
  89 #define AARCH64_FEATURE_MEMTAG          0x1000000000000ULL
  90 /* Transactional Memory Extension.  */
  91 #define AARCH64_FEATURE_TME             0x2000000000000ULL
  92
  93 /* SVE2 instructions.  */
  94 #define AARCH64_FEATURE_SVE2            0x000000010
  95 #define AARCH64_FEATURE_SVE2_AES                0x000000080
  96 #define AARCH64_FEATURE_SVE2_BITPERM    0x000000100
  97 #define AARCH64_FEATURE_SVE2_SM4                0x000000200
  98 #define AARCH64_FEATURE_SVE2_SHA3       0x000000400
  99
 100 /* Architectures are the sum of the base and extensions.  */
 101 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
 102                                                  AARCH64_FEATURE_FP  \
 103                                                  | AARCH64_FEATURE_SIMD)
 104 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 105                                                  AARCH64_FEATURE_CRC    \
 106                                                  | AARCH64_FEATURE_V8_1 \
 107                                                  | AARCH64_FEATURE_LSE  \
 108                                                  | AARCH64_FEATURE_PAN  \
 109                                                  | AARCH64_FEATURE_LOR  \
 110                                                  | AARCH64_FEATURE_RDMA)
 111 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 112                                                  AARCH64_FEATURE_V8_2   \
 113                                                  | AARCH64_FEATURE_RAS)
 114 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 115                                                  AARCH64_FEATURE_V8_3   \
 116                                                  | AARCH64_FEATURE_RCPC \
 117                                                  | AARCH64_FEATURE_COMPNUM)
 118 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 119                                                  AARCH64_FEATURE_V8_4   \
 120                                                  | AARCH64_FEATURE_DOTPROD \
 121                                                  | AARCH64_FEATURE_F16_FML)
 122 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 123                                                  AARCH64_FEATURE_V8_5   \
 124                                                  | AARCH64_FEATURE_FLAGMANIP \
 125                                                  | AARCH64_FEATURE_FRINTTS \
 126                                                  | AARCH64_FEATURE_SB   \
 127                                                  | AARCH64_FEATURE_PREDRES \
 128                                                  | AARCH64_FEATURE_CVADP \
 129                                                  | AARCH64_FEATURE_BTI  \
 130                                                  | AARCH64_FEATURE_SCXTNUM \
 131                                                  | AARCH64_FEATURE_ID_PFR2 \
 132                                                  | AARCH64_FEATURE_SSBS)
 133 #define AARCH64_ARCH_V8_6       AARCH64_FEATURE (AARCH64_ARCH_V8_5,     \
 134                                                  AARCH64_FEATURE_V8_6)
 135
 136 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 137 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 138
 139 /* CPU-specific features.  */
 140 typedef unsigned long long aarch64_feature_set;
 141
 142 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 143   ((~(CPU) & (FEAT)) == 0)
 144
 145 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 146   (((CPU) & (FEAT)) != 0)
 147
 148 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 149   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 150
 151 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 152   do                                            \
 153     {                                           \
 154       (TARG) = (F1) | (F2);                     \
 155     }                                           \
 156   while (0)
 157
 158 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 159   do                                            \
 160     {                                           \
 161       (TARG) = (F1) &~ (F2);                    \
 162     }                                           \
 163   while (0)
 164
 165 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 166
 167 enum aarch64_operand_class
 168 {
 169   AARCH64_OPND_CLASS_NIL,
 170   AARCH64_OPND_CLASS_INT_REG,
 171   AARCH64_OPND_CLASS_MODIFIED_REG,
 172   AARCH64_OPND_CLASS_FP_REG,
 173   AARCH64_OPND_CLASS_SIMD_REG,
 174   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 175   AARCH64_OPND_CLASS_SISD_REG,
 176   AARCH64_OPND_CLASS_SIMD_REGLIST,
 177   AARCH64_OPND_CLASS_SVE_REG,
 178   AARCH64_OPND_CLASS_PRED_REG,
 179   AARCH64_OPND_CLASS_ADDRESS,
 180   AARCH64_OPND_CLASS_IMMEDIATE,
 181   AARCH64_OPND_CLASS_SYSTEM,
 182   AARCH64_OPND_CLASS_COND,
 183 };
 184
 185 /* Operand code that helps both parsing and coding.
 186    Keep AARCH64_OPERANDS synced.  */
 187
 188 enum aarch64_opnd
 189 {
 190   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 191
 192   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 193   AARCH64_OPND_Rn,      /* Integer register as source.  */
 194   AARCH64_OPND_Rm,      /* Integer register as source.  */
 195   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 196   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 197   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 198   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 199   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 200   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 201
 202   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 203   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 204   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 205   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 206   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 207   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 208
 209   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 210   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 211   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 212   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 213   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 214   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 215
 216   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 217   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 218   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 219
 220   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 221   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 222   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 223   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 224   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 225   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 226   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 227   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 228   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 229   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 230                            qualifier is S_H.  */
 231   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 232   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 233   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 234                            structure to all lanes.  */
 235   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 236
 237   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 238   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 239
 240   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 241   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 242   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 243   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 244   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 245   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 246   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 247   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 248                            (no encoding).  */
 249   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 250   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 251   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 252   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 253   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 254   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 255   AARCH64_OPND_IMM,     /* Immediate.  */
 256   AARCH64_OPND_IMM_2,   /* Immediate.  */
 257   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 258   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 259   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 260   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 261   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 262   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 263   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 264   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 265   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 266   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 267   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 268                            each condition flag.  */
 269
 270   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 271   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 272   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 273   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 274   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 275   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 276   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 277   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 278
 279   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 280   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 281
 282   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 283   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 284   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 285   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 286   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 287
 288   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 289   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 290   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 291   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 292   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 293                                    negative or unaligned and there is
 294                                    no writeback allowed.  This operand code
 295                                    is only used to support the programmer-
 296                                    friendly feature of using LDR/STR as the
 297                                    the mnemonic name for LDUR/STUR instructions
 298                                    wherever there is no ambiguity.  */
 299   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 300   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 301                                    16) immediate.  */
 302   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 303   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 304                                    16) immediate.  */
 305   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 306   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 307   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 308
 309   AARCH64_OPND_SYSREG,          /* System register operand.  */
 310   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 311   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 312   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 313   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 314   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 315   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 316   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 317   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 318   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 319   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 320   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 321
 322   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 323   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 324   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 325   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 326   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 327   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 328   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 329   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 330   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 331   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 332   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 333   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 334   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 335   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 336   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 337   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 338   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 339   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 340   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 341   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 342   AARCH64_OPND_SVE_ADDR_ZX,         /* SVE [Zn.<T>{, <Xm>}].  */
 343   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 344   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 345   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 346   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 347   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 348                                        Bit 14 controls S/U choice.  */
 349   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 350                                        Bit 22 controls S/U choice.  */
 351   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 352                                        Bit 14 controls S/U choice.  */
 353   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 354                                        Bit 22 controls S/U choice.  */
 355   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 356                                        Bit 14 controls S/U choice.  */
 357   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 358                                        Bit 22 controls S/U choice.  */
 359   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 360                                        Bit 14 controls S/U choice.  */
 361   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 362                                        Bit 22 controls S/U choice.  */
 363   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 364   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 365   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 366   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 367   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 368   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 369   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 370   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 371   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 372   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 373   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 374   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 375   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 376   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 377   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 378   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 379   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 380   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 381   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 382   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 383   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 384   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 385   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 386   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 387   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 388   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 389   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 390   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 391   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 392   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 393   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 394   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 395   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 396   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 397   AARCH64_OPND_SVE_SHLIMM_UNPRED_22,    /* SVE 3 bit shift left unpred.  */
 398   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 399   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 400   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,    /* SVE 3 bit shift right unpred.  */
 401   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 402   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 403   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 404   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 405   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 406   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 407   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 408   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 409   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 410   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 411   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 412   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 413   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 414   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 415   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 416   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 417   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 418   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 419   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 420   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
 421   AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
 422   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 423   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 424   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 425   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 426   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 427   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 428   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 429   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 430 };
 431
 432 /* Qualifier constrains an operand.  It either specifies a variant of an
 433    operand type or limits values available to an operand type.
 434
 435    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 436
 437 enum aarch64_opnd_qualifier
 438 {
 439   /* Indicating no further qualification on an operand.  */
 440   AARCH64_OPND_QLF_NIL,
 441
 442   /* Qualifying an operand which is a general purpose (integer) register;
 443      indicating the operand data size or a specific register.  */
 444   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 445   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 446   AARCH64_OPND_QLF_WSP, /* WSP.  */
 447   AARCH64_OPND_QLF_SP,  /* SP.  */
 448
 449   /* Qualifying an operand which is a floating-point register, a SIMD
 450      vector element or a SIMD vector element list; indicating operand data
 451      size or the size of each SIMD vector element in the case of a SIMD
 452      vector element list.
 453      These qualifiers are also used to qualify an address operand to
 454      indicate the size of data element a load/store instruction is
 455      accessing.
 456      They are also used for the immediate shift operand in e.g. SSHR.  Such
 457      a use is only for the ease of operand encoding/decoding and qualifier
 458      sequence matching; such a use should not be applied widely; use the value
 459      constraint qualifiers for immediate operands wherever possible.  */
 460   AARCH64_OPND_QLF_S_B,
 461   AARCH64_OPND_QLF_S_H,
 462   AARCH64_OPND_QLF_S_S,
 463   AARCH64_OPND_QLF_S_D,
 464   AARCH64_OPND_QLF_S_Q,
 465   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 466      are selected by the instruction.  Other than that it has no difference
 467      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 468      reasons and is an exception from normal AArch64 disassembly scheme.  */
 469   AARCH64_OPND_QLF_S_4B,
 470
 471   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 472      register list; indicating register shape.
 473      They are also used for the immediate shift operand in e.g. SSHR.  Such
 474      a use is only for the ease of operand encoding/decoding and qualifier
 475      sequence matching; such a use should not be applied widely; use the value
 476      constraint qualifiers for immediate operands wherever possible.  */
 477   AARCH64_OPND_QLF_V_4B,
 478   AARCH64_OPND_QLF_V_8B,
 479   AARCH64_OPND_QLF_V_16B,
 480   AARCH64_OPND_QLF_V_2H,
 481   AARCH64_OPND_QLF_V_4H,
 482   AARCH64_OPND_QLF_V_8H,
 483   AARCH64_OPND_QLF_V_2S,
 484   AARCH64_OPND_QLF_V_4S,
 485   AARCH64_OPND_QLF_V_1D,
 486   AARCH64_OPND_QLF_V_2D,
 487   AARCH64_OPND_QLF_V_1Q,
 488
 489   AARCH64_OPND_QLF_P_Z,
 490   AARCH64_OPND_QLF_P_M,
 491
 492   /* Used in scaled signed immediate that are scaled by a Tag granule
 493      like in stg, st2g, etc.   */
 494   AARCH64_OPND_QLF_imm_tag,
 495
 496   /* Constraint on value.  */
 497   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 498   AARCH64_OPND_QLF_imm_0_7,
 499   AARCH64_OPND_QLF_imm_0_15,
 500   AARCH64_OPND_QLF_imm_0_31,
 501   AARCH64_OPND_QLF_imm_0_63,
 502   AARCH64_OPND_QLF_imm_1_32,
 503   AARCH64_OPND_QLF_imm_1_64,
 504
 505   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 506      or shift-ones.  */
 507   AARCH64_OPND_QLF_LSL,
 508   AARCH64_OPND_QLF_MSL,
 509
 510   /* Special qualifier helping retrieve qualifier information during the
 511      decoding time (currently not in use).  */
 512   AARCH64_OPND_QLF_RETRIEVE,
 513 };
 514 \f
 515 /* Instruction class.  */
 516
 517 enum aarch64_insn_class
 518 {
 519   addsub_carry,
 520   addsub_ext,
 521   addsub_imm,
 522   addsub_shift,
 523   asimdall,
 524   asimddiff,
 525   asimdelem,
 526   asimdext,
 527   asimdimm,
 528   asimdins,
 529   asimdmisc,
 530   asimdperm,
 531   asimdsame,
 532   asimdshf,
 533   asimdtbl,
 534   asisddiff,
 535   asisdelem,
 536   asisdlse,
 537   asisdlsep,
 538   asisdlso,
 539   asisdlsop,
 540   asisdmisc,
 541   asisdone,
 542   asisdpair,
 543   asisdsame,
 544   asisdshf,
 545   bitfield,
 546   branch_imm,
 547   branch_reg,
 548   compbranch,
 549   condbranch,
 550   condcmp_imm,
 551   condcmp_reg,
 552   condsel,
 553   cryptoaes,
 554   cryptosha2,
 555   cryptosha3,
 556   dp_1src,
 557   dp_2src,
 558   dp_3src,
 559   exception,
 560   extract,
 561   float2fix,
 562   float2int,
 563   floatccmp,
 564   floatcmp,
 565   floatdp1,
 566   floatdp2,
 567   floatdp3,
 568   floatimm,
 569   floatsel,
 570   ldst_immpost,
 571   ldst_immpre,
 572   ldst_imm9,    /* immpost or immpre */
 573   ldst_imm10,   /* LDRAA/LDRAB */
 574   ldst_pos,
 575   ldst_regoff,
 576   ldst_unpriv,
 577   ldst_unscaled,
 578   ldstexcl,
 579   ldstnapair_offs,
 580   ldstpair_off,
 581   ldstpair_indexed,
 582   loadlit,
 583   log_imm,
 584   log_shift,
 585   lse_atomic,
 586   movewide,
 587   pcreladdr,
 588   ic_system,
 589   sve_cpy,
 590   sve_index,
 591   sve_limm,
 592   sve_misc,
 593   sve_movprfx,
 594   sve_pred_zm,
 595   sve_shift_pred,
 596   sve_shift_unpred,
 597   sve_size_bhs,
 598   sve_size_bhsd,
 599   sve_size_hsd,
 600   sve_size_hsd2,
 601   sve_size_sd,
 602   sve_size_bh,
 603   sve_size_sd2,
 604   sve_size_13,
 605   sve_shift_tsz_hsd,
 606   sve_shift_tsz_bhsd,
 607   sve_size_tsz_bhs,
 608   testbranch,
 609   cryptosm3,
 610   cryptosm4,
 611   dotproduct,
 612 };
 613
 614 /* Opcode enumerators.  */
 615
 616 enum aarch64_op
 617 {
 618   OP_NIL,
 619   OP_STRB_POS,
 620   OP_LDRB_POS,
 621   OP_LDRSB_POS,
 622   OP_STRH_POS,
 623   OP_LDRH_POS,
 624   OP_LDRSH_POS,
 625   OP_STR_POS,
 626   OP_LDR_POS,
 627   OP_STRF_POS,
 628   OP_LDRF_POS,
 629   OP_LDRSW_POS,
 630   OP_PRFM_POS,
 631
 632   OP_STURB,
 633   OP_LDURB,
 634   OP_LDURSB,
 635   OP_STURH,
 636   OP_LDURH,
 637   OP_LDURSH,
 638   OP_STUR,
 639   OP_LDUR,
 640   OP_STURV,
 641   OP_LDURV,
 642   OP_LDURSW,
 643   OP_PRFUM,
 644
 645   OP_LDR_LIT,
 646   OP_LDRV_LIT,
 647   OP_LDRSW_LIT,
 648   OP_PRFM_LIT,
 649
 650   OP_ADD,
 651   OP_B,
 652   OP_BL,
 653
 654   OP_MOVN,
 655   OP_MOVZ,
 656   OP_MOVK,
 657
 658   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 659   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 660   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 661
 662   OP_MOV_V,             /* MOV alias for moving vector register.  */
 663
 664   OP_ASR_IMM,
 665   OP_LSR_IMM,
 666   OP_LSL_IMM,
 667
 668   OP_BIC,
 669
 670   OP_UBFX,
 671   OP_BFXIL,
 672   OP_SBFX,
 673   OP_SBFIZ,
 674   OP_BFI,
 675   OP_BFC,               /* ARMv8.2.  */
 676   OP_UBFIZ,
 677   OP_UXTB,
 678   OP_UXTH,
 679   OP_UXTW,
 680
 681   OP_CINC,
 682   OP_CINV,
 683   OP_CNEG,
 684   OP_CSET,
 685   OP_CSETM,
 686
 687   OP_FCVT,
 688   OP_FCVTN,
 689   OP_FCVTN2,
 690   OP_FCVTL,
 691   OP_FCVTL2,
 692   OP_FCVTXN_S,          /* Scalar version.  */
 693
 694   OP_ROR_IMM,
 695
 696   OP_SXTL,
 697   OP_SXTL2,
 698   OP_UXTL,
 699   OP_UXTL2,
 700
 701   OP_MOV_P_P,
 702   OP_MOV_Z_P_Z,
 703   OP_MOV_Z_V,
 704   OP_MOV_Z_Z,
 705   OP_MOV_Z_Zi,
 706   OP_MOVM_P_P_P,
 707   OP_MOVS_P_P,
 708   OP_MOVZS_P_P_P,
 709   OP_MOVZ_P_P_P,
 710   OP_NOTS_P_P_P_Z,
 711   OP_NOT_P_P_P_Z,
 712
 713   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 714
 715   OP_TOTAL_NUM,         /* Pseudo.  */
 716 };
 717
 718 /* Error types.  */
 719 enum err_type
 720 {
 721   ERR_OK,
 722   ERR_UND,
 723   ERR_UNP,
 724   ERR_NYI,
 725   ERR_VFI,
 726   ERR_NR_ENTRIES
 727 };
 728
 729 /* Maximum number of operands an instruction can have.  */
 730 #define AARCH64_MAX_OPND_NUM 6
 731 /* Maximum number of qualifier sequences an instruction can have.  */
 732 #define AARCH64_MAX_QLF_SEQ_NUM 10
 733 /* Operand qualifier typedef; optimized for the size.  */
 734 typedef unsigned char aarch64_opnd_qualifier_t;
 735 /* Operand qualifier sequence typedef.  */
 736 typedef aarch64_opnd_qualifier_t        \
 737           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 738
 739 /* FIXME: improve the efficiency.  */
 740 static inline bfd_boolean
 741 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 742 {
 743   int i;
 744   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 745     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 746       return FALSE;
 747   return TRUE;
 748 }
 749
 750 /*  Forward declare error reporting type.  */
 751 typedef struct aarch64_operand_error aarch64_operand_error;
 752 /* Forward declare instruction sequence type.  */
 753 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 754 /* Forward declare instruction definition.  */
 755 typedef struct aarch64_inst aarch64_inst;
 756
 757 /* This structure holds information for a particular opcode.  */
 758
 759 struct aarch64_opcode
 760 {
 761   /* The name of the mnemonic.  */
 762   const char *name;
 763
 764   /* The opcode itself.  Those bits which will be filled in with
 765      operands are zeroes.  */
 766   aarch64_insn opcode;
 767
 768   /* The opcode mask.  This is used by the disassembler.  This is a
 769      mask containing ones indicating those bits which must match the
 770      opcode field, and zeroes indicating those bits which need not
 771      match (and are presumably filled in by operands).  */
 772   aarch64_insn mask;
 773
 774   /* Instruction class.  */
 775   enum aarch64_insn_class iclass;
 776
 777   /* Enumerator identifier.  */
 778   enum aarch64_op op;
 779
 780   /* Which architecture variant provides this instruction.  */
 781   const aarch64_feature_set *avariant;
 782
 783   /* An array of operand codes.  Each code is an index into the
 784      operand table.  They appear in the order which the operands must
 785      appear in assembly code, and are terminated by a zero.  */
 786   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 787
 788   /* A list of operand qualifier code sequence.  Each operand qualifier
 789      code qualifies the corresponding operand code.  Each operand
 790      qualifier sequence specifies a valid opcode variant and related
 791      constraint on operands.  */
 792   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 793
 794   /* Flags providing information about this instruction */
 795   uint64_t flags;
 796
 797   /* Extra constraints on the instruction that the verifier checks.  */
 798   uint32_t constraints;
 799
 800   /* If nonzero, this operand and operand 0 are both registers and
 801      are required to have the same register number.  */
 802   unsigned char tied_operand;
 803
 804   /* If non-NULL, a function to verify that a given instruction is valid.  */
 805   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 806                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 807                               struct aarch64_instr_sequence *);
 808 };
 809
 810 typedef struct aarch64_opcode aarch64_opcode;
 811
 812 /* Table describing all the AArch64 opcodes.  */
 813 extern aarch64_opcode aarch64_opcode_table[];
 814
 815 /* Opcode flags.  */
 816 #define F_ALIAS (1 << 0)
 817 #define F_HAS_ALIAS (1 << 1)
 818 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 819    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 820 #define F_P1 (1 << 2)
 821 #define F_P2 (2 << 2)
 822 #define F_P3 (3 << 2)
 823 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 824 #define F_COND (1 << 4)
 825 /* Instruction has the field of 'sf'.  */
 826 #define F_SF (1 << 5)
 827 /* Instruction has the field of 'size:Q'.  */
 828 #define F_SIZEQ (1 << 6)
 829 /* Floating-point instruction has the field of 'type'.  */
 830 #define F_FPTYPE (1 << 7)
 831 /* AdvSIMD scalar instruction has the field of 'size'.  */
 832 #define F_SSIZE (1 << 8)
 833 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 834 #define F_T (1 << 9)
 835 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 836 #define F_GPRSIZE_IN_Q (1 << 10)
 837 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 838 #define F_LDS_SIZE (1 << 11)
 839 /* Optional operand; assume maximum of 1 operand can be optional.  */
 840 #define F_OPD0_OPT (1 << 12)
 841 #define F_OPD1_OPT (2 << 12)
 842 #define F_OPD2_OPT (3 << 12)
 843 #define F_OPD3_OPT (4 << 12)
 844 #define F_OPD4_OPT (5 << 12)
 845 /* Default value for the optional operand when omitted from the assembly.  */
 846 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 847 /* Instruction that is an alias of another instruction needs to be
 848    encoded/decoded by converting it to/from the real form, followed by
 849    the encoding/decoding according to the rules of the real opcode.
 850    This compares to the direct coding using the alias's information.
 851    N.B. this flag requires F_ALIAS to be used together.  */
 852 #define F_CONV (1 << 20)
 853 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 854    friendly pseudo instruction available only in the assembly code (thus will
 855    not show up in the disassembly).  */
 856 #define F_PSEUDO (1 << 21)
 857 /* Instruction has miscellaneous encoding/decoding rules.  */
 858 #define F_MISC (1 << 22)
 859 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 860 #define F_N (1 << 23)
 861 /* Opcode dependent field.  */
 862 #define F_OD(X) (((X) & 0x7) << 24)
 863 /* Instruction has the field of 'sz'.  */
 864 #define F_LSE_SZ (1 << 27)
 865 /* Require an exact qualifier match, even for NIL qualifiers.  */
 866 #define F_STRICT (1ULL << 28)
 867 /* This system instruction is used to read system registers.  */
 868 #define F_SYS_READ (1ULL << 29)
 869 /* This system instruction is used to write system registers.  */
 870 #define F_SYS_WRITE (1ULL << 30)
 871 /* This instruction has an extra constraint on it that imposes a requirement on
 872    subsequent instructions.  */
 873 #define F_SCAN (1ULL << 31)
 874 /* Next bit is 32.  */
 875
 876 /* Instruction constraints.  */
 877 /* This instruction has a predication constraint on the instruction at PC+4.  */
 878 #define C_SCAN_MOVPRFX (1U << 0)
 879 /* This instruction's operation width is determined by the operand with the
 880    largest element size.  */
 881 #define C_MAX_ELEM (1U << 1)
 882 /* Next bit is 2.  */
 883
 884 static inline bfd_boolean
 885 alias_opcode_p (const aarch64_opcode *opcode)
 886 {
 887   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 888 }
 889
 890 static inline bfd_boolean
 891 opcode_has_alias (const aarch64_opcode *opcode)
 892 {
 893   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 894 }
 895
 896 /* Priority for disassembling preference.  */
 897 static inline int
 898 opcode_priority (const aarch64_opcode *opcode)
 899 {
 900   return (opcode->flags >> 2) & 0x3;
 901 }
 902
 903 static inline bfd_boolean
 904 pseudo_opcode_p (const aarch64_opcode *opcode)
 905 {
 906   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 907 }
 908
 909 static inline bfd_boolean
 910 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 911 {
 912   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 913     ? TRUE : FALSE;
 914 }
 915
 916 static inline aarch64_insn
 917 get_optional_operand_default_value (const aarch64_opcode *opcode)
 918 {
 919   return (opcode->flags >> 15) & 0x1f;
 920 }
 921
 922 static inline unsigned int
 923 get_opcode_dependent_value (const aarch64_opcode *opcode)
 924 {
 925   return (opcode->flags >> 24) & 0x7;
 926 }
 927
 928 static inline bfd_boolean
 929 opcode_has_special_coder (const aarch64_opcode *opcode)
 930 {
 931   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 932           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 933     : FALSE;
 934 }
 935 \f
 936 struct aarch64_name_value_pair
 937 {
 938   const char *  name;
 939   aarch64_insn  value;
 940 };
 941
 942 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 943 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 944 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 945 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 946
 947 typedef struct
 948 {
 949   const char *  name;
 950   aarch64_insn  value;
 951   uint32_t      flags;
 952 } aarch64_sys_reg;
 953
 954 extern const aarch64_sys_reg aarch64_sys_regs [];
 955 extern const aarch64_sys_reg aarch64_pstatefields [];
 956 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 957 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 958                                                 const aarch64_sys_reg *);
 959 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 960                                                     const aarch64_sys_reg *);
 961
 962 typedef struct
 963 {
 964   const char *name;
 965   uint32_t value;
 966   uint32_t flags ;
 967 } aarch64_sys_ins_reg;
 968
 969 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 970 extern bfd_boolean
 971 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 972                                  const aarch64_sys_ins_reg *);
 973
 974 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 975 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 976 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 977 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 978 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 979
 980 /* Shift/extending operator kinds.
 981    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 982 enum aarch64_modifier_kind
 983 {
 984   AARCH64_MOD_NONE,
 985   AARCH64_MOD_MSL,
 986   AARCH64_MOD_ROR,
 987   AARCH64_MOD_ASR,
 988   AARCH64_MOD_LSR,
 989   AARCH64_MOD_LSL,
 990   AARCH64_MOD_UXTB,
 991   AARCH64_MOD_UXTH,
 992   AARCH64_MOD_UXTW,
 993   AARCH64_MOD_UXTX,
 994   AARCH64_MOD_SXTB,
 995   AARCH64_MOD_SXTH,
 996   AARCH64_MOD_SXTW,
 997   AARCH64_MOD_SXTX,
 998   AARCH64_MOD_MUL,
 999   AARCH64_MOD_MUL_VL,
1000 };
1001
1002 bfd_boolean
1003 aarch64_extend_operator_p (enum aarch64_modifier_kind);
1004
1005 enum aarch64_modifier_kind
1006 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1007 /* Condition.  */
1008
1009 typedef struct
1010 {
1011   /* A list of names with the first one as the disassembly preference;
1012      terminated by NULL if fewer than 3.  */
1013   const char *names[4];
1014   aarch64_insn value;
1015 } aarch64_cond;
1016
1017 extern const aarch64_cond aarch64_conds[16];
1018
1019 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1020 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1021 \f
1022 /* Structure representing an operand.  */
1023
1024 struct aarch64_opnd_info
1025 {
1026   enum aarch64_opnd type;
1027   aarch64_opnd_qualifier_t qualifier;
1028   int idx;
1029
1030   union
1031     {
1032       struct
1033         {
1034           unsigned regno;
1035         } reg;
1036       struct
1037         {
1038           unsigned int regno;
1039           int64_t index;
1040         } reglane;
1041       /* e.g. LVn.  */
1042       struct
1043         {
1044           unsigned first_regno : 5;
1045           unsigned num_regs : 3;
1046           /* 1 if it is a list of reg element.  */
1047           unsigned has_index : 1;
1048           /* Lane index; valid only when has_index is 1.  */
1049           int64_t index;
1050         } reglist;
1051       /* e.g. immediate or pc relative address offset.  */
1052       struct
1053         {
1054           int64_t value;
1055           unsigned is_fp : 1;
1056         } imm;
1057       /* e.g. address in STR (register offset).  */
1058       struct
1059         {
1060           unsigned base_regno;
1061           struct
1062             {
1063               union
1064                 {
1065                   int imm;
1066                   unsigned regno;
1067                 };
1068               unsigned is_reg;
1069             } offset;
1070           unsigned pcrel : 1;           /* PC-relative.  */
1071           unsigned writeback : 1;
1072           unsigned preind : 1;          /* Pre-indexed.  */
1073           unsigned postind : 1;         /* Post-indexed.  */
1074         } addr;
1075
1076       struct
1077         {
1078           /* The encoding of the system register.  */
1079           aarch64_insn value;
1080
1081           /* The system register flags.  */
1082           uint32_t flags;
1083         } sysreg;
1084
1085       const aarch64_cond *cond;
1086       /* The encoding of the PSTATE field.  */
1087       aarch64_insn pstatefield;
1088       const aarch64_sys_ins_reg *sysins_op;
1089       const struct aarch64_name_value_pair *barrier;
1090       const struct aarch64_name_value_pair *hint_option;
1091       const struct aarch64_name_value_pair *prfop;
1092     };
1093
1094   /* Operand shifter; in use when the operand is a register offset address,
1095      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1096   struct
1097     {
1098       enum aarch64_modifier_kind kind;
1099       unsigned operator_present: 1;     /* Only valid during encoding.  */
1100       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1101       unsigned amount_present: 1;
1102       int64_t amount;
1103     } shifter;
1104
1105   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1106                            to be done on it.  In some (but not all) of these
1107                            cases, we need to tell libopcodes to skip the
1108                            constraint checking and the encoding for this
1109                            operand, so that the libopcodes can pick up the
1110                            right opcode before the operand is fixed-up.  This
1111                            flag should only be used during the
1112                            assembling/encoding.  */
1113   unsigned present:1;   /* Whether this operand is present in the assembly
1114                            line; not used during the disassembly.  */
1115 };
1116
1117 typedef struct aarch64_opnd_info aarch64_opnd_info;
1118
1119 /* Structure representing an instruction.
1120
1121    It is used during both the assembling and disassembling.  The assembler
1122    fills an aarch64_inst after a successful parsing and then passes it to the
1123    encoding routine to do the encoding.  During the disassembling, the
1124    disassembler calls the decoding routine to decode a binary instruction; on a
1125    successful return, such a structure will be filled with information of the
1126    instruction; then the disassembler uses the information to print out the
1127    instruction.  */
1128
1129 struct aarch64_inst
1130 {
1131   /* The value of the binary instruction.  */
1132   aarch64_insn value;
1133
1134   /* Corresponding opcode entry.  */
1135   const aarch64_opcode *opcode;
1136
1137   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1138   const aarch64_cond *cond;
1139
1140   /* Operands information.  */
1141   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1142 };
1143
1144 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1145 #define HINT_OPD_CSYNC  0x11
1146 #define HINT_OPD_C      0x22
1147 #define HINT_OPD_J      0x24
1148 #define HINT_OPD_JC     0x26
1149 #define HINT_OPD_NULL   0x00
1150
1151 \f
1152 /* Diagnosis related declaration and interface.  */
1153
1154 /* Operand error kind enumerators.
1155
1156    AARCH64_OPDE_RECOVERABLE
1157      Less severe error found during the parsing, very possibly because that
1158      GAS has picked up a wrong instruction template for the parsing.
1159
1160    AARCH64_OPDE_SYNTAX_ERROR
1161      General syntax error; it can be either a user error, or simply because
1162      that GAS is trying a wrong instruction template.
1163
1164    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1165      Definitely a user syntax error.
1166
1167    AARCH64_OPDE_INVALID_VARIANT
1168      No syntax error, but the operands are not a valid combination, e.g.
1169      FMOV D0,S0
1170
1171    AARCH64_OPDE_UNTIED_OPERAND
1172      The asm failed to use the same register for a destination operand
1173      and a tied source operand.
1174
1175    AARCH64_OPDE_OUT_OF_RANGE
1176      Error about some immediate value out of a valid range.
1177
1178    AARCH64_OPDE_UNALIGNED
1179      Error about some immediate value not properly aligned (i.e. not being a
1180      multiple times of a certain value).
1181
1182    AARCH64_OPDE_REG_LIST
1183      Error about the register list operand having unexpected number of
1184      registers.
1185
1186    AARCH64_OPDE_OTHER_ERROR
1187      Error of the highest severity and used for any severe issue that does not
1188      fall into any of the above categories.
1189
1190    The enumerators are only interesting to GAS.  They are declared here (in
1191    libopcodes) because that some errors are detected (and then notified to GAS)
1192    by libopcodes (rather than by GAS solely).
1193
1194    The first three errors are only deteced by GAS while the
1195    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1196    only libopcodes has the information about the valid variants of each
1197    instruction.
1198
1199    The enumerators have an increasing severity.  This is helpful when there are
1200    multiple instruction templates available for a given mnemonic name (e.g.
1201    FMOV); this mechanism will help choose the most suitable template from which
1202    the generated diagnostics can most closely describe the issues, if any.  */
1203
1204 enum aarch64_operand_error_kind
1205 {
1206   AARCH64_OPDE_NIL,
1207   AARCH64_OPDE_RECOVERABLE,
1208   AARCH64_OPDE_SYNTAX_ERROR,
1209   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1210   AARCH64_OPDE_INVALID_VARIANT,
1211   AARCH64_OPDE_UNTIED_OPERAND,
1212   AARCH64_OPDE_OUT_OF_RANGE,
1213   AARCH64_OPDE_UNALIGNED,
1214   AARCH64_OPDE_REG_LIST,
1215   AARCH64_OPDE_OTHER_ERROR
1216 };
1217
1218 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1219 struct aarch64_operand_error
1220 {
1221   enum aarch64_operand_error_kind kind;
1222   int index;
1223   const char *error;
1224   int data[3];  /* Some data for extra information.  */
1225   bfd_boolean non_fatal;
1226 };
1227
1228 /* AArch64 sequence structure used to track instructions with F_SCAN
1229    dependencies for both assembler and disassembler.  */
1230 struct aarch64_instr_sequence
1231 {
1232   /* The instruction that caused this sequence to be opened.  */
1233   aarch64_inst *instr;
1234   /* The number of instructions the above instruction allows to be kept in the
1235      sequence before an automatic close is done.  */
1236   int num_insns;
1237   /* The instructions currently added to the sequence.  */
1238   aarch64_inst **current_insns;
1239   /* The number of instructions already in the sequence.  */
1240   int next_insn;
1241 };
1242
1243 /* Encoding entrypoint.  */
1244
1245 extern int
1246 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1247                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1248                        aarch64_operand_error *, aarch64_instr_sequence *);
1249
1250 extern const aarch64_opcode *
1251 aarch64_replace_opcode (struct aarch64_inst *,
1252                         const aarch64_opcode *);
1253
1254 /* Given the opcode enumerator OP, return the pointer to the corresponding
1255    opcode entry.  */
1256
1257 extern const aarch64_opcode *
1258 aarch64_get_opcode (enum aarch64_op);
1259
1260 /* Generate the string representation of an operand.  */
1261 extern void
1262 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1263                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1264                        char **);
1265
1266 /* Miscellaneous interface.  */
1267
1268 extern int
1269 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1270
1271 extern aarch64_opnd_qualifier_t
1272 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1273                                 const aarch64_opnd_qualifier_t, int);
1274
1275 extern bfd_boolean
1276 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1277
1278 extern int
1279 aarch64_num_of_operands (const aarch64_opcode *);
1280
1281 extern int
1282 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1283
1284 extern int
1285 aarch64_zero_register_p (const aarch64_opnd_info *);
1286
1287 extern enum err_type
1288 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1289                      aarch64_operand_error *);
1290
1291 extern void
1292 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1293
1294 /* Given an operand qualifier, return the expected data element size
1295    of a qualified operand.  */
1296 extern unsigned char
1297 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1298
1299 extern enum aarch64_operand_class
1300 aarch64_get_operand_class (enum aarch64_opnd);
1301
1302 extern const char *
1303 aarch64_get_operand_name (enum aarch64_opnd);
1304
1305 extern const char *
1306 aarch64_get_operand_desc (enum aarch64_opnd);
1307
1308 extern bfd_boolean
1309 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1310
1311 #ifdef DEBUG_AARCH64
1312 extern int debug_dump;
1313
1314 extern void
1315 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1316
1317 #define DEBUG_TRACE(M, ...)                                     \
1318   {                                                             \
1319     if (debug_dump)                                             \
1320       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1321   }
1322
1323 #define DEBUG_TRACE_IF(C, M, ...)                               \
1324   {                                                             \
1325     if (debug_dump && (C))                                      \
1326       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1327   }
1328 #else  /* !DEBUG_AARCH64 */
1329 #define DEBUG_TRACE(M, ...) ;
1330 #define DEBUG_TRACE_IF(C, M, ...) ;
1331 #endif /* DEBUG_AARCH64 */
1332
1333 extern const char *const aarch64_sve_pattern_array[32];
1334 extern const char *const aarch64_sve_prfop_array[16];
1335
1336 #ifdef __cplusplus
1337 }
1338 #endif
1339
1340 #endif /* OPCODE_AARCH64_H */