1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn
;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41 #define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
42 #define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43 #define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44 #define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
45 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
46 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
47 #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
48 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
49 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
50 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
51 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
52 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
53 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
54 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
55 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
56 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
57 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
58 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
59 #define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
60 #define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
61 #define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
62 #define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
63 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
64 #define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
65 #define AARCH64_FEATURE_V8_6 0x00000002 /* ARMv8.6 processors. */
66 #define AARCH64_FEATURE_BFLOAT16 0x00000004 /* Bfloat16 insns. */
68 /* Flag Manipulation insns. */
69 #define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
70 /* FRINT[32,64][Z,X] insns. */
71 #define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
73 #define AARCH64_FEATURE_SB 0x10000000000ULL
74 /* Execution and Data Prediction Restriction instructions. */
75 #define AARCH64_FEATURE_PREDRES 0x20000000000ULL
77 #define AARCH64_FEATURE_CVADP 0x40000000000ULL
78 /* Random Number instructions. */
79 #define AARCH64_FEATURE_RNG 0x80000000000ULL
80 /* BTI instructions. */
81 #define AARCH64_FEATURE_BTI 0x100000000000ULL
83 #define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
84 /* ID_PFR2 instructions. */
85 #define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
86 /* SSBS mechanism enabled. */
87 #define AARCH64_FEATURE_SSBS 0x800000000000ULL
88 /* Memory Tagging Extension. */
89 #define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
90 /* Transactional Memory Extension. */
91 #define AARCH64_FEATURE_TME 0x2000000000000ULL
93 /* Matrix Multiply instructions */
94 #define AARCH64_FEATURE_I8MM 0x10000000000000ULL
95 #define AARCH64_FEATURE_F32MM 0x20000000000000ULL
96 #define AARCH64_FEATURE_F64MM 0x40000000000000ULL
98 /* SVE2 instructions. */
99 #define AARCH64_FEATURE_SVE2 0x000000010
100 #define AARCH64_FEATURE_SVE2_AES 0x000000080
101 #define AARCH64_FEATURE_SVE2_BITPERM 0x000000100
102 #define AARCH64_FEATURE_SVE2_SM4 0x000000200
103 #define AARCH64_FEATURE_SVE2_SHA3 0x000000400
105 /* Crypto instructions are the combination of AES and SHA2. */
106 #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
108 /* Architectures are the sum of the base and extensions. */
109 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
111 | AARCH64_FEATURE_SIMD)
112 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
113 AARCH64_FEATURE_CRC \
114 | AARCH64_FEATURE_V8_1 \
115 | AARCH64_FEATURE_LSE \
116 | AARCH64_FEATURE_PAN \
117 | AARCH64_FEATURE_LOR \
118 | AARCH64_FEATURE_RDMA)
119 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
120 AARCH64_FEATURE_V8_2 \
121 | AARCH64_FEATURE_RAS)
122 #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
123 AARCH64_FEATURE_V8_3 \
124 | AARCH64_FEATURE_RCPC \
125 | AARCH64_FEATURE_COMPNUM)
126 #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
127 AARCH64_FEATURE_V8_4 \
128 | AARCH64_FEATURE_DOTPROD \
129 | AARCH64_FEATURE_F16_FML)
130 #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
131 AARCH64_FEATURE_V8_5 \
132 | AARCH64_FEATURE_FLAGMANIP \
133 | AARCH64_FEATURE_FRINTTS \
134 | AARCH64_FEATURE_SB \
135 | AARCH64_FEATURE_PREDRES \
136 | AARCH64_FEATURE_CVADP \
137 | AARCH64_FEATURE_BTI \
138 | AARCH64_FEATURE_SCXTNUM \
139 | AARCH64_FEATURE_ID_PFR2 \
140 | AARCH64_FEATURE_SSBS)
141 #define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
142 AARCH64_FEATURE_V8_6 \
143 | AARCH64_FEATURE_BFLOAT16 \
144 | AARCH64_FEATURE_I8MM)
146 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
147 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
149 /* CPU-specific features. */
150 typedef unsigned long long aarch64_feature_set
;
152 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
153 ((~(CPU) & (FEAT)) == 0)
155 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
156 (((CPU) & (FEAT)) != 0)
158 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
159 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
161 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
164 (TARG) = (F1) | (F2); \
168 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
171 (TARG) = (F1) &~ (F2); \
175 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
177 enum aarch64_operand_class
179 AARCH64_OPND_CLASS_NIL
,
180 AARCH64_OPND_CLASS_INT_REG
,
181 AARCH64_OPND_CLASS_MODIFIED_REG
,
182 AARCH64_OPND_CLASS_FP_REG
,
183 AARCH64_OPND_CLASS_SIMD_REG
,
184 AARCH64_OPND_CLASS_SIMD_ELEMENT
,
185 AARCH64_OPND_CLASS_SISD_REG
,
186 AARCH64_OPND_CLASS_SIMD_REGLIST
,
187 AARCH64_OPND_CLASS_SVE_REG
,
188 AARCH64_OPND_CLASS_PRED_REG
,
189 AARCH64_OPND_CLASS_ADDRESS
,
190 AARCH64_OPND_CLASS_IMMEDIATE
,
191 AARCH64_OPND_CLASS_SYSTEM
,
192 AARCH64_OPND_CLASS_COND
,
195 /* Operand code that helps both parsing and coding.
196 Keep AARCH64_OPERANDS synced. */
200 AARCH64_OPND_NIL
, /* no operand---MUST BE FIRST!*/
202 AARCH64_OPND_Rd
, /* Integer register as destination. */
203 AARCH64_OPND_Rn
, /* Integer register as source. */
204 AARCH64_OPND_Rm
, /* Integer register as source. */
205 AARCH64_OPND_Rt
, /* Integer register used in ld/st instructions. */
206 AARCH64_OPND_Rt2
, /* Integer register used in ld/st pair instructions. */
207 AARCH64_OPND_Rt_SP
, /* Integer Rt or SP used in STG instructions. */
208 AARCH64_OPND_Rs
, /* Integer register used in ld/st exclusive. */
209 AARCH64_OPND_Ra
, /* Integer register used in ddp_3src instructions. */
210 AARCH64_OPND_Rt_SYS
, /* Integer register used in system instructions. */
212 AARCH64_OPND_Rd_SP
, /* Integer Rd or SP. */
213 AARCH64_OPND_Rn_SP
, /* Integer Rn or SP. */
214 AARCH64_OPND_Rm_SP
, /* Integer Rm or SP. */
215 AARCH64_OPND_PAIRREG
, /* Paired register operand. */
216 AARCH64_OPND_Rm_EXT
, /* Integer Rm extended. */
217 AARCH64_OPND_Rm_SFT
, /* Integer Rm shifted. */
219 AARCH64_OPND_Fd
, /* Floating-point Fd. */
220 AARCH64_OPND_Fn
, /* Floating-point Fn. */
221 AARCH64_OPND_Fm
, /* Floating-point Fm. */
222 AARCH64_OPND_Fa
, /* Floating-point Fa. */
223 AARCH64_OPND_Ft
, /* Floating-point Ft. */
224 AARCH64_OPND_Ft2
, /* Floating-point Ft2. */
226 AARCH64_OPND_Sd
, /* AdvSIMD Scalar Sd. */
227 AARCH64_OPND_Sn
, /* AdvSIMD Scalar Sn. */
228 AARCH64_OPND_Sm
, /* AdvSIMD Scalar Sm. */
230 AARCH64_OPND_Va
, /* AdvSIMD Vector Va. */
231 AARCH64_OPND_Vd
, /* AdvSIMD Vector Vd. */
232 AARCH64_OPND_Vn
, /* AdvSIMD Vector Vn. */
233 AARCH64_OPND_Vm
, /* AdvSIMD Vector Vm. */
234 AARCH64_OPND_VdD1
, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
235 AARCH64_OPND_VnD1
, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
236 AARCH64_OPND_Ed
, /* AdvSIMD Vector Element Vd. */
237 AARCH64_OPND_En
, /* AdvSIMD Vector Element Vn. */
238 AARCH64_OPND_Em
, /* AdvSIMD Vector Element Vm. */
239 AARCH64_OPND_Em16
, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
241 AARCH64_OPND_LVn
, /* AdvSIMD Vector register list used in e.g. TBL. */
242 AARCH64_OPND_LVt
, /* AdvSIMD Vector register list used in ld/st. */
243 AARCH64_OPND_LVt_AL
, /* AdvSIMD Vector register list for loading single
244 structure to all lanes. */
245 AARCH64_OPND_LEt
, /* AdvSIMD Vector Element list. */
247 AARCH64_OPND_CRn
, /* Co-processor register in CRn field. */
248 AARCH64_OPND_CRm
, /* Co-processor register in CRm field. */
250 AARCH64_OPND_IDX
, /* AdvSIMD EXT index operand. */
251 AARCH64_OPND_MASK
, /* AdvSIMD EXT index operand. */
252 AARCH64_OPND_IMM_VLSL
,/* Immediate for shifting vector registers left. */
253 AARCH64_OPND_IMM_VLSR
,/* Immediate for shifting vector registers right. */
254 AARCH64_OPND_SIMD_IMM
,/* AdvSIMD modified immediate without shift. */
255 AARCH64_OPND_SIMD_IMM_SFT
, /* AdvSIMD modified immediate with shift. */
256 AARCH64_OPND_SIMD_FPIMM
,/* AdvSIMD 8-bit fp immediate. */
257 AARCH64_OPND_SHLL_IMM
,/* Immediate shift for AdvSIMD SHLL instruction
259 AARCH64_OPND_IMM0
, /* Immediate for #0. */
260 AARCH64_OPND_FPIMM0
, /* Immediate for #0.0. */
261 AARCH64_OPND_FPIMM
, /* Floating-point Immediate. */
262 AARCH64_OPND_IMMR
, /* Immediate #<immr> in e.g. BFM. */
263 AARCH64_OPND_IMMS
, /* Immediate #<imms> in e.g. BFM. */
264 AARCH64_OPND_WIDTH
, /* Immediate #<width> in e.g. BFI. */
265 AARCH64_OPND_IMM
, /* Immediate. */
266 AARCH64_OPND_IMM_2
, /* Immediate. */
267 AARCH64_OPND_UIMM3_OP1
,/* Unsigned 3-bit immediate in the op1 field. */
268 AARCH64_OPND_UIMM3_OP2
,/* Unsigned 3-bit immediate in the op2 field. */
269 AARCH64_OPND_UIMM4
, /* Unsigned 4-bit immediate in the CRm field. */
270 AARCH64_OPND_UIMM4_ADDG
,/* Unsigned 4-bit immediate in addg/subg. */
271 AARCH64_OPND_UIMM7
, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
272 AARCH64_OPND_UIMM10
, /* Unsigned 10-bit immediate in addg/subg. */
273 AARCH64_OPND_BIT_NUM
, /* Immediate. */
274 AARCH64_OPND_EXCEPTION
,/* imm16 operand in exception instructions. */
275 AARCH64_OPND_CCMP_IMM
,/* Immediate in conditional compare instructions. */
276 AARCH64_OPND_SIMM5
, /* 5-bit signed immediate in the imm5 field. */
277 AARCH64_OPND_NZCV
, /* Flag bit specifier giving an alternative value for
278 each condition flag. */
280 AARCH64_OPND_LIMM
, /* Logical Immediate. */
281 AARCH64_OPND_AIMM
, /* Arithmetic immediate. */
282 AARCH64_OPND_HALF
, /* #<imm16>{, LSL #<shift>} operand in move wide. */
283 AARCH64_OPND_FBITS
, /* FP #<fbits> operand in e.g. SCVTF */
284 AARCH64_OPND_IMM_MOV
, /* Immediate operand for the MOV alias. */
285 AARCH64_OPND_IMM_ROT1
, /* Immediate rotate operand for FCMLA. */
286 AARCH64_OPND_IMM_ROT2
, /* Immediate rotate operand for indexed FCMLA. */
287 AARCH64_OPND_IMM_ROT3
, /* Immediate rotate operand for FCADD. */
289 AARCH64_OPND_COND
, /* Standard condition as the last operand. */
290 AARCH64_OPND_COND1
, /* Same as the above, but excluding AL and NV. */
292 AARCH64_OPND_ADDR_ADRP
, /* Memory address for ADRP */
293 AARCH64_OPND_ADDR_PCREL14
, /* 14-bit PC-relative address for e.g. TBZ. */
294 AARCH64_OPND_ADDR_PCREL19
, /* 19-bit PC-relative address for e.g. LDR. */
295 AARCH64_OPND_ADDR_PCREL21
, /* 21-bit PC-relative address for e.g. ADR. */
296 AARCH64_OPND_ADDR_PCREL26
, /* 26-bit PC-relative address for e.g. BL. */
298 AARCH64_OPND_ADDR_SIMPLE
, /* Address of ld/st exclusive. */
299 AARCH64_OPND_ADDR_REGOFF
, /* Address of register offset. */
300 AARCH64_OPND_ADDR_SIMM7
, /* Address of signed 7-bit immediate. */
301 AARCH64_OPND_ADDR_SIMM9
, /* Address of signed 9-bit immediate. */
302 AARCH64_OPND_ADDR_SIMM9_2
, /* Same as the above, but the immediate is
303 negative or unaligned and there is
304 no writeback allowed. This operand code
305 is only used to support the programmer-
306 friendly feature of using LDR/STR as the
307 the mnemonic name for LDUR/STUR instructions
308 wherever there is no ambiguity. */
309 AARCH64_OPND_ADDR_SIMM10
, /* Address of signed 10-bit immediate. */
310 AARCH64_OPND_ADDR_SIMM11
, /* Address with a signed 11-bit (multiple of
312 AARCH64_OPND_ADDR_UIMM12
, /* Address of unsigned 12-bit immediate. */
313 AARCH64_OPND_ADDR_SIMM13
, /* Address with a signed 13-bit (multiple of
315 AARCH64_OPND_SIMD_ADDR_SIMPLE
,/* Address of ld/st multiple structures. */
316 AARCH64_OPND_ADDR_OFFSET
, /* Address with an optional 9-bit immediate. */
317 AARCH64_OPND_SIMD_ADDR_POST
, /* Address of ld/st multiple post-indexed. */
319 AARCH64_OPND_SYSREG
, /* System register operand. */
320 AARCH64_OPND_PSTATEFIELD
, /* PSTATE field name operand. */
321 AARCH64_OPND_SYSREG_AT
, /* System register <at_op> operand. */
322 AARCH64_OPND_SYSREG_DC
, /* System register <dc_op> operand. */
323 AARCH64_OPND_SYSREG_IC
, /* System register <ic_op> operand. */
324 AARCH64_OPND_SYSREG_TLBI
, /* System register <tlbi_op> operand. */
325 AARCH64_OPND_SYSREG_SR
, /* System register RCTX operand. */
326 AARCH64_OPND_BARRIER
, /* Barrier operand. */
327 AARCH64_OPND_BARRIER_ISB
, /* Barrier operand for ISB. */
328 AARCH64_OPND_PRFOP
, /* Prefetch operation. */
329 AARCH64_OPND_BARRIER_PSB
, /* Barrier operand for PSB. */
330 AARCH64_OPND_BTI_TARGET
, /* BTI {<target>}. */
332 AARCH64_OPND_SVE_ADDR_RI_S4x16
, /* SVE [<Xn|SP>, #<simm4>*16]. */
333 AARCH64_OPND_SVE_ADDR_RI_S4x32
, /* SVE [<Xn|SP>, #<simm4>*32]. */
334 AARCH64_OPND_SVE_ADDR_RI_S4xVL
, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
335 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
336 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
337 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
338 AARCH64_OPND_SVE_ADDR_RI_S6xVL
, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
339 AARCH64_OPND_SVE_ADDR_RI_S9xVL
, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
340 AARCH64_OPND_SVE_ADDR_RI_U6
, /* SVE [<Xn|SP>, #<uimm6>]. */
341 AARCH64_OPND_SVE_ADDR_RI_U6x2
, /* SVE [<Xn|SP>, #<uimm6>*2]. */
342 AARCH64_OPND_SVE_ADDR_RI_U6x4
, /* SVE [<Xn|SP>, #<uimm6>*4]. */
343 AARCH64_OPND_SVE_ADDR_RI_U6x8
, /* SVE [<Xn|SP>, #<uimm6>*8]. */
344 AARCH64_OPND_SVE_ADDR_R
, /* SVE [<Xn|SP>]. */
345 AARCH64_OPND_SVE_ADDR_RR
, /* SVE [<Xn|SP>, <Xm|XZR>]. */
346 AARCH64_OPND_SVE_ADDR_RR_LSL1
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
347 AARCH64_OPND_SVE_ADDR_RR_LSL2
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
348 AARCH64_OPND_SVE_ADDR_RR_LSL3
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
349 AARCH64_OPND_SVE_ADDR_RX
, /* SVE [<Xn|SP>, <Xm>]. */
350 AARCH64_OPND_SVE_ADDR_RX_LSL1
, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
351 AARCH64_OPND_SVE_ADDR_RX_LSL2
, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
352 AARCH64_OPND_SVE_ADDR_RX_LSL3
, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
353 AARCH64_OPND_SVE_ADDR_ZX
, /* SVE [Zn.<T>{, <Xm>}]. */
354 AARCH64_OPND_SVE_ADDR_RZ
, /* SVE [<Xn|SP>, Zm.D]. */
355 AARCH64_OPND_SVE_ADDR_RZ_LSL1
, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
356 AARCH64_OPND_SVE_ADDR_RZ_LSL2
, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
357 AARCH64_OPND_SVE_ADDR_RZ_LSL3
, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
358 AARCH64_OPND_SVE_ADDR_RZ_XTW_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
359 Bit 14 controls S/U choice. */
360 AARCH64_OPND_SVE_ADDR_RZ_XTW_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
361 Bit 22 controls S/U choice. */
362 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
363 Bit 14 controls S/U choice. */
364 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
365 Bit 22 controls S/U choice. */
366 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
367 Bit 14 controls S/U choice. */
368 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
369 Bit 22 controls S/U choice. */
370 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
371 Bit 14 controls S/U choice. */
372 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
373 Bit 22 controls S/U choice. */
374 AARCH64_OPND_SVE_ADDR_ZI_U5
, /* SVE [Zn.<T>, #<uimm5>]. */
375 AARCH64_OPND_SVE_ADDR_ZI_U5x2
, /* SVE [Zn.<T>, #<uimm5>*2]. */
376 AARCH64_OPND_SVE_ADDR_ZI_U5x4
, /* SVE [Zn.<T>, #<uimm5>*4]. */
377 AARCH64_OPND_SVE_ADDR_ZI_U5x8
, /* SVE [Zn.<T>, #<uimm5>*8]. */
378 AARCH64_OPND_SVE_ADDR_ZZ_LSL
, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
379 AARCH64_OPND_SVE_ADDR_ZZ_SXTW
, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
380 AARCH64_OPND_SVE_ADDR_ZZ_UXTW
, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
381 AARCH64_OPND_SVE_AIMM
, /* SVE unsigned arithmetic immediate. */
382 AARCH64_OPND_SVE_ASIMM
, /* SVE signed arithmetic immediate. */
383 AARCH64_OPND_SVE_FPIMM8
, /* SVE 8-bit floating-point immediate. */
384 AARCH64_OPND_SVE_I1_HALF_ONE
, /* SVE choice between 0.5 and 1.0. */
385 AARCH64_OPND_SVE_I1_HALF_TWO
, /* SVE choice between 0.5 and 2.0. */
386 AARCH64_OPND_SVE_I1_ZERO_ONE
, /* SVE choice between 0.0 and 1.0. */
387 AARCH64_OPND_SVE_IMM_ROT1
, /* SVE 1-bit rotate operand (90 or 270). */
388 AARCH64_OPND_SVE_IMM_ROT2
, /* SVE 2-bit rotate operand (N*90). */
389 AARCH64_OPND_SVE_IMM_ROT3
, /* SVE cadd 1-bit rotate (90 or 270). */
390 AARCH64_OPND_SVE_INV_LIMM
, /* SVE inverted logical immediate. */
391 AARCH64_OPND_SVE_LIMM
, /* SVE logical immediate. */
392 AARCH64_OPND_SVE_LIMM_MOV
, /* SVE logical immediate for MOV. */
393 AARCH64_OPND_SVE_PATTERN
, /* SVE vector pattern enumeration. */
394 AARCH64_OPND_SVE_PATTERN_SCALED
, /* Likewise, with additional MUL factor. */
395 AARCH64_OPND_SVE_PRFOP
, /* SVE prefetch operation. */
396 AARCH64_OPND_SVE_Pd
, /* SVE p0-p15 in Pd. */
397 AARCH64_OPND_SVE_Pg3
, /* SVE p0-p7 in Pg. */
398 AARCH64_OPND_SVE_Pg4_5
, /* SVE p0-p15 in Pg, bits [8,5]. */
399 AARCH64_OPND_SVE_Pg4_10
, /* SVE p0-p15 in Pg, bits [13,10]. */
400 AARCH64_OPND_SVE_Pg4_16
, /* SVE p0-p15 in Pg, bits [19,16]. */
401 AARCH64_OPND_SVE_Pm
, /* SVE p0-p15 in Pm. */
402 AARCH64_OPND_SVE_Pn
, /* SVE p0-p15 in Pn. */
403 AARCH64_OPND_SVE_Pt
, /* SVE p0-p15 in Pt. */
404 AARCH64_OPND_SVE_Rm
, /* Integer Rm or ZR, alt. SVE position. */
405 AARCH64_OPND_SVE_Rn_SP
, /* Integer Rn or SP, alt. SVE position. */
406 AARCH64_OPND_SVE_SHLIMM_PRED
, /* SVE shift left amount (predicated). */
407 AARCH64_OPND_SVE_SHLIMM_UNPRED
, /* SVE shift left amount (unpredicated). */
408 AARCH64_OPND_SVE_SHLIMM_UNPRED_22
, /* SVE 3 bit shift left unpred. */
409 AARCH64_OPND_SVE_SHRIMM_PRED
, /* SVE shift right amount (predicated). */
410 AARCH64_OPND_SVE_SHRIMM_UNPRED
, /* SVE shift right amount (unpredicated). */
411 AARCH64_OPND_SVE_SHRIMM_UNPRED_22
, /* SVE 3 bit shift right unpred. */
412 AARCH64_OPND_SVE_SIMM5
, /* SVE signed 5-bit immediate. */
413 AARCH64_OPND_SVE_SIMM5B
, /* SVE secondary signed 5-bit immediate. */
414 AARCH64_OPND_SVE_SIMM6
, /* SVE signed 6-bit immediate. */
415 AARCH64_OPND_SVE_SIMM8
, /* SVE signed 8-bit immediate. */
416 AARCH64_OPND_SVE_UIMM3
, /* SVE unsigned 3-bit immediate. */
417 AARCH64_OPND_SVE_UIMM7
, /* SVE unsigned 7-bit immediate. */
418 AARCH64_OPND_SVE_UIMM8
, /* SVE unsigned 8-bit immediate. */
419 AARCH64_OPND_SVE_UIMM8_53
, /* SVE split unsigned 8-bit immediate. */
420 AARCH64_OPND_SVE_VZn
, /* Scalar SIMD&FP register in Zn field. */
421 AARCH64_OPND_SVE_Vd
, /* Scalar SIMD&FP register in Vd. */
422 AARCH64_OPND_SVE_Vm
, /* Scalar SIMD&FP register in Vm. */
423 AARCH64_OPND_SVE_Vn
, /* Scalar SIMD&FP register in Vn. */
424 AARCH64_OPND_SVE_Za_5
, /* SVE vector register in Za, bits [9,5]. */
425 AARCH64_OPND_SVE_Za_16
, /* SVE vector register in Za, bits [20,16]. */
426 AARCH64_OPND_SVE_Zd
, /* SVE vector register in Zd. */
427 AARCH64_OPND_SVE_Zm_5
, /* SVE vector register in Zm, bits [9,5]. */
428 AARCH64_OPND_SVE_Zm_16
, /* SVE vector register in Zm, bits [20,16]. */
429 AARCH64_OPND_SVE_Zm3_INDEX
, /* z0-z7[0-3] in Zm, bits [20,16]. */
430 AARCH64_OPND_SVE_Zm3_22_INDEX
, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
431 AARCH64_OPND_SVE_Zm3_11_INDEX
, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
432 AARCH64_OPND_SVE_Zm4_11_INDEX
, /* z0-z15[0-3] in Zm plus bit 11. */
433 AARCH64_OPND_SVE_Zm4_INDEX
, /* z0-z15[0-1] in Zm, bits [20,16]. */
434 AARCH64_OPND_SVE_Zn
, /* SVE vector register in Zn. */
435 AARCH64_OPND_SVE_Zn_INDEX
, /* Indexed SVE vector register, for DUP. */
436 AARCH64_OPND_SVE_ZnxN
, /* SVE vector register list in Zn. */
437 AARCH64_OPND_SVE_Zt
, /* SVE vector register in Zt. */
438 AARCH64_OPND_SVE_ZtxN
, /* SVE vector register list in Zt. */
439 AARCH64_OPND_TME_UIMM16
, /* TME unsigned 16-bit immediate. */
440 AARCH64_OPND_SM3_IMM2
, /* SM3 encodes lane in bits [13, 14]. */
443 /* Qualifier constrains an operand. It either specifies a variant of an
444 operand type or limits values available to an operand type.
446 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
448 enum aarch64_opnd_qualifier
450 /* Indicating no further qualification on an operand. */
451 AARCH64_OPND_QLF_NIL
,
453 /* Qualifying an operand which is a general purpose (integer) register;
454 indicating the operand data size or a specific register. */
455 AARCH64_OPND_QLF_W
, /* Wn, WZR or WSP. */
456 AARCH64_OPND_QLF_X
, /* Xn, XZR or XSP. */
457 AARCH64_OPND_QLF_WSP
, /* WSP. */
458 AARCH64_OPND_QLF_SP
, /* SP. */
460 /* Qualifying an operand which is a floating-point register, a SIMD
461 vector element or a SIMD vector element list; indicating operand data
462 size or the size of each SIMD vector element in the case of a SIMD
464 These qualifiers are also used to qualify an address operand to
465 indicate the size of data element a load/store instruction is
467 They are also used for the immediate shift operand in e.g. SSHR. Such
468 a use is only for the ease of operand encoding/decoding and qualifier
469 sequence matching; such a use should not be applied widely; use the value
470 constraint qualifiers for immediate operands wherever possible. */
471 AARCH64_OPND_QLF_S_B
,
472 AARCH64_OPND_QLF_S_H
,
473 AARCH64_OPND_QLF_S_S
,
474 AARCH64_OPND_QLF_S_D
,
475 AARCH64_OPND_QLF_S_Q
,
476 /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
477 or 2 x 2 byte are selected by the instruction. Other than that they have
478 no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
479 for syntactical reasons and is an exception from normal AArch64
480 disassembly scheme. */
481 AARCH64_OPND_QLF_S_4B
,
482 AARCH64_OPND_QLF_S_2H
,
484 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
485 register list; indicating register shape.
486 They are also used for the immediate shift operand in e.g. SSHR. Such
487 a use is only for the ease of operand encoding/decoding and qualifier
488 sequence matching; such a use should not be applied widely; use the value
489 constraint qualifiers for immediate operands wherever possible. */
490 AARCH64_OPND_QLF_V_4B
,
491 AARCH64_OPND_QLF_V_8B
,
492 AARCH64_OPND_QLF_V_16B
,
493 AARCH64_OPND_QLF_V_2H
,
494 AARCH64_OPND_QLF_V_4H
,
495 AARCH64_OPND_QLF_V_8H
,
496 AARCH64_OPND_QLF_V_2S
,
497 AARCH64_OPND_QLF_V_4S
,
498 AARCH64_OPND_QLF_V_1D
,
499 AARCH64_OPND_QLF_V_2D
,
500 AARCH64_OPND_QLF_V_1Q
,
502 AARCH64_OPND_QLF_P_Z
,
503 AARCH64_OPND_QLF_P_M
,
505 /* Used in scaled signed immediate that are scaled by a Tag granule
506 like in stg, st2g, etc. */
507 AARCH64_OPND_QLF_imm_tag
,
509 /* Constraint on value. */
510 AARCH64_OPND_QLF_CR
, /* CRn, CRm. */
511 AARCH64_OPND_QLF_imm_0_7
,
512 AARCH64_OPND_QLF_imm_0_15
,
513 AARCH64_OPND_QLF_imm_0_31
,
514 AARCH64_OPND_QLF_imm_0_63
,
515 AARCH64_OPND_QLF_imm_1_32
,
516 AARCH64_OPND_QLF_imm_1_64
,
518 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
520 AARCH64_OPND_QLF_LSL
,
521 AARCH64_OPND_QLF_MSL
,
523 /* Special qualifier helping retrieve qualifier information during the
524 decoding time (currently not in use). */
525 AARCH64_OPND_QLF_RETRIEVE
,
528 /* Instruction class. */
530 enum aarch64_insn_class
586 ldst_imm9
, /* immpost or immpre */
587 ldst_imm10
, /* LDRAA/LDRAB */
629 /* Opcode enumerators. */
673 OP_MOV_IMM_LOG
, /* MOV alias for moving bitmask immediate. */
674 OP_MOV_IMM_WIDE
, /* MOV alias for moving wide immediate. */
675 OP_MOV_IMM_WIDEN
, /* MOV alias for moving wide immediate (negated). */
677 OP_MOV_V
, /* MOV alias for moving vector register. */
690 OP_BFC
, /* ARMv8.2. */
707 OP_FCVTXN_S
, /* Scalar version. */
728 OP_FCMLA_ELEM
, /* ARMv8.3, indexed element version. */
730 OP_TOTAL_NUM
, /* Pseudo. */
744 /* Maximum number of operands an instruction can have. */
745 #define AARCH64_MAX_OPND_NUM 6
746 /* Maximum number of qualifier sequences an instruction can have. */
747 #define AARCH64_MAX_QLF_SEQ_NUM 10
748 /* Operand qualifier typedef; optimized for the size. */
749 typedef unsigned char aarch64_opnd_qualifier_t
;
750 /* Operand qualifier sequence typedef. */
751 typedef aarch64_opnd_qualifier_t \
752 aarch64_opnd_qualifier_seq_t
[AARCH64_MAX_OPND_NUM
];
754 /* FIXME: improve the efficiency. */
755 static inline bfd_boolean
756 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t
*qualifiers
)
759 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
760 if (qualifiers
[i
] != AARCH64_OPND_QLF_NIL
)
765 /* Forward declare error reporting type. */
766 typedef struct aarch64_operand_error aarch64_operand_error
;
767 /* Forward declare instruction sequence type. */
768 typedef struct aarch64_instr_sequence aarch64_instr_sequence
;
769 /* Forward declare instruction definition. */
770 typedef struct aarch64_inst aarch64_inst
;
772 /* This structure holds information for a particular opcode. */
774 struct aarch64_opcode
776 /* The name of the mnemonic. */
779 /* The opcode itself. Those bits which will be filled in with
780 operands are zeroes. */
783 /* The opcode mask. This is used by the disassembler. This is a
784 mask containing ones indicating those bits which must match the
785 opcode field, and zeroes indicating those bits which need not
786 match (and are presumably filled in by operands). */
789 /* Instruction class. */
790 enum aarch64_insn_class iclass
;
792 /* Enumerator identifier. */
795 /* Which architecture variant provides this instruction. */
796 const aarch64_feature_set
*avariant
;
798 /* An array of operand codes. Each code is an index into the
799 operand table. They appear in the order which the operands must
800 appear in assembly code, and are terminated by a zero. */
801 enum aarch64_opnd operands
[AARCH64_MAX_OPND_NUM
];
803 /* A list of operand qualifier code sequence. Each operand qualifier
804 code qualifies the corresponding operand code. Each operand
805 qualifier sequence specifies a valid opcode variant and related
806 constraint on operands. */
807 aarch64_opnd_qualifier_seq_t qualifiers_list
[AARCH64_MAX_QLF_SEQ_NUM
];
809 /* Flags providing information about this instruction */
812 /* Extra constraints on the instruction that the verifier checks. */
813 uint32_t constraints
;
815 /* If nonzero, this operand and operand 0 are both registers and
816 are required to have the same register number. */
817 unsigned char tied_operand
;
819 /* If non-NULL, a function to verify that a given instruction is valid. */
820 enum err_type (* verifier
) (const struct aarch64_inst
*, const aarch64_insn
,
821 bfd_vma
, bfd_boolean
, aarch64_operand_error
*,
822 struct aarch64_instr_sequence
*);
825 typedef struct aarch64_opcode aarch64_opcode
;
827 /* Table describing all the AArch64 opcodes. */
828 extern aarch64_opcode aarch64_opcode_table
[];
831 #define F_ALIAS (1 << 0)
832 #define F_HAS_ALIAS (1 << 1)
833 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
834 is specified, it is the priority 0 by default, i.e. the lowest priority. */
835 #define F_P1 (1 << 2)
836 #define F_P2 (2 << 2)
837 #define F_P3 (3 << 2)
838 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
839 #define F_COND (1 << 4)
840 /* Instruction has the field of 'sf'. */
841 #define F_SF (1 << 5)
842 /* Instruction has the field of 'size:Q'. */
843 #define F_SIZEQ (1 << 6)
844 /* Floating-point instruction has the field of 'type'. */
845 #define F_FPTYPE (1 << 7)
846 /* AdvSIMD scalar instruction has the field of 'size'. */
847 #define F_SSIZE (1 << 8)
848 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
850 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
851 #define F_GPRSIZE_IN_Q (1 << 10)
852 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
853 #define F_LDS_SIZE (1 << 11)
854 /* Optional operand; assume maximum of 1 operand can be optional. */
855 #define F_OPD0_OPT (1 << 12)
856 #define F_OPD1_OPT (2 << 12)
857 #define F_OPD2_OPT (3 << 12)
858 #define F_OPD3_OPT (4 << 12)
859 #define F_OPD4_OPT (5 << 12)
860 /* Default value for the optional operand when omitted from the assembly. */
861 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
862 /* Instruction that is an alias of another instruction needs to be
863 encoded/decoded by converting it to/from the real form, followed by
864 the encoding/decoding according to the rules of the real opcode.
865 This compares to the direct coding using the alias's information.
866 N.B. this flag requires F_ALIAS to be used together. */
867 #define F_CONV (1 << 20)
868 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
869 friendly pseudo instruction available only in the assembly code (thus will
870 not show up in the disassembly). */
871 #define F_PSEUDO (1 << 21)
872 /* Instruction has miscellaneous encoding/decoding rules. */
873 #define F_MISC (1 << 22)
874 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
875 #define F_N (1 << 23)
876 /* Opcode dependent field. */
877 #define F_OD(X) (((X) & 0x7) << 24)
878 /* Instruction has the field of 'sz'. */
879 #define F_LSE_SZ (1 << 27)
880 /* Require an exact qualifier match, even for NIL qualifiers. */
881 #define F_STRICT (1ULL << 28)
882 /* This system instruction is used to read system registers. */
883 #define F_SYS_READ (1ULL << 29)
884 /* This system instruction is used to write system registers. */
885 #define F_SYS_WRITE (1ULL << 30)
886 /* This instruction has an extra constraint on it that imposes a requirement on
887 subsequent instructions. */
888 #define F_SCAN (1ULL << 31)
889 /* Next bit is 32. */
891 /* Instruction constraints. */
892 /* This instruction has a predication constraint on the instruction at PC+4. */
893 #define C_SCAN_MOVPRFX (1U << 0)
894 /* This instruction's operation width is determined by the operand with the
895 largest element size. */
896 #define C_MAX_ELEM (1U << 1)
899 static inline bfd_boolean
900 alias_opcode_p (const aarch64_opcode
*opcode
)
902 return (opcode
->flags
& F_ALIAS
) ? TRUE
: FALSE
;
905 static inline bfd_boolean
906 opcode_has_alias (const aarch64_opcode
*opcode
)
908 return (opcode
->flags
& F_HAS_ALIAS
) ? TRUE
: FALSE
;
911 /* Priority for disassembling preference. */
913 opcode_priority (const aarch64_opcode
*opcode
)
915 return (opcode
->flags
>> 2) & 0x3;
918 static inline bfd_boolean
919 pseudo_opcode_p (const aarch64_opcode
*opcode
)
921 return (opcode
->flags
& F_PSEUDO
) != 0lu ? TRUE
: FALSE
;
924 static inline bfd_boolean
925 optional_operand_p (const aarch64_opcode
*opcode
, unsigned int idx
)
927 return (((opcode
->flags
>> 12) & 0x7) == idx
+ 1)
931 static inline aarch64_insn
932 get_optional_operand_default_value (const aarch64_opcode
*opcode
)
934 return (opcode
->flags
>> 15) & 0x1f;
937 static inline unsigned int
938 get_opcode_dependent_value (const aarch64_opcode
*opcode
)
940 return (opcode
->flags
>> 24) & 0x7;
943 static inline bfd_boolean
944 opcode_has_special_coder (const aarch64_opcode
*opcode
)
946 return (opcode
->flags
& (F_SF
| F_LSE_SZ
| F_SIZEQ
| F_FPTYPE
| F_SSIZE
| F_T
947 | F_GPRSIZE_IN_Q
| F_LDS_SIZE
| F_MISC
| F_N
| F_COND
)) ? TRUE
951 struct aarch64_name_value_pair
957 extern const struct aarch64_name_value_pair aarch64_operand_modifiers
[];
958 extern const struct aarch64_name_value_pair aarch64_barrier_options
[16];
959 extern const struct aarch64_name_value_pair aarch64_prfops
[32];
960 extern const struct aarch64_name_value_pair aarch64_hint_options
[];
969 extern const aarch64_sys_reg aarch64_sys_regs
[];
970 extern const aarch64_sys_reg aarch64_pstatefields
[];
971 extern bfd_boolean
aarch64_sys_reg_deprecated_p (const aarch64_sys_reg
*);
972 extern bfd_boolean
aarch64_sys_reg_supported_p (const aarch64_feature_set
,
973 const aarch64_sys_reg
*);
974 extern bfd_boolean
aarch64_pstatefield_supported_p (const aarch64_feature_set
,
975 const aarch64_sys_reg
*);
982 } aarch64_sys_ins_reg
;
984 extern bfd_boolean
aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg
*);
986 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set
,
987 const aarch64_sys_ins_reg
*);
989 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic
[];
990 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc
[];
991 extern const aarch64_sys_ins_reg aarch64_sys_regs_at
[];
992 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi
[];
993 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr
[];
995 /* Shift/extending operator kinds.
996 N.B. order is important; keep aarch64_operand_modifiers synced. */
997 enum aarch64_modifier_kind
1018 aarch64_extend_operator_p (enum aarch64_modifier_kind
);
1020 enum aarch64_modifier_kind
1021 aarch64_get_operand_modifier (const struct aarch64_name_value_pair
*);
1026 /* A list of names with the first one as the disassembly preference;
1027 terminated by NULL if fewer than 3. */
1028 const char *names
[4];
1032 extern const aarch64_cond aarch64_conds
[16];
1034 const aarch64_cond
* get_cond_from_value (aarch64_insn value
);
1035 const aarch64_cond
* get_inverted_cond (const aarch64_cond
*cond
);
1037 /* Structure representing an operand. */
1039 struct aarch64_opnd_info
1041 enum aarch64_opnd type
;
1042 aarch64_opnd_qualifier_t qualifier
;
1059 unsigned first_regno
: 5;
1060 unsigned num_regs
: 3;
1061 /* 1 if it is a list of reg element. */
1062 unsigned has_index
: 1;
1063 /* Lane index; valid only when has_index is 1. */
1066 /* e.g. immediate or pc relative address offset. */
1072 /* e.g. address in STR (register offset). */
1075 unsigned base_regno
;
1085 unsigned pcrel
: 1; /* PC-relative. */
1086 unsigned writeback
: 1;
1087 unsigned preind
: 1; /* Pre-indexed. */
1088 unsigned postind
: 1; /* Post-indexed. */
1093 /* The encoding of the system register. */
1096 /* The system register flags. */
1100 const aarch64_cond
*cond
;
1101 /* The encoding of the PSTATE field. */
1102 aarch64_insn pstatefield
;
1103 const aarch64_sys_ins_reg
*sysins_op
;
1104 const struct aarch64_name_value_pair
*barrier
;
1105 const struct aarch64_name_value_pair
*hint_option
;
1106 const struct aarch64_name_value_pair
*prfop
;
1109 /* Operand shifter; in use when the operand is a register offset address,
1110 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1113 enum aarch64_modifier_kind kind
;
1114 unsigned operator_present
: 1; /* Only valid during encoding. */
1115 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1116 unsigned amount_present
: 1;
1120 unsigned skip
:1; /* Operand is not completed if there is a fixup needed
1121 to be done on it. In some (but not all) of these
1122 cases, we need to tell libopcodes to skip the
1123 constraint checking and the encoding for this
1124 operand, so that the libopcodes can pick up the
1125 right opcode before the operand is fixed-up. This
1126 flag should only be used during the
1127 assembling/encoding. */
1128 unsigned present
:1; /* Whether this operand is present in the assembly
1129 line; not used during the disassembly. */
1132 typedef struct aarch64_opnd_info aarch64_opnd_info
;
1134 /* Structure representing an instruction.
1136 It is used during both the assembling and disassembling. The assembler
1137 fills an aarch64_inst after a successful parsing and then passes it to the
1138 encoding routine to do the encoding. During the disassembling, the
1139 disassembler calls the decoding routine to decode a binary instruction; on a
1140 successful return, such a structure will be filled with information of the
1141 instruction; then the disassembler uses the information to print out the
1146 /* The value of the binary instruction. */
1149 /* Corresponding opcode entry. */
1150 const aarch64_opcode
*opcode
;
1152 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1153 const aarch64_cond
*cond
;
1155 /* Operands information. */
1156 aarch64_opnd_info operands
[AARCH64_MAX_OPND_NUM
];
1159 /* Defining the HINT #imm values for the aarch64_hint_options. */
1160 #define HINT_OPD_CSYNC 0x11
1161 #define HINT_OPD_C 0x22
1162 #define HINT_OPD_J 0x24
1163 #define HINT_OPD_JC 0x26
1164 #define HINT_OPD_NULL 0x00
1167 /* Diagnosis related declaration and interface. */
1169 /* Operand error kind enumerators.
1171 AARCH64_OPDE_RECOVERABLE
1172 Less severe error found during the parsing, very possibly because that
1173 GAS has picked up a wrong instruction template for the parsing.
1175 AARCH64_OPDE_SYNTAX_ERROR
1176 General syntax error; it can be either a user error, or simply because
1177 that GAS is trying a wrong instruction template.
1179 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1180 Definitely a user syntax error.
1182 AARCH64_OPDE_INVALID_VARIANT
1183 No syntax error, but the operands are not a valid combination, e.g.
1186 AARCH64_OPDE_UNTIED_OPERAND
1187 The asm failed to use the same register for a destination operand
1188 and a tied source operand.
1190 AARCH64_OPDE_OUT_OF_RANGE
1191 Error about some immediate value out of a valid range.
1193 AARCH64_OPDE_UNALIGNED
1194 Error about some immediate value not properly aligned (i.e. not being a
1195 multiple times of a certain value).
1197 AARCH64_OPDE_REG_LIST
1198 Error about the register list operand having unexpected number of
1201 AARCH64_OPDE_OTHER_ERROR
1202 Error of the highest severity and used for any severe issue that does not
1203 fall into any of the above categories.
1205 The enumerators are only interesting to GAS. They are declared here (in
1206 libopcodes) because that some errors are detected (and then notified to GAS)
1207 by libopcodes (rather than by GAS solely).
1209 The first three errors are only deteced by GAS while the
1210 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1211 only libopcodes has the information about the valid variants of each
1214 The enumerators have an increasing severity. This is helpful when there are
1215 multiple instruction templates available for a given mnemonic name (e.g.
1216 FMOV); this mechanism will help choose the most suitable template from which
1217 the generated diagnostics can most closely describe the issues, if any. */
1219 enum aarch64_operand_error_kind
1222 AARCH64_OPDE_RECOVERABLE
,
1223 AARCH64_OPDE_SYNTAX_ERROR
,
1224 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
1225 AARCH64_OPDE_INVALID_VARIANT
,
1226 AARCH64_OPDE_UNTIED_OPERAND
,
1227 AARCH64_OPDE_OUT_OF_RANGE
,
1228 AARCH64_OPDE_UNALIGNED
,
1229 AARCH64_OPDE_REG_LIST
,
1230 AARCH64_OPDE_OTHER_ERROR
1233 /* N.B. GAS assumes that this structure work well with shallow copy. */
1234 struct aarch64_operand_error
1236 enum aarch64_operand_error_kind kind
;
1239 int data
[3]; /* Some data for extra information. */
1240 bfd_boolean non_fatal
;
1243 /* AArch64 sequence structure used to track instructions with F_SCAN
1244 dependencies for both assembler and disassembler. */
1245 struct aarch64_instr_sequence
1247 /* The instruction that caused this sequence to be opened. */
1248 aarch64_inst
*instr
;
1249 /* The number of instructions the above instruction allows to be kept in the
1250 sequence before an automatic close is done. */
1252 /* The instructions currently added to the sequence. */
1253 aarch64_inst
**current_insns
;
1254 /* The number of instructions already in the sequence. */
1258 /* Encoding entrypoint. */
1261 aarch64_opcode_encode (const aarch64_opcode
*, const aarch64_inst
*,
1262 aarch64_insn
*, aarch64_opnd_qualifier_t
*,
1263 aarch64_operand_error
*, aarch64_instr_sequence
*);
1265 extern const aarch64_opcode
*
1266 aarch64_replace_opcode (struct aarch64_inst
*,
1267 const aarch64_opcode
*);
1269 /* Given the opcode enumerator OP, return the pointer to the corresponding
1272 extern const aarch64_opcode
*
1273 aarch64_get_opcode (enum aarch64_op
);
1275 /* Generate the string representation of an operand. */
1277 aarch64_print_operand (char *, size_t, bfd_vma
, const aarch64_opcode
*,
1278 const aarch64_opnd_info
*, int, int *, bfd_vma
*,
1281 /* Miscellaneous interface. */
1284 aarch64_operand_index (const enum aarch64_opnd
*, enum aarch64_opnd
);
1286 extern aarch64_opnd_qualifier_t
1287 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t
*, int,
1288 const aarch64_opnd_qualifier_t
, int);
1291 aarch64_is_destructive_by_operands (const aarch64_opcode
*);
1294 aarch64_num_of_operands (const aarch64_opcode
*);
1297 aarch64_stack_pointer_p (const aarch64_opnd_info
*);
1300 aarch64_zero_register_p (const aarch64_opnd_info
*);
1302 extern enum err_type
1303 aarch64_decode_insn (aarch64_insn
, aarch64_inst
*, bfd_boolean
,
1304 aarch64_operand_error
*);
1307 init_insn_sequence (const struct aarch64_inst
*, aarch64_instr_sequence
*);
1309 /* Given an operand qualifier, return the expected data element size
1310 of a qualified operand. */
1311 extern unsigned char
1312 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t
);
1314 extern enum aarch64_operand_class
1315 aarch64_get_operand_class (enum aarch64_opnd
);
1318 aarch64_get_operand_name (enum aarch64_opnd
);
1321 aarch64_get_operand_desc (enum aarch64_opnd
);
1324 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1326 #ifdef DEBUG_AARCH64
1327 extern int debug_dump
;
1330 aarch64_verbose (const char *, ...) __attribute__ ((format (printf
, 1, 2)));
1332 #define DEBUG_TRACE(M, ...) \
1335 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1338 #define DEBUG_TRACE_IF(C, M, ...) \
1340 if (debug_dump && (C)) \
1341 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1343 #else /* !DEBUG_AARCH64 */
1344 #define DEBUG_TRACE(M, ...) ;
1345 #define DEBUG_TRACE_IF(C, M, ...) ;
1346 #endif /* DEBUG_AARCH64 */
1348 extern const char *const aarch64_sve_pattern_array
[32];
1349 extern const char *const aarch64_sve_prfop_array
[16];
1355 #endif /* OPCODE_AARCH64_H */