include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Flag Manipulation insns.  */
  68 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  69 /* FRINT[32,64][Z,X] insns.  */
  70 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  71 /* SB instruction.  */
  72 #define AARCH64_FEATURE_SB              0x10000000000ULL
  73
  74 /* Architectures are the sum of the base and extensions.  */
  75 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  76                                                  AARCH64_FEATURE_FP  \
  77                                                  | AARCH64_FEATURE_SIMD)
  78 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  79                                                  AARCH64_FEATURE_CRC    \
  80                                                  | AARCH64_FEATURE_V8_1 \
  81                                                  | AARCH64_FEATURE_LSE  \
  82                                                  | AARCH64_FEATURE_PAN  \
  83                                                  | AARCH64_FEATURE_LOR  \
  84                                                  | AARCH64_FEATURE_RDMA)
  85 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  86                                                  AARCH64_FEATURE_V8_2   \
  87                                                  | AARCH64_FEATURE_RAS)
  88 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  89                                                  AARCH64_FEATURE_V8_3   \
  90                                                  | AARCH64_FEATURE_RCPC \
  91                                                  | AARCH64_FEATURE_COMPNUM)
  92 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
  93                                                  AARCH64_FEATURE_V8_4   \
  94                                                  | AARCH64_FEATURE_DOTPROD \
  95                                                  | AARCH64_FEATURE_F16_FML)
  96 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
  97                                                  AARCH64_FEATURE_V8_5   \
  98                                                  | AARCH64_FEATURE_FLAGMANIP \
  99                                                  | AARCH64_FEATURE_FRINTTS \
 100                                                  | AARCH64_FEATURE_SB)
 101
 102
 103 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 104 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 105
 106 /* CPU-specific features.  */
 107 typedef unsigned long long aarch64_feature_set;
 108
 109 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 110   ((~(CPU) & (FEAT)) == 0)
 111
 112 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 113   (((CPU) & (FEAT)) != 0)
 114
 115 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 116   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 117
 118 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 119   do                                            \
 120     {                                           \
 121       (TARG) = (F1) | (F2);                     \
 122     }                                           \
 123   while (0)
 124
 125 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 126   do                                            \
 127     {                                           \
 128       (TARG) = (F1) &~ (F2);                    \
 129     }                                           \
 130   while (0)
 131
 132 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 133
 134 enum aarch64_operand_class
 135 {
 136   AARCH64_OPND_CLASS_NIL,
 137   AARCH64_OPND_CLASS_INT_REG,
 138   AARCH64_OPND_CLASS_MODIFIED_REG,
 139   AARCH64_OPND_CLASS_FP_REG,
 140   AARCH64_OPND_CLASS_SIMD_REG,
 141   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 142   AARCH64_OPND_CLASS_SISD_REG,
 143   AARCH64_OPND_CLASS_SIMD_REGLIST,
 144   AARCH64_OPND_CLASS_SVE_REG,
 145   AARCH64_OPND_CLASS_PRED_REG,
 146   AARCH64_OPND_CLASS_ADDRESS,
 147   AARCH64_OPND_CLASS_IMMEDIATE,
 148   AARCH64_OPND_CLASS_SYSTEM,
 149   AARCH64_OPND_CLASS_COND,
 150 };
 151
 152 /* Operand code that helps both parsing and coding.
 153    Keep AARCH64_OPERANDS synced.  */
 154
 155 enum aarch64_opnd
 156 {
 157   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 158
 159   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 160   AARCH64_OPND_Rn,      /* Integer register as source.  */
 161   AARCH64_OPND_Rm,      /* Integer register as source.  */
 162   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 163   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 164   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 165   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 166   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 167
 168   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 169   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 170   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 171   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 172   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 173   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 174
 175   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 176   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 177   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 178   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 179   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 180   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 181
 182   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 183   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 184   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 185
 186   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 187   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 188   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 189   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 190   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 191   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 192   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 193   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 194   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 195   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 196                            qualifier is S_H.  */
 197   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 198   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 199   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 200                            structure to all lanes.  */
 201   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 202
 203   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 204   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 205
 206   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 207   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 208   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 209   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 210   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 211   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 212   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 213   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 214                            (no encoding).  */
 215   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 216   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 217   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 218   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 219   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 220   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 221   AARCH64_OPND_IMM,     /* Immediate.  */
 222   AARCH64_OPND_IMM_2,   /* Immediate.  */
 223   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 224   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 225   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 226   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 227   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 228   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 229   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 230   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 231   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 232                            each condition flag.  */
 233
 234   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 235   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 236   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 237   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 238   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 239   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 240   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 241   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 242
 243   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 244   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 245
 246   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 247   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 248   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 249   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 250   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 251
 252   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 253   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 254   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 255   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 256   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 257                                    negative or unaligned and there is
 258                                    no writeback allowed.  This operand code
 259                                    is only used to support the programmer-
 260                                    friendly feature of using LDR/STR as the
 261                                    the mnemonic name for LDUR/STUR instructions
 262                                    wherever there is no ambiguity.  */
 263   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 264   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 265   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 266   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 267   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 268
 269   AARCH64_OPND_SYSREG,          /* System register operand.  */
 270   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 271   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 272   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 273   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 274   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 275   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 276   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 277   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 278   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 279
 280   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 281   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 282   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 283   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 284   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 285   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 286   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 287   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 288   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 289   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 290   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 291   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 292   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 293   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 294   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 295   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 296   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 297   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 298   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 299   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 300   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 301   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 302   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 303   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 304   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 305                                        Bit 14 controls S/U choice.  */
 306   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 307                                        Bit 22 controls S/U choice.  */
 308   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 309                                        Bit 14 controls S/U choice.  */
 310   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 311                                        Bit 22 controls S/U choice.  */
 312   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 313                                        Bit 14 controls S/U choice.  */
 314   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 315                                        Bit 22 controls S/U choice.  */
 316   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 317                                        Bit 14 controls S/U choice.  */
 318   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 319                                        Bit 22 controls S/U choice.  */
 320   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 321   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 322   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 323   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 324   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 325   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 326   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 327   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 328   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 329   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 330   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 331   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 332   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 333   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 334   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 335   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 336   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 337   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 338   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 339   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 340   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 341   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 342   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 343   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 344   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 345   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 346   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 347   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 348   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 349   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 350   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 351   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 352   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 353   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 354   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 355   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 356   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 357   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 358   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 359   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 360   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 361   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 362   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 363   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 364   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 365   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 366   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 367   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 368   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 369   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 370   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 371   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 372   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 373   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 374   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 375   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 376   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 377   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 378   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 379   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 380   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 381 };
 382
 383 /* Qualifier constrains an operand.  It either specifies a variant of an
 384    operand type or limits values available to an operand type.
 385
 386    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 387
 388 enum aarch64_opnd_qualifier
 389 {
 390   /* Indicating no further qualification on an operand.  */
 391   AARCH64_OPND_QLF_NIL,
 392
 393   /* Qualifying an operand which is a general purpose (integer) register;
 394      indicating the operand data size or a specific register.  */
 395   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 396   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 397   AARCH64_OPND_QLF_WSP, /* WSP.  */
 398   AARCH64_OPND_QLF_SP,  /* SP.  */
 399
 400   /* Qualifying an operand which is a floating-point register, a SIMD
 401      vector element or a SIMD vector element list; indicating operand data
 402      size or the size of each SIMD vector element in the case of a SIMD
 403      vector element list.
 404      These qualifiers are also used to qualify an address operand to
 405      indicate the size of data element a load/store instruction is
 406      accessing.
 407      They are also used for the immediate shift operand in e.g. SSHR.  Such
 408      a use is only for the ease of operand encoding/decoding and qualifier
 409      sequence matching; such a use should not be applied widely; use the value
 410      constraint qualifiers for immediate operands wherever possible.  */
 411   AARCH64_OPND_QLF_S_B,
 412   AARCH64_OPND_QLF_S_H,
 413   AARCH64_OPND_QLF_S_S,
 414   AARCH64_OPND_QLF_S_D,
 415   AARCH64_OPND_QLF_S_Q,
 416   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 417      are selected by the instruction.  Other than that it has no difference
 418      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 419      reasons and is an exception from normal AArch64 disassembly scheme.  */
 420   AARCH64_OPND_QLF_S_4B,
 421
 422   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 423      register list; indicating register shape.
 424      They are also used for the immediate shift operand in e.g. SSHR.  Such
 425      a use is only for the ease of operand encoding/decoding and qualifier
 426      sequence matching; such a use should not be applied widely; use the value
 427      constraint qualifiers for immediate operands wherever possible.  */
 428   AARCH64_OPND_QLF_V_4B,
 429   AARCH64_OPND_QLF_V_8B,
 430   AARCH64_OPND_QLF_V_16B,
 431   AARCH64_OPND_QLF_V_2H,
 432   AARCH64_OPND_QLF_V_4H,
 433   AARCH64_OPND_QLF_V_8H,
 434   AARCH64_OPND_QLF_V_2S,
 435   AARCH64_OPND_QLF_V_4S,
 436   AARCH64_OPND_QLF_V_1D,
 437   AARCH64_OPND_QLF_V_2D,
 438   AARCH64_OPND_QLF_V_1Q,
 439
 440   AARCH64_OPND_QLF_P_Z,
 441   AARCH64_OPND_QLF_P_M,
 442
 443   /* Constraint on value.  */
 444   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 445   AARCH64_OPND_QLF_imm_0_7,
 446   AARCH64_OPND_QLF_imm_0_15,
 447   AARCH64_OPND_QLF_imm_0_31,
 448   AARCH64_OPND_QLF_imm_0_63,
 449   AARCH64_OPND_QLF_imm_1_32,
 450   AARCH64_OPND_QLF_imm_1_64,
 451
 452   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 453      or shift-ones.  */
 454   AARCH64_OPND_QLF_LSL,
 455   AARCH64_OPND_QLF_MSL,
 456
 457   /* Special qualifier helping retrieve qualifier information during the
 458      decoding time (currently not in use).  */
 459   AARCH64_OPND_QLF_RETRIEVE,
 460 };
 461 \f
 462 /* Instruction class.  */
 463
 464 enum aarch64_insn_class
 465 {
 466   addsub_carry,
 467   addsub_ext,
 468   addsub_imm,
 469   addsub_shift,
 470   asimdall,
 471   asimddiff,
 472   asimdelem,
 473   asimdext,
 474   asimdimm,
 475   asimdins,
 476   asimdmisc,
 477   asimdperm,
 478   asimdsame,
 479   asimdshf,
 480   asimdtbl,
 481   asisddiff,
 482   asisdelem,
 483   asisdlse,
 484   asisdlsep,
 485   asisdlso,
 486   asisdlsop,
 487   asisdmisc,
 488   asisdone,
 489   asisdpair,
 490   asisdsame,
 491   asisdshf,
 492   bitfield,
 493   branch_imm,
 494   branch_reg,
 495   compbranch,
 496   condbranch,
 497   condcmp_imm,
 498   condcmp_reg,
 499   condsel,
 500   cryptoaes,
 501   cryptosha2,
 502   cryptosha3,
 503   dp_1src,
 504   dp_2src,
 505   dp_3src,
 506   exception,
 507   extract,
 508   float2fix,
 509   float2int,
 510   floatccmp,
 511   floatcmp,
 512   floatdp1,
 513   floatdp2,
 514   floatdp3,
 515   floatimm,
 516   floatsel,
 517   ldst_immpost,
 518   ldst_immpre,
 519   ldst_imm9,    /* immpost or immpre */
 520   ldst_imm10,   /* LDRAA/LDRAB */
 521   ldst_pos,
 522   ldst_regoff,
 523   ldst_unpriv,
 524   ldst_unscaled,
 525   ldstexcl,
 526   ldstnapair_offs,
 527   ldstpair_off,
 528   ldstpair_indexed,
 529   loadlit,
 530   log_imm,
 531   log_shift,
 532   lse_atomic,
 533   movewide,
 534   pcreladdr,
 535   ic_system,
 536   sve_cpy,
 537   sve_index,
 538   sve_limm,
 539   sve_misc,
 540   sve_movprfx,
 541   sve_pred_zm,
 542   sve_shift_pred,
 543   sve_shift_unpred,
 544   sve_size_bhs,
 545   sve_size_bhsd,
 546   sve_size_hsd,
 547   sve_size_sd,
 548   testbranch,
 549   cryptosm3,
 550   cryptosm4,
 551   dotproduct,
 552 };
 553
 554 /* Opcode enumerators.  */
 555
 556 enum aarch64_op
 557 {
 558   OP_NIL,
 559   OP_STRB_POS,
 560   OP_LDRB_POS,
 561   OP_LDRSB_POS,
 562   OP_STRH_POS,
 563   OP_LDRH_POS,
 564   OP_LDRSH_POS,
 565   OP_STR_POS,
 566   OP_LDR_POS,
 567   OP_STRF_POS,
 568   OP_LDRF_POS,
 569   OP_LDRSW_POS,
 570   OP_PRFM_POS,
 571
 572   OP_STURB,
 573   OP_LDURB,
 574   OP_LDURSB,
 575   OP_STURH,
 576   OP_LDURH,
 577   OP_LDURSH,
 578   OP_STUR,
 579   OP_LDUR,
 580   OP_STURV,
 581   OP_LDURV,
 582   OP_LDURSW,
 583   OP_PRFUM,
 584
 585   OP_LDR_LIT,
 586   OP_LDRV_LIT,
 587   OP_LDRSW_LIT,
 588   OP_PRFM_LIT,
 589
 590   OP_ADD,
 591   OP_B,
 592   OP_BL,
 593
 594   OP_MOVN,
 595   OP_MOVZ,
 596   OP_MOVK,
 597
 598   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 599   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 600   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 601
 602   OP_MOV_V,             /* MOV alias for moving vector register.  */
 603
 604   OP_ASR_IMM,
 605   OP_LSR_IMM,
 606   OP_LSL_IMM,
 607
 608   OP_BIC,
 609
 610   OP_UBFX,
 611   OP_BFXIL,
 612   OP_SBFX,
 613   OP_SBFIZ,
 614   OP_BFI,
 615   OP_BFC,               /* ARMv8.2.  */
 616   OP_UBFIZ,
 617   OP_UXTB,
 618   OP_UXTH,
 619   OP_UXTW,
 620
 621   OP_CINC,
 622   OP_CINV,
 623   OP_CNEG,
 624   OP_CSET,
 625   OP_CSETM,
 626
 627   OP_FCVT,
 628   OP_FCVTN,
 629   OP_FCVTN2,
 630   OP_FCVTL,
 631   OP_FCVTL2,
 632   OP_FCVTXN_S,          /* Scalar version.  */
 633
 634   OP_ROR_IMM,
 635
 636   OP_SXTL,
 637   OP_SXTL2,
 638   OP_UXTL,
 639   OP_UXTL2,
 640
 641   OP_MOV_P_P,
 642   OP_MOV_Z_P_Z,
 643   OP_MOV_Z_V,
 644   OP_MOV_Z_Z,
 645   OP_MOV_Z_Zi,
 646   OP_MOVM_P_P_P,
 647   OP_MOVS_P_P,
 648   OP_MOVZS_P_P_P,
 649   OP_MOVZ_P_P_P,
 650   OP_NOTS_P_P_P_Z,
 651   OP_NOT_P_P_P_Z,
 652
 653   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 654
 655   OP_TOTAL_NUM,         /* Pseudo.  */
 656 };
 657
 658 /* Error types.  */
 659 enum err_type
 660 {
 661   ERR_OK,
 662   ERR_UND,
 663   ERR_UNP,
 664   ERR_NYI,
 665   ERR_VFI,
 666   ERR_NR_ENTRIES
 667 };
 668
 669 /* Maximum number of operands an instruction can have.  */
 670 #define AARCH64_MAX_OPND_NUM 6
 671 /* Maximum number of qualifier sequences an instruction can have.  */
 672 #define AARCH64_MAX_QLF_SEQ_NUM 10
 673 /* Operand qualifier typedef; optimized for the size.  */
 674 typedef unsigned char aarch64_opnd_qualifier_t;
 675 /* Operand qualifier sequence typedef.  */
 676 typedef aarch64_opnd_qualifier_t        \
 677           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 678
 679 /* FIXME: improve the efficiency.  */
 680 static inline bfd_boolean
 681 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 682 {
 683   int i;
 684   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 685     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 686       return FALSE;
 687   return TRUE;
 688 }
 689
 690 /*  Forward declare error reporting type.  */
 691 typedef struct aarch64_operand_error aarch64_operand_error;
 692 /* Forward declare instruction sequence type.  */
 693 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 694 /* Forward declare instruction definition.  */
 695 typedef struct aarch64_inst aarch64_inst;
 696
 697 /* This structure holds information for a particular opcode.  */
 698
 699 struct aarch64_opcode
 700 {
 701   /* The name of the mnemonic.  */
 702   const char *name;
 703
 704   /* The opcode itself.  Those bits which will be filled in with
 705      operands are zeroes.  */
 706   aarch64_insn opcode;
 707
 708   /* The opcode mask.  This is used by the disassembler.  This is a
 709      mask containing ones indicating those bits which must match the
 710      opcode field, and zeroes indicating those bits which need not
 711      match (and are presumably filled in by operands).  */
 712   aarch64_insn mask;
 713
 714   /* Instruction class.  */
 715   enum aarch64_insn_class iclass;
 716
 717   /* Enumerator identifier.  */
 718   enum aarch64_op op;
 719
 720   /* Which architecture variant provides this instruction.  */
 721   const aarch64_feature_set *avariant;
 722
 723   /* An array of operand codes.  Each code is an index into the
 724      operand table.  They appear in the order which the operands must
 725      appear in assembly code, and are terminated by a zero.  */
 726   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 727
 728   /* A list of operand qualifier code sequence.  Each operand qualifier
 729      code qualifies the corresponding operand code.  Each operand
 730      qualifier sequence specifies a valid opcode variant and related
 731      constraint on operands.  */
 732   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 733
 734   /* Flags providing information about this instruction */
 735   uint64_t flags;
 736
 737   /* Extra constraints on the instruction that the verifier checks.  */
 738   uint32_t constraints;
 739
 740   /* If nonzero, this operand and operand 0 are both registers and
 741      are required to have the same register number.  */
 742   unsigned char tied_operand;
 743
 744   /* If non-NULL, a function to verify that a given instruction is valid.  */
 745   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 746                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 747                               struct aarch64_instr_sequence *);
 748 };
 749
 750 typedef struct aarch64_opcode aarch64_opcode;
 751
 752 /* Table describing all the AArch64 opcodes.  */
 753 extern aarch64_opcode aarch64_opcode_table[];
 754
 755 /* Opcode flags.  */
 756 #define F_ALIAS (1 << 0)
 757 #define F_HAS_ALIAS (1 << 1)
 758 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 759    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 760 #define F_P1 (1 << 2)
 761 #define F_P2 (2 << 2)
 762 #define F_P3 (3 << 2)
 763 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 764 #define F_COND (1 << 4)
 765 /* Instruction has the field of 'sf'.  */
 766 #define F_SF (1 << 5)
 767 /* Instruction has the field of 'size:Q'.  */
 768 #define F_SIZEQ (1 << 6)
 769 /* Floating-point instruction has the field of 'type'.  */
 770 #define F_FPTYPE (1 << 7)
 771 /* AdvSIMD scalar instruction has the field of 'size'.  */
 772 #define F_SSIZE (1 << 8)
 773 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 774 #define F_T (1 << 9)
 775 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 776 #define F_GPRSIZE_IN_Q (1 << 10)
 777 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 778 #define F_LDS_SIZE (1 << 11)
 779 /* Optional operand; assume maximum of 1 operand can be optional.  */
 780 #define F_OPD0_OPT (1 << 12)
 781 #define F_OPD1_OPT (2 << 12)
 782 #define F_OPD2_OPT (3 << 12)
 783 #define F_OPD3_OPT (4 << 12)
 784 #define F_OPD4_OPT (5 << 12)
 785 /* Default value for the optional operand when omitted from the assembly.  */
 786 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 787 /* Instruction that is an alias of another instruction needs to be
 788    encoded/decoded by converting it to/from the real form, followed by
 789    the encoding/decoding according to the rules of the real opcode.
 790    This compares to the direct coding using the alias's information.
 791    N.B. this flag requires F_ALIAS to be used together.  */
 792 #define F_CONV (1 << 20)
 793 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 794    friendly pseudo instruction available only in the assembly code (thus will
 795    not show up in the disassembly).  */
 796 #define F_PSEUDO (1 << 21)
 797 /* Instruction has miscellaneous encoding/decoding rules.  */
 798 #define F_MISC (1 << 22)
 799 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 800 #define F_N (1 << 23)
 801 /* Opcode dependent field.  */
 802 #define F_OD(X) (((X) & 0x7) << 24)
 803 /* Instruction has the field of 'sz'.  */
 804 #define F_LSE_SZ (1 << 27)
 805 /* Require an exact qualifier match, even for NIL qualifiers.  */
 806 #define F_STRICT (1ULL << 28)
 807 /* This system instruction is used to read system registers.  */
 808 #define F_SYS_READ (1ULL << 29)
 809 /* This system instruction is used to write system registers.  */
 810 #define F_SYS_WRITE (1ULL << 30)
 811 /* This instruction has an extra constraint on it that imposes a requirement on
 812    subsequent instructions.  */
 813 #define F_SCAN (1ULL << 31)
 814 /* Next bit is 32.  */
 815
 816 /* Instruction constraints.  */
 817 /* This instruction has a predication constraint on the instruction at PC+4.  */
 818 #define C_SCAN_MOVPRFX (1U << 0)
 819 /* This instruction's operation width is determined by the operand with the
 820    largest element size.  */
 821 #define C_MAX_ELEM (1U << 1)
 822 /* Next bit is 2.  */
 823
 824 static inline bfd_boolean
 825 alias_opcode_p (const aarch64_opcode *opcode)
 826 {
 827   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 828 }
 829
 830 static inline bfd_boolean
 831 opcode_has_alias (const aarch64_opcode *opcode)
 832 {
 833   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 834 }
 835
 836 /* Priority for disassembling preference.  */
 837 static inline int
 838 opcode_priority (const aarch64_opcode *opcode)
 839 {
 840   return (opcode->flags >> 2) & 0x3;
 841 }
 842
 843 static inline bfd_boolean
 844 pseudo_opcode_p (const aarch64_opcode *opcode)
 845 {
 846   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 847 }
 848
 849 static inline bfd_boolean
 850 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 851 {
 852   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 853     ? TRUE : FALSE;
 854 }
 855
 856 static inline aarch64_insn
 857 get_optional_operand_default_value (const aarch64_opcode *opcode)
 858 {
 859   return (opcode->flags >> 15) & 0x1f;
 860 }
 861
 862 static inline unsigned int
 863 get_opcode_dependent_value (const aarch64_opcode *opcode)
 864 {
 865   return (opcode->flags >> 24) & 0x7;
 866 }
 867
 868 static inline bfd_boolean
 869 opcode_has_special_coder (const aarch64_opcode *opcode)
 870 {
 871   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 872           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 873     : FALSE;
 874 }
 875 \f
 876 struct aarch64_name_value_pair
 877 {
 878   const char *  name;
 879   aarch64_insn  value;
 880 };
 881
 882 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 883 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 884 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 885 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 886
 887 typedef struct
 888 {
 889   const char *  name;
 890   aarch64_insn  value;
 891   uint32_t      flags;
 892 } aarch64_sys_reg;
 893
 894 extern const aarch64_sys_reg aarch64_sys_regs [];
 895 extern const aarch64_sys_reg aarch64_pstatefields [];
 896 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 897 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 898                                                 const aarch64_sys_reg *);
 899 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 900                                                     const aarch64_sys_reg *);
 901
 902 typedef struct
 903 {
 904   const char *name;
 905   uint32_t value;
 906   uint32_t flags ;
 907 } aarch64_sys_ins_reg;
 908
 909 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 910 extern bfd_boolean
 911 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 912                                  const aarch64_sys_ins_reg *);
 913
 914 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 915 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 916 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 917 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 918
 919 /* Shift/extending operator kinds.
 920    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 921 enum aarch64_modifier_kind
 922 {
 923   AARCH64_MOD_NONE,
 924   AARCH64_MOD_MSL,
 925   AARCH64_MOD_ROR,
 926   AARCH64_MOD_ASR,
 927   AARCH64_MOD_LSR,
 928   AARCH64_MOD_LSL,
 929   AARCH64_MOD_UXTB,
 930   AARCH64_MOD_UXTH,
 931   AARCH64_MOD_UXTW,
 932   AARCH64_MOD_UXTX,
 933   AARCH64_MOD_SXTB,
 934   AARCH64_MOD_SXTH,
 935   AARCH64_MOD_SXTW,
 936   AARCH64_MOD_SXTX,
 937   AARCH64_MOD_MUL,
 938   AARCH64_MOD_MUL_VL,
 939 };
 940
 941 bfd_boolean
 942 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 943
 944 enum aarch64_modifier_kind
 945 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 946 /* Condition.  */
 947
 948 typedef struct
 949 {
 950   /* A list of names with the first one as the disassembly preference;
 951      terminated by NULL if fewer than 3.  */
 952   const char *names[4];
 953   aarch64_insn value;
 954 } aarch64_cond;
 955
 956 extern const aarch64_cond aarch64_conds[16];
 957
 958 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 959 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 960 \f
 961 /* Structure representing an operand.  */
 962
 963 struct aarch64_opnd_info
 964 {
 965   enum aarch64_opnd type;
 966   aarch64_opnd_qualifier_t qualifier;
 967   int idx;
 968
 969   union
 970     {
 971       struct
 972         {
 973           unsigned regno;
 974         } reg;
 975       struct
 976         {
 977           unsigned int regno;
 978           int64_t index;
 979         } reglane;
 980       /* e.g. LVn.  */
 981       struct
 982         {
 983           unsigned first_regno : 5;
 984           unsigned num_regs : 3;
 985           /* 1 if it is a list of reg element.  */
 986           unsigned has_index : 1;
 987           /* Lane index; valid only when has_index is 1.  */
 988           int64_t index;
 989         } reglist;
 990       /* e.g. immediate or pc relative address offset.  */
 991       struct
 992         {
 993           int64_t value;
 994           unsigned is_fp : 1;
 995         } imm;
 996       /* e.g. address in STR (register offset).  */
 997       struct
 998         {
 999           unsigned base_regno;
1000           struct
1001             {
1002               union
1003                 {
1004                   int imm;
1005                   unsigned regno;
1006                 };
1007               unsigned is_reg;
1008             } offset;
1009           unsigned pcrel : 1;           /* PC-relative.  */
1010           unsigned writeback : 1;
1011           unsigned preind : 1;          /* Pre-indexed.  */
1012           unsigned postind : 1;         /* Post-indexed.  */
1013         } addr;
1014
1015       struct
1016         {
1017           /* The encoding of the system register.  */
1018           aarch64_insn value;
1019
1020           /* The system register flags.  */
1021           uint32_t flags;
1022         } sysreg;
1023
1024       const aarch64_cond *cond;
1025       /* The encoding of the PSTATE field.  */
1026       aarch64_insn pstatefield;
1027       const aarch64_sys_ins_reg *sysins_op;
1028       const struct aarch64_name_value_pair *barrier;
1029       const struct aarch64_name_value_pair *hint_option;
1030       const struct aarch64_name_value_pair *prfop;
1031     };
1032
1033   /* Operand shifter; in use when the operand is a register offset address,
1034      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1035   struct
1036     {
1037       enum aarch64_modifier_kind kind;
1038       unsigned operator_present: 1;     /* Only valid during encoding.  */
1039       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1040       unsigned amount_present: 1;
1041       int64_t amount;
1042     } shifter;
1043
1044   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1045                            to be done on it.  In some (but not all) of these
1046                            cases, we need to tell libopcodes to skip the
1047                            constraint checking and the encoding for this
1048                            operand, so that the libopcodes can pick up the
1049                            right opcode before the operand is fixed-up.  This
1050                            flag should only be used during the
1051                            assembling/encoding.  */
1052   unsigned present:1;   /* Whether this operand is present in the assembly
1053                            line; not used during the disassembly.  */
1054 };
1055
1056 typedef struct aarch64_opnd_info aarch64_opnd_info;
1057
1058 /* Structure representing an instruction.
1059
1060    It is used during both the assembling and disassembling.  The assembler
1061    fills an aarch64_inst after a successful parsing and then passes it to the
1062    encoding routine to do the encoding.  During the disassembling, the
1063    disassembler calls the decoding routine to decode a binary instruction; on a
1064    successful return, such a structure will be filled with information of the
1065    instruction; then the disassembler uses the information to print out the
1066    instruction.  */
1067
1068 struct aarch64_inst
1069 {
1070   /* The value of the binary instruction.  */
1071   aarch64_insn value;
1072
1073   /* Corresponding opcode entry.  */
1074   const aarch64_opcode *opcode;
1075
1076   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1077   const aarch64_cond *cond;
1078
1079   /* Operands information.  */
1080   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1081 };
1082
1083 \f
1084 /* Diagnosis related declaration and interface.  */
1085
1086 /* Operand error kind enumerators.
1087
1088    AARCH64_OPDE_RECOVERABLE
1089      Less severe error found during the parsing, very possibly because that
1090      GAS has picked up a wrong instruction template for the parsing.
1091
1092    AARCH64_OPDE_SYNTAX_ERROR
1093      General syntax error; it can be either a user error, or simply because
1094      that GAS is trying a wrong instruction template.
1095
1096    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1097      Definitely a user syntax error.
1098
1099    AARCH64_OPDE_INVALID_VARIANT
1100      No syntax error, but the operands are not a valid combination, e.g.
1101      FMOV D0,S0
1102
1103    AARCH64_OPDE_UNTIED_OPERAND
1104      The asm failed to use the same register for a destination operand
1105      and a tied source operand.
1106
1107    AARCH64_OPDE_OUT_OF_RANGE
1108      Error about some immediate value out of a valid range.
1109
1110    AARCH64_OPDE_UNALIGNED
1111      Error about some immediate value not properly aligned (i.e. not being a
1112      multiple times of a certain value).
1113
1114    AARCH64_OPDE_REG_LIST
1115      Error about the register list operand having unexpected number of
1116      registers.
1117
1118    AARCH64_OPDE_OTHER_ERROR
1119      Error of the highest severity and used for any severe issue that does not
1120      fall into any of the above categories.
1121
1122    The enumerators are only interesting to GAS.  They are declared here (in
1123    libopcodes) because that some errors are detected (and then notified to GAS)
1124    by libopcodes (rather than by GAS solely).
1125
1126    The first three errors are only deteced by GAS while the
1127    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1128    only libopcodes has the information about the valid variants of each
1129    instruction.
1130
1131    The enumerators have an increasing severity.  This is helpful when there are
1132    multiple instruction templates available for a given mnemonic name (e.g.
1133    FMOV); this mechanism will help choose the most suitable template from which
1134    the generated diagnostics can most closely describe the issues, if any.  */
1135
1136 enum aarch64_operand_error_kind
1137 {
1138   AARCH64_OPDE_NIL,
1139   AARCH64_OPDE_RECOVERABLE,
1140   AARCH64_OPDE_SYNTAX_ERROR,
1141   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1142   AARCH64_OPDE_INVALID_VARIANT,
1143   AARCH64_OPDE_UNTIED_OPERAND,
1144   AARCH64_OPDE_OUT_OF_RANGE,
1145   AARCH64_OPDE_UNALIGNED,
1146   AARCH64_OPDE_REG_LIST,
1147   AARCH64_OPDE_OTHER_ERROR
1148 };
1149
1150 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1151 struct aarch64_operand_error
1152 {
1153   enum aarch64_operand_error_kind kind;
1154   int index;
1155   const char *error;
1156   int data[3];  /* Some data for extra information.  */
1157   bfd_boolean non_fatal;
1158 };
1159
1160 /* AArch64 sequence structure used to track instructions with F_SCAN
1161    dependencies for both assembler and disassembler.  */
1162 struct aarch64_instr_sequence
1163 {
1164   /* The instruction that caused this sequence to be opened.  */
1165   aarch64_inst *instr;
1166   /* The number of instructions the above instruction allows to be kept in the
1167      sequence before an automatic close is done.  */
1168   int num_insns;
1169   /* The instructions currently added to the sequence.  */
1170   aarch64_inst **current_insns;
1171   /* The number of instructions already in the sequence.  */
1172   int next_insn;
1173 };
1174
1175 /* Encoding entrypoint.  */
1176
1177 extern int
1178 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1179                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1180                        aarch64_operand_error *, aarch64_instr_sequence *);
1181
1182 extern const aarch64_opcode *
1183 aarch64_replace_opcode (struct aarch64_inst *,
1184                         const aarch64_opcode *);
1185
1186 /* Given the opcode enumerator OP, return the pointer to the corresponding
1187    opcode entry.  */
1188
1189 extern const aarch64_opcode *
1190 aarch64_get_opcode (enum aarch64_op);
1191
1192 /* Generate the string representation of an operand.  */
1193 extern void
1194 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1195                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1196                        char **);
1197
1198 /* Miscellaneous interface.  */
1199
1200 extern int
1201 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1202
1203 extern aarch64_opnd_qualifier_t
1204 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1205                                 const aarch64_opnd_qualifier_t, int);
1206
1207 extern bfd_boolean
1208 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1209
1210 extern int
1211 aarch64_num_of_operands (const aarch64_opcode *);
1212
1213 extern int
1214 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1215
1216 extern int
1217 aarch64_zero_register_p (const aarch64_opnd_info *);
1218
1219 extern enum err_type
1220 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1221                      aarch64_operand_error *);
1222
1223 extern void
1224 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1225
1226 /* Given an operand qualifier, return the expected data element size
1227    of a qualified operand.  */
1228 extern unsigned char
1229 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1230
1231 extern enum aarch64_operand_class
1232 aarch64_get_operand_class (enum aarch64_opnd);
1233
1234 extern const char *
1235 aarch64_get_operand_name (enum aarch64_opnd);
1236
1237 extern const char *
1238 aarch64_get_operand_desc (enum aarch64_opnd);
1239
1240 extern bfd_boolean
1241 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1242
1243 #ifdef DEBUG_AARCH64
1244 extern int debug_dump;
1245
1246 extern void
1247 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1248
1249 #define DEBUG_TRACE(M, ...)                                     \
1250   {                                                             \
1251     if (debug_dump)                                             \
1252       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1253   }
1254
1255 #define DEBUG_TRACE_IF(C, M, ...)                               \
1256   {                                                             \
1257     if (debug_dump && (C))                                      \
1258       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1259   }
1260 #else  /* !DEBUG_AARCH64 */
1261 #define DEBUG_TRACE(M, ...) ;
1262 #define DEBUG_TRACE_IF(C, M, ...) ;
1263 #endif /* DEBUG_AARCH64 */
1264
1265 extern const char *const aarch64_sve_pattern_array[32];
1266 extern const char *const aarch64_sve_prfop_array[16];
1267
1268 #ifdef __cplusplus
1269 }
1270 #endif
1271
1272 #endif /* OPCODE_AARCH64_H */