include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Flag Manipulation insns.  */
  68 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  69 /* FRINT[32,64][Z,X] insns.  */
  70 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  71 /* SB instruction.  */
  72 #define AARCH64_FEATURE_SB              0x10000000000ULL
  73 /* Execution and Data Prediction Restriction instructions.  */
  74 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  75 /* DC CVADP.  */
  76 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  77 /* Random Number instructions.  */
  78 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  79 /* BTI instructions.  */
  80 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  81 /* SCXTNUM_ELx.  */
  82 #define AARCH64_FEATURE_SCXTNUM         0x200000000000ULL
  83 /* ID_PFR2 instructions.  */
  84 #define AARCH64_FEATURE_ID_PFR2         0x400000000000ULL
  85 /* SSBS mechanism enabled.  */
  86 #define AARCH64_FEATURE_SSBS            0x800000000000ULL
  87 /* Memory Tagging Extension.  */
  88 #define AARCH64_FEATURE_MEMTAG          0x1000000000000ULL
  89
  90
  91 /* Architectures are the sum of the base and extensions.  */
  92 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  93                                                  AARCH64_FEATURE_FP  \
  94                                                  | AARCH64_FEATURE_SIMD)
  95 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  96                                                  AARCH64_FEATURE_CRC    \
  97                                                  | AARCH64_FEATURE_V8_1 \
  98                                                  | AARCH64_FEATURE_LSE  \
  99                                                  | AARCH64_FEATURE_PAN  \
 100                                                  | AARCH64_FEATURE_LOR  \
 101                                                  | AARCH64_FEATURE_RDMA)
 102 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 103                                                  AARCH64_FEATURE_V8_2   \
 104                                                  | AARCH64_FEATURE_RAS)
 105 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 106                                                  AARCH64_FEATURE_V8_3   \
 107                                                  | AARCH64_FEATURE_RCPC \
 108                                                  | AARCH64_FEATURE_COMPNUM)
 109 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 110                                                  AARCH64_FEATURE_V8_4   \
 111                                                  | AARCH64_FEATURE_DOTPROD \
 112                                                  | AARCH64_FEATURE_F16_FML)
 113 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 114                                                  AARCH64_FEATURE_V8_5   \
 115                                                  | AARCH64_FEATURE_FLAGMANIP \
 116                                                  | AARCH64_FEATURE_FRINTTS \
 117                                                  | AARCH64_FEATURE_SB   \
 118                                                  | AARCH64_FEATURE_PREDRES \
 119                                                  | AARCH64_FEATURE_CVADP \
 120                                                  | AARCH64_FEATURE_BTI  \
 121                                                  | AARCH64_FEATURE_SCXTNUM \
 122                                                  | AARCH64_FEATURE_ID_PFR2 \
 123                                                  | AARCH64_FEATURE_SSBS)
 124
 125
 126 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 127 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 128
 129 /* CPU-specific features.  */
 130 typedef unsigned long long aarch64_feature_set;
 131
 132 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 133   ((~(CPU) & (FEAT)) == 0)
 134
 135 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 136   (((CPU) & (FEAT)) != 0)
 137
 138 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 139   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 140
 141 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 142   do                                            \
 143     {                                           \
 144       (TARG) = (F1) | (F2);                     \
 145     }                                           \
 146   while (0)
 147
 148 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 149   do                                            \
 150     {                                           \
 151       (TARG) = (F1) &~ (F2);                    \
 152     }                                           \
 153   while (0)
 154
 155 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 156
 157 enum aarch64_operand_class
 158 {
 159   AARCH64_OPND_CLASS_NIL,
 160   AARCH64_OPND_CLASS_INT_REG,
 161   AARCH64_OPND_CLASS_MODIFIED_REG,
 162   AARCH64_OPND_CLASS_FP_REG,
 163   AARCH64_OPND_CLASS_SIMD_REG,
 164   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 165   AARCH64_OPND_CLASS_SISD_REG,
 166   AARCH64_OPND_CLASS_SIMD_REGLIST,
 167   AARCH64_OPND_CLASS_SVE_REG,
 168   AARCH64_OPND_CLASS_PRED_REG,
 169   AARCH64_OPND_CLASS_ADDRESS,
 170   AARCH64_OPND_CLASS_IMMEDIATE,
 171   AARCH64_OPND_CLASS_SYSTEM,
 172   AARCH64_OPND_CLASS_COND,
 173 };
 174
 175 /* Operand code that helps both parsing and coding.
 176    Keep AARCH64_OPERANDS synced.  */
 177
 178 enum aarch64_opnd
 179 {
 180   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 181
 182   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 183   AARCH64_OPND_Rn,      /* Integer register as source.  */
 184   AARCH64_OPND_Rm,      /* Integer register as source.  */
 185   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 186   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 187   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 188   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 189   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 190
 191   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 192   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 193   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 194   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 195   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 196   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 197
 198   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 199   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 200   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 201   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 202   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 203   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 204
 205   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 206   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 207   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 208
 209   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 210   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 211   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 212   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 213   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 214   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 215   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 216   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 217   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 218   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 219                            qualifier is S_H.  */
 220   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 221   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 222   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 223                            structure to all lanes.  */
 224   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 225
 226   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 227   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 228
 229   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 230   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 231   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 232   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 233   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 234   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 235   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 236   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 237                            (no encoding).  */
 238   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 239   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 240   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 241   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 242   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 243   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 244   AARCH64_OPND_IMM,     /* Immediate.  */
 245   AARCH64_OPND_IMM_2,   /* Immediate.  */
 246   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 247   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 248   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 249   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 250   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 251   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 252   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 253   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 254   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 255                            each condition flag.  */
 256
 257   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 258   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 259   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 260   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 261   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 262   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 263   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 264   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 265
 266   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 267   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 268
 269   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 270   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 271   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 272   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 273   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 274
 275   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 276   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 277   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 278   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 279   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 280                                    negative or unaligned and there is
 281                                    no writeback allowed.  This operand code
 282                                    is only used to support the programmer-
 283                                    friendly feature of using LDR/STR as the
 284                                    the mnemonic name for LDUR/STUR instructions
 285                                    wherever there is no ambiguity.  */
 286   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 287   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 288   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 289   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 290   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 291
 292   AARCH64_OPND_SYSREG,          /* System register operand.  */
 293   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 294   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 295   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 296   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 297   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 298   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 299   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 300   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 301   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 302   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 303   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 304
 305   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 306   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 307   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 308   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 309   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 310   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 311   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 312   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 313   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 314   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 315   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 316   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 317   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 318   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 319   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 320   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 321   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 322   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 323   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 324   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 325   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 326   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 327   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 328   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 329   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 330                                        Bit 14 controls S/U choice.  */
 331   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 332                                        Bit 22 controls S/U choice.  */
 333   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 334                                        Bit 14 controls S/U choice.  */
 335   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 336                                        Bit 22 controls S/U choice.  */
 337   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 338                                        Bit 14 controls S/U choice.  */
 339   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 340                                        Bit 22 controls S/U choice.  */
 341   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 342                                        Bit 14 controls S/U choice.  */
 343   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 344                                        Bit 22 controls S/U choice.  */
 345   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 346   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 347   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 348   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 349   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 350   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 351   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 352   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 353   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 354   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 355   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 356   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 357   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 358   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 359   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 360   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 361   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 362   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 363   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 364   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 365   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 366   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 367   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 368   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 369   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 370   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 371   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 372   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 373   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 374   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 375   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 376   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 377   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 378   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 379   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 380   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 381   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 382   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 383   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 384   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 385   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 386   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 387   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 388   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 389   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 390   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 391   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 392   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 393   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 394   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 395   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 396   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 397   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 398   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 399   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 400   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 401   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 402   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 403   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 404   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 405   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 406 };
 407
 408 /* Qualifier constrains an operand.  It either specifies a variant of an
 409    operand type or limits values available to an operand type.
 410
 411    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 412
 413 enum aarch64_opnd_qualifier
 414 {
 415   /* Indicating no further qualification on an operand.  */
 416   AARCH64_OPND_QLF_NIL,
 417
 418   /* Qualifying an operand which is a general purpose (integer) register;
 419      indicating the operand data size or a specific register.  */
 420   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 421   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 422   AARCH64_OPND_QLF_WSP, /* WSP.  */
 423   AARCH64_OPND_QLF_SP,  /* SP.  */
 424
 425   /* Qualifying an operand which is a floating-point register, a SIMD
 426      vector element or a SIMD vector element list; indicating operand data
 427      size or the size of each SIMD vector element in the case of a SIMD
 428      vector element list.
 429      These qualifiers are also used to qualify an address operand to
 430      indicate the size of data element a load/store instruction is
 431      accessing.
 432      They are also used for the immediate shift operand in e.g. SSHR.  Such
 433      a use is only for the ease of operand encoding/decoding and qualifier
 434      sequence matching; such a use should not be applied widely; use the value
 435      constraint qualifiers for immediate operands wherever possible.  */
 436   AARCH64_OPND_QLF_S_B,
 437   AARCH64_OPND_QLF_S_H,
 438   AARCH64_OPND_QLF_S_S,
 439   AARCH64_OPND_QLF_S_D,
 440   AARCH64_OPND_QLF_S_Q,
 441   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 442      are selected by the instruction.  Other than that it has no difference
 443      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 444      reasons and is an exception from normal AArch64 disassembly scheme.  */
 445   AARCH64_OPND_QLF_S_4B,
 446
 447   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 448      register list; indicating register shape.
 449      They are also used for the immediate shift operand in e.g. SSHR.  Such
 450      a use is only for the ease of operand encoding/decoding and qualifier
 451      sequence matching; such a use should not be applied widely; use the value
 452      constraint qualifiers for immediate operands wherever possible.  */
 453   AARCH64_OPND_QLF_V_4B,
 454   AARCH64_OPND_QLF_V_8B,
 455   AARCH64_OPND_QLF_V_16B,
 456   AARCH64_OPND_QLF_V_2H,
 457   AARCH64_OPND_QLF_V_4H,
 458   AARCH64_OPND_QLF_V_8H,
 459   AARCH64_OPND_QLF_V_2S,
 460   AARCH64_OPND_QLF_V_4S,
 461   AARCH64_OPND_QLF_V_1D,
 462   AARCH64_OPND_QLF_V_2D,
 463   AARCH64_OPND_QLF_V_1Q,
 464
 465   AARCH64_OPND_QLF_P_Z,
 466   AARCH64_OPND_QLF_P_M,
 467
 468   /* Constraint on value.  */
 469   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 470   AARCH64_OPND_QLF_imm_0_7,
 471   AARCH64_OPND_QLF_imm_0_15,
 472   AARCH64_OPND_QLF_imm_0_31,
 473   AARCH64_OPND_QLF_imm_0_63,
 474   AARCH64_OPND_QLF_imm_1_32,
 475   AARCH64_OPND_QLF_imm_1_64,
 476
 477   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 478      or shift-ones.  */
 479   AARCH64_OPND_QLF_LSL,
 480   AARCH64_OPND_QLF_MSL,
 481
 482   /* Special qualifier helping retrieve qualifier information during the
 483      decoding time (currently not in use).  */
 484   AARCH64_OPND_QLF_RETRIEVE,
 485 };
 486 \f
 487 /* Instruction class.  */
 488
 489 enum aarch64_insn_class
 490 {
 491   addsub_carry,
 492   addsub_ext,
 493   addsub_imm,
 494   addsub_shift,
 495   asimdall,
 496   asimddiff,
 497   asimdelem,
 498   asimdext,
 499   asimdimm,
 500   asimdins,
 501   asimdmisc,
 502   asimdperm,
 503   asimdsame,
 504   asimdshf,
 505   asimdtbl,
 506   asisddiff,
 507   asisdelem,
 508   asisdlse,
 509   asisdlsep,
 510   asisdlso,
 511   asisdlsop,
 512   asisdmisc,
 513   asisdone,
 514   asisdpair,
 515   asisdsame,
 516   asisdshf,
 517   bitfield,
 518   branch_imm,
 519   branch_reg,
 520   compbranch,
 521   condbranch,
 522   condcmp_imm,
 523   condcmp_reg,
 524   condsel,
 525   cryptoaes,
 526   cryptosha2,
 527   cryptosha3,
 528   dp_1src,
 529   dp_2src,
 530   dp_3src,
 531   exception,
 532   extract,
 533   float2fix,
 534   float2int,
 535   floatccmp,
 536   floatcmp,
 537   floatdp1,
 538   floatdp2,
 539   floatdp3,
 540   floatimm,
 541   floatsel,
 542   ldst_immpost,
 543   ldst_immpre,
 544   ldst_imm9,    /* immpost or immpre */
 545   ldst_imm10,   /* LDRAA/LDRAB */
 546   ldst_pos,
 547   ldst_regoff,
 548   ldst_unpriv,
 549   ldst_unscaled,
 550   ldstexcl,
 551   ldstnapair_offs,
 552   ldstpair_off,
 553   ldstpair_indexed,
 554   loadlit,
 555   log_imm,
 556   log_shift,
 557   lse_atomic,
 558   movewide,
 559   pcreladdr,
 560   ic_system,
 561   sve_cpy,
 562   sve_index,
 563   sve_limm,
 564   sve_misc,
 565   sve_movprfx,
 566   sve_pred_zm,
 567   sve_shift_pred,
 568   sve_shift_unpred,
 569   sve_size_bhs,
 570   sve_size_bhsd,
 571   sve_size_hsd,
 572   sve_size_sd,
 573   testbranch,
 574   cryptosm3,
 575   cryptosm4,
 576   dotproduct,
 577 };
 578
 579 /* Opcode enumerators.  */
 580
 581 enum aarch64_op
 582 {
 583   OP_NIL,
 584   OP_STRB_POS,
 585   OP_LDRB_POS,
 586   OP_LDRSB_POS,
 587   OP_STRH_POS,
 588   OP_LDRH_POS,
 589   OP_LDRSH_POS,
 590   OP_STR_POS,
 591   OP_LDR_POS,
 592   OP_STRF_POS,
 593   OP_LDRF_POS,
 594   OP_LDRSW_POS,
 595   OP_PRFM_POS,
 596
 597   OP_STURB,
 598   OP_LDURB,
 599   OP_LDURSB,
 600   OP_STURH,
 601   OP_LDURH,
 602   OP_LDURSH,
 603   OP_STUR,
 604   OP_LDUR,
 605   OP_STURV,
 606   OP_LDURV,
 607   OP_LDURSW,
 608   OP_PRFUM,
 609
 610   OP_LDR_LIT,
 611   OP_LDRV_LIT,
 612   OP_LDRSW_LIT,
 613   OP_PRFM_LIT,
 614
 615   OP_ADD,
 616   OP_B,
 617   OP_BL,
 618
 619   OP_MOVN,
 620   OP_MOVZ,
 621   OP_MOVK,
 622
 623   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 624   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 625   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 626
 627   OP_MOV_V,             /* MOV alias for moving vector register.  */
 628
 629   OP_ASR_IMM,
 630   OP_LSR_IMM,
 631   OP_LSL_IMM,
 632
 633   OP_BIC,
 634
 635   OP_UBFX,
 636   OP_BFXIL,
 637   OP_SBFX,
 638   OP_SBFIZ,
 639   OP_BFI,
 640   OP_BFC,               /* ARMv8.2.  */
 641   OP_UBFIZ,
 642   OP_UXTB,
 643   OP_UXTH,
 644   OP_UXTW,
 645
 646   OP_CINC,
 647   OP_CINV,
 648   OP_CNEG,
 649   OP_CSET,
 650   OP_CSETM,
 651
 652   OP_FCVT,
 653   OP_FCVTN,
 654   OP_FCVTN2,
 655   OP_FCVTL,
 656   OP_FCVTL2,
 657   OP_FCVTXN_S,          /* Scalar version.  */
 658
 659   OP_ROR_IMM,
 660
 661   OP_SXTL,
 662   OP_SXTL2,
 663   OP_UXTL,
 664   OP_UXTL2,
 665
 666   OP_MOV_P_P,
 667   OP_MOV_Z_P_Z,
 668   OP_MOV_Z_V,
 669   OP_MOV_Z_Z,
 670   OP_MOV_Z_Zi,
 671   OP_MOVM_P_P_P,
 672   OP_MOVS_P_P,
 673   OP_MOVZS_P_P_P,
 674   OP_MOVZ_P_P_P,
 675   OP_NOTS_P_P_P_Z,
 676   OP_NOT_P_P_P_Z,
 677
 678   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 679
 680   OP_TOTAL_NUM,         /* Pseudo.  */
 681 };
 682
 683 /* Error types.  */
 684 enum err_type
 685 {
 686   ERR_OK,
 687   ERR_UND,
 688   ERR_UNP,
 689   ERR_NYI,
 690   ERR_VFI,
 691   ERR_NR_ENTRIES
 692 };
 693
 694 /* Maximum number of operands an instruction can have.  */
 695 #define AARCH64_MAX_OPND_NUM 6
 696 /* Maximum number of qualifier sequences an instruction can have.  */
 697 #define AARCH64_MAX_QLF_SEQ_NUM 10
 698 /* Operand qualifier typedef; optimized for the size.  */
 699 typedef unsigned char aarch64_opnd_qualifier_t;
 700 /* Operand qualifier sequence typedef.  */
 701 typedef aarch64_opnd_qualifier_t        \
 702           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 703
 704 /* FIXME: improve the efficiency.  */
 705 static inline bfd_boolean
 706 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 707 {
 708   int i;
 709   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 710     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 711       return FALSE;
 712   return TRUE;
 713 }
 714
 715 /*  Forward declare error reporting type.  */
 716 typedef struct aarch64_operand_error aarch64_operand_error;
 717 /* Forward declare instruction sequence type.  */
 718 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 719 /* Forward declare instruction definition.  */
 720 typedef struct aarch64_inst aarch64_inst;
 721
 722 /* This structure holds information for a particular opcode.  */
 723
 724 struct aarch64_opcode
 725 {
 726   /* The name of the mnemonic.  */
 727   const char *name;
 728
 729   /* The opcode itself.  Those bits which will be filled in with
 730      operands are zeroes.  */
 731   aarch64_insn opcode;
 732
 733   /* The opcode mask.  This is used by the disassembler.  This is a
 734      mask containing ones indicating those bits which must match the
 735      opcode field, and zeroes indicating those bits which need not
 736      match (and are presumably filled in by operands).  */
 737   aarch64_insn mask;
 738
 739   /* Instruction class.  */
 740   enum aarch64_insn_class iclass;
 741
 742   /* Enumerator identifier.  */
 743   enum aarch64_op op;
 744
 745   /* Which architecture variant provides this instruction.  */
 746   const aarch64_feature_set *avariant;
 747
 748   /* An array of operand codes.  Each code is an index into the
 749      operand table.  They appear in the order which the operands must
 750      appear in assembly code, and are terminated by a zero.  */
 751   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 752
 753   /* A list of operand qualifier code sequence.  Each operand qualifier
 754      code qualifies the corresponding operand code.  Each operand
 755      qualifier sequence specifies a valid opcode variant and related
 756      constraint on operands.  */
 757   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 758
 759   /* Flags providing information about this instruction */
 760   uint64_t flags;
 761
 762   /* Extra constraints on the instruction that the verifier checks.  */
 763   uint32_t constraints;
 764
 765   /* If nonzero, this operand and operand 0 are both registers and
 766      are required to have the same register number.  */
 767   unsigned char tied_operand;
 768
 769   /* If non-NULL, a function to verify that a given instruction is valid.  */
 770   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 771                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 772                               struct aarch64_instr_sequence *);
 773 };
 774
 775 typedef struct aarch64_opcode aarch64_opcode;
 776
 777 /* Table describing all the AArch64 opcodes.  */
 778 extern aarch64_opcode aarch64_opcode_table[];
 779
 780 /* Opcode flags.  */
 781 #define F_ALIAS (1 << 0)
 782 #define F_HAS_ALIAS (1 << 1)
 783 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 784    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 785 #define F_P1 (1 << 2)
 786 #define F_P2 (2 << 2)
 787 #define F_P3 (3 << 2)
 788 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 789 #define F_COND (1 << 4)
 790 /* Instruction has the field of 'sf'.  */
 791 #define F_SF (1 << 5)
 792 /* Instruction has the field of 'size:Q'.  */
 793 #define F_SIZEQ (1 << 6)
 794 /* Floating-point instruction has the field of 'type'.  */
 795 #define F_FPTYPE (1 << 7)
 796 /* AdvSIMD scalar instruction has the field of 'size'.  */
 797 #define F_SSIZE (1 << 8)
 798 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 799 #define F_T (1 << 9)
 800 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 801 #define F_GPRSIZE_IN_Q (1 << 10)
 802 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 803 #define F_LDS_SIZE (1 << 11)
 804 /* Optional operand; assume maximum of 1 operand can be optional.  */
 805 #define F_OPD0_OPT (1 << 12)
 806 #define F_OPD1_OPT (2 << 12)
 807 #define F_OPD2_OPT (3 << 12)
 808 #define F_OPD3_OPT (4 << 12)
 809 #define F_OPD4_OPT (5 << 12)
 810 /* Default value for the optional operand when omitted from the assembly.  */
 811 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 812 /* Instruction that is an alias of another instruction needs to be
 813    encoded/decoded by converting it to/from the real form, followed by
 814    the encoding/decoding according to the rules of the real opcode.
 815    This compares to the direct coding using the alias's information.
 816    N.B. this flag requires F_ALIAS to be used together.  */
 817 #define F_CONV (1 << 20)
 818 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 819    friendly pseudo instruction available only in the assembly code (thus will
 820    not show up in the disassembly).  */
 821 #define F_PSEUDO (1 << 21)
 822 /* Instruction has miscellaneous encoding/decoding rules.  */
 823 #define F_MISC (1 << 22)
 824 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 825 #define F_N (1 << 23)
 826 /* Opcode dependent field.  */
 827 #define F_OD(X) (((X) & 0x7) << 24)
 828 /* Instruction has the field of 'sz'.  */
 829 #define F_LSE_SZ (1 << 27)
 830 /* Require an exact qualifier match, even for NIL qualifiers.  */
 831 #define F_STRICT (1ULL << 28)
 832 /* This system instruction is used to read system registers.  */
 833 #define F_SYS_READ (1ULL << 29)
 834 /* This system instruction is used to write system registers.  */
 835 #define F_SYS_WRITE (1ULL << 30)
 836 /* This instruction has an extra constraint on it that imposes a requirement on
 837    subsequent instructions.  */
 838 #define F_SCAN (1ULL << 31)
 839 /* Next bit is 32.  */
 840
 841 /* Instruction constraints.  */
 842 /* This instruction has a predication constraint on the instruction at PC+4.  */
 843 #define C_SCAN_MOVPRFX (1U << 0)
 844 /* This instruction's operation width is determined by the operand with the
 845    largest element size.  */
 846 #define C_MAX_ELEM (1U << 1)
 847 /* Next bit is 2.  */
 848
 849 static inline bfd_boolean
 850 alias_opcode_p (const aarch64_opcode *opcode)
 851 {
 852   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 853 }
 854
 855 static inline bfd_boolean
 856 opcode_has_alias (const aarch64_opcode *opcode)
 857 {
 858   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 859 }
 860
 861 /* Priority for disassembling preference.  */
 862 static inline int
 863 opcode_priority (const aarch64_opcode *opcode)
 864 {
 865   return (opcode->flags >> 2) & 0x3;
 866 }
 867
 868 static inline bfd_boolean
 869 pseudo_opcode_p (const aarch64_opcode *opcode)
 870 {
 871   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 872 }
 873
 874 static inline bfd_boolean
 875 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 876 {
 877   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 878     ? TRUE : FALSE;
 879 }
 880
 881 static inline aarch64_insn
 882 get_optional_operand_default_value (const aarch64_opcode *opcode)
 883 {
 884   return (opcode->flags >> 15) & 0x1f;
 885 }
 886
 887 static inline unsigned int
 888 get_opcode_dependent_value (const aarch64_opcode *opcode)
 889 {
 890   return (opcode->flags >> 24) & 0x7;
 891 }
 892
 893 static inline bfd_boolean
 894 opcode_has_special_coder (const aarch64_opcode *opcode)
 895 {
 896   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 897           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 898     : FALSE;
 899 }
 900 \f
 901 struct aarch64_name_value_pair
 902 {
 903   const char *  name;
 904   aarch64_insn  value;
 905 };
 906
 907 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 908 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 909 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 910 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 911
 912 typedef struct
 913 {
 914   const char *  name;
 915   aarch64_insn  value;
 916   uint32_t      flags;
 917 } aarch64_sys_reg;
 918
 919 extern const aarch64_sys_reg aarch64_sys_regs [];
 920 extern const aarch64_sys_reg aarch64_pstatefields [];
 921 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 922 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 923                                                 const aarch64_sys_reg *);
 924 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 925                                                     const aarch64_sys_reg *);
 926
 927 typedef struct
 928 {
 929   const char *name;
 930   uint32_t value;
 931   uint32_t flags ;
 932 } aarch64_sys_ins_reg;
 933
 934 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 935 extern bfd_boolean
 936 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 937                                  const aarch64_sys_ins_reg *);
 938
 939 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 940 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 941 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 942 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 943 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 944
 945 /* Shift/extending operator kinds.
 946    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 947 enum aarch64_modifier_kind
 948 {
 949   AARCH64_MOD_NONE,
 950   AARCH64_MOD_MSL,
 951   AARCH64_MOD_ROR,
 952   AARCH64_MOD_ASR,
 953   AARCH64_MOD_LSR,
 954   AARCH64_MOD_LSL,
 955   AARCH64_MOD_UXTB,
 956   AARCH64_MOD_UXTH,
 957   AARCH64_MOD_UXTW,
 958   AARCH64_MOD_UXTX,
 959   AARCH64_MOD_SXTB,
 960   AARCH64_MOD_SXTH,
 961   AARCH64_MOD_SXTW,
 962   AARCH64_MOD_SXTX,
 963   AARCH64_MOD_MUL,
 964   AARCH64_MOD_MUL_VL,
 965 };
 966
 967 bfd_boolean
 968 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 969
 970 enum aarch64_modifier_kind
 971 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 972 /* Condition.  */
 973
 974 typedef struct
 975 {
 976   /* A list of names with the first one as the disassembly preference;
 977      terminated by NULL if fewer than 3.  */
 978   const char *names[4];
 979   aarch64_insn value;
 980 } aarch64_cond;
 981
 982 extern const aarch64_cond aarch64_conds[16];
 983
 984 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 985 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 986 \f
 987 /* Structure representing an operand.  */
 988
 989 struct aarch64_opnd_info
 990 {
 991   enum aarch64_opnd type;
 992   aarch64_opnd_qualifier_t qualifier;
 993   int idx;
 994
 995   union
 996     {
 997       struct
 998         {
 999           unsigned regno;
1000         } reg;
1001       struct
1002         {
1003           unsigned int regno;
1004           int64_t index;
1005         } reglane;
1006       /* e.g. LVn.  */
1007       struct
1008         {
1009           unsigned first_regno : 5;
1010           unsigned num_regs : 3;
1011           /* 1 if it is a list of reg element.  */
1012           unsigned has_index : 1;
1013           /* Lane index; valid only when has_index is 1.  */
1014           int64_t index;
1015         } reglist;
1016       /* e.g. immediate or pc relative address offset.  */
1017       struct
1018         {
1019           int64_t value;
1020           unsigned is_fp : 1;
1021         } imm;
1022       /* e.g. address in STR (register offset).  */
1023       struct
1024         {
1025           unsigned base_regno;
1026           struct
1027             {
1028               union
1029                 {
1030                   int imm;
1031                   unsigned regno;
1032                 };
1033               unsigned is_reg;
1034             } offset;
1035           unsigned pcrel : 1;           /* PC-relative.  */
1036           unsigned writeback : 1;
1037           unsigned preind : 1;          /* Pre-indexed.  */
1038           unsigned postind : 1;         /* Post-indexed.  */
1039         } addr;
1040
1041       struct
1042         {
1043           /* The encoding of the system register.  */
1044           aarch64_insn value;
1045
1046           /* The system register flags.  */
1047           uint32_t flags;
1048         } sysreg;
1049
1050       const aarch64_cond *cond;
1051       /* The encoding of the PSTATE field.  */
1052       aarch64_insn pstatefield;
1053       const aarch64_sys_ins_reg *sysins_op;
1054       const struct aarch64_name_value_pair *barrier;
1055       const struct aarch64_name_value_pair *hint_option;
1056       const struct aarch64_name_value_pair *prfop;
1057     };
1058
1059   /* Operand shifter; in use when the operand is a register offset address,
1060      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1061   struct
1062     {
1063       enum aarch64_modifier_kind kind;
1064       unsigned operator_present: 1;     /* Only valid during encoding.  */
1065       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1066       unsigned amount_present: 1;
1067       int64_t amount;
1068     } shifter;
1069
1070   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1071                            to be done on it.  In some (but not all) of these
1072                            cases, we need to tell libopcodes to skip the
1073                            constraint checking and the encoding for this
1074                            operand, so that the libopcodes can pick up the
1075                            right opcode before the operand is fixed-up.  This
1076                            flag should only be used during the
1077                            assembling/encoding.  */
1078   unsigned present:1;   /* Whether this operand is present in the assembly
1079                            line; not used during the disassembly.  */
1080 };
1081
1082 typedef struct aarch64_opnd_info aarch64_opnd_info;
1083
1084 /* Structure representing an instruction.
1085
1086    It is used during both the assembling and disassembling.  The assembler
1087    fills an aarch64_inst after a successful parsing and then passes it to the
1088    encoding routine to do the encoding.  During the disassembling, the
1089    disassembler calls the decoding routine to decode a binary instruction; on a
1090    successful return, such a structure will be filled with information of the
1091    instruction; then the disassembler uses the information to print out the
1092    instruction.  */
1093
1094 struct aarch64_inst
1095 {
1096   /* The value of the binary instruction.  */
1097   aarch64_insn value;
1098
1099   /* Corresponding opcode entry.  */
1100   const aarch64_opcode *opcode;
1101
1102   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1103   const aarch64_cond *cond;
1104
1105   /* Operands information.  */
1106   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1107 };
1108
1109 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1110 #define HINT_OPD_CSYNC  0x11
1111 #define HINT_OPD_C      0x22
1112 #define HINT_OPD_J      0x24
1113 #define HINT_OPD_JC     0x26
1114 #define HINT_OPD_NULL   0x00
1115
1116 \f
1117 /* Diagnosis related declaration and interface.  */
1118
1119 /* Operand error kind enumerators.
1120
1121    AARCH64_OPDE_RECOVERABLE
1122      Less severe error found during the parsing, very possibly because that
1123      GAS has picked up a wrong instruction template for the parsing.
1124
1125    AARCH64_OPDE_SYNTAX_ERROR
1126      General syntax error; it can be either a user error, or simply because
1127      that GAS is trying a wrong instruction template.
1128
1129    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1130      Definitely a user syntax error.
1131
1132    AARCH64_OPDE_INVALID_VARIANT
1133      No syntax error, but the operands are not a valid combination, e.g.
1134      FMOV D0,S0
1135
1136    AARCH64_OPDE_UNTIED_OPERAND
1137      The asm failed to use the same register for a destination operand
1138      and a tied source operand.
1139
1140    AARCH64_OPDE_OUT_OF_RANGE
1141      Error about some immediate value out of a valid range.
1142
1143    AARCH64_OPDE_UNALIGNED
1144      Error about some immediate value not properly aligned (i.e. not being a
1145      multiple times of a certain value).
1146
1147    AARCH64_OPDE_REG_LIST
1148      Error about the register list operand having unexpected number of
1149      registers.
1150
1151    AARCH64_OPDE_OTHER_ERROR
1152      Error of the highest severity and used for any severe issue that does not
1153      fall into any of the above categories.
1154
1155    The enumerators are only interesting to GAS.  They are declared here (in
1156    libopcodes) because that some errors are detected (and then notified to GAS)
1157    by libopcodes (rather than by GAS solely).
1158
1159    The first three errors are only deteced by GAS while the
1160    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1161    only libopcodes has the information about the valid variants of each
1162    instruction.
1163
1164    The enumerators have an increasing severity.  This is helpful when there are
1165    multiple instruction templates available for a given mnemonic name (e.g.
1166    FMOV); this mechanism will help choose the most suitable template from which
1167    the generated diagnostics can most closely describe the issues, if any.  */
1168
1169 enum aarch64_operand_error_kind
1170 {
1171   AARCH64_OPDE_NIL,
1172   AARCH64_OPDE_RECOVERABLE,
1173   AARCH64_OPDE_SYNTAX_ERROR,
1174   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1175   AARCH64_OPDE_INVALID_VARIANT,
1176   AARCH64_OPDE_UNTIED_OPERAND,
1177   AARCH64_OPDE_OUT_OF_RANGE,
1178   AARCH64_OPDE_UNALIGNED,
1179   AARCH64_OPDE_REG_LIST,
1180   AARCH64_OPDE_OTHER_ERROR
1181 };
1182
1183 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1184 struct aarch64_operand_error
1185 {
1186   enum aarch64_operand_error_kind kind;
1187   int index;
1188   const char *error;
1189   int data[3];  /* Some data for extra information.  */
1190   bfd_boolean non_fatal;
1191 };
1192
1193 /* AArch64 sequence structure used to track instructions with F_SCAN
1194    dependencies for both assembler and disassembler.  */
1195 struct aarch64_instr_sequence
1196 {
1197   /* The instruction that caused this sequence to be opened.  */
1198   aarch64_inst *instr;
1199   /* The number of instructions the above instruction allows to be kept in the
1200      sequence before an automatic close is done.  */
1201   int num_insns;
1202   /* The instructions currently added to the sequence.  */
1203   aarch64_inst **current_insns;
1204   /* The number of instructions already in the sequence.  */
1205   int next_insn;
1206 };
1207
1208 /* Encoding entrypoint.  */
1209
1210 extern int
1211 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1212                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1213                        aarch64_operand_error *, aarch64_instr_sequence *);
1214
1215 extern const aarch64_opcode *
1216 aarch64_replace_opcode (struct aarch64_inst *,
1217                         const aarch64_opcode *);
1218
1219 /* Given the opcode enumerator OP, return the pointer to the corresponding
1220    opcode entry.  */
1221
1222 extern const aarch64_opcode *
1223 aarch64_get_opcode (enum aarch64_op);
1224
1225 /* Generate the string representation of an operand.  */
1226 extern void
1227 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1228                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1229                        char **);
1230
1231 /* Miscellaneous interface.  */
1232
1233 extern int
1234 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1235
1236 extern aarch64_opnd_qualifier_t
1237 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1238                                 const aarch64_opnd_qualifier_t, int);
1239
1240 extern bfd_boolean
1241 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1242
1243 extern int
1244 aarch64_num_of_operands (const aarch64_opcode *);
1245
1246 extern int
1247 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1248
1249 extern int
1250 aarch64_zero_register_p (const aarch64_opnd_info *);
1251
1252 extern enum err_type
1253 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1254                      aarch64_operand_error *);
1255
1256 extern void
1257 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1258
1259 /* Given an operand qualifier, return the expected data element size
1260    of a qualified operand.  */
1261 extern unsigned char
1262 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1263
1264 extern enum aarch64_operand_class
1265 aarch64_get_operand_class (enum aarch64_opnd);
1266
1267 extern const char *
1268 aarch64_get_operand_name (enum aarch64_opnd);
1269
1270 extern const char *
1271 aarch64_get_operand_desc (enum aarch64_opnd);
1272
1273 extern bfd_boolean
1274 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1275
1276 #ifdef DEBUG_AARCH64
1277 extern int debug_dump;
1278
1279 extern void
1280 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1281
1282 #define DEBUG_TRACE(M, ...)                                     \
1283   {                                                             \
1284     if (debug_dump)                                             \
1285       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1286   }
1287
1288 #define DEBUG_TRACE_IF(C, M, ...)                               \
1289   {                                                             \
1290     if (debug_dump && (C))                                      \
1291       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1292   }
1293 #else  /* !DEBUG_AARCH64 */
1294 #define DEBUG_TRACE(M, ...) ;
1295 #define DEBUG_TRACE_IF(C, M, ...) ;
1296 #endif /* DEBUG_AARCH64 */
1297
1298 extern const char *const aarch64_sve_pattern_array[32];
1299 extern const char *const aarch64_sve_prfop_array[16];
1300
1301 #ifdef __cplusplus
1302 }
1303 #endif
1304
1305 #endif /* OPCODE_AARCH64_H */