include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 /* The offset for pc-relative addressing is currently defined to be 0.  */
  31 #define AARCH64_PCREL_OFFSET            0
  32
  33 typedef uint32_t aarch64_insn;
  34
  35 /* The following bitmasks control CPU features.  */
  36 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  37 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  38 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  39 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  40 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  41 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  42 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  43
  44 /* Architectures are the sum of the base and extensions.  */
  45 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  46                                                  AARCH64_FEATURE_FP  \
  47                                                  | AARCH64_FEATURE_SIMD)
  48 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  49 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  50
  51 /* CPU-specific features.  */
  52 typedef unsigned long aarch64_feature_set;
  53
  54 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  55   (((CPU) & (FEAT)) != 0)
  56
  57 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  58   do                                            \
  59     {                                           \
  60       (TARG) = (F1) | (F2);                     \
  61     }                                           \
  62   while (0)
  63
  64 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  65   do                                            \
  66     {                                           \
  67       (TARG) = (F1) &~ (F2);                    \
  68     }                                           \
  69   while (0)
  70
  71 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
  72
  73 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
  74   (((OPC) & (FEAT)) != 0)
  75
  76 enum aarch64_operand_class
  77 {
  78   AARCH64_OPND_CLASS_NIL,
  79   AARCH64_OPND_CLASS_INT_REG,
  80   AARCH64_OPND_CLASS_MODIFIED_REG,
  81   AARCH64_OPND_CLASS_FP_REG,
  82   AARCH64_OPND_CLASS_SIMD_REG,
  83   AARCH64_OPND_CLASS_SIMD_ELEMENT,
  84   AARCH64_OPND_CLASS_SISD_REG,
  85   AARCH64_OPND_CLASS_SIMD_REGLIST,
  86   AARCH64_OPND_CLASS_CP_REG,
  87   AARCH64_OPND_CLASS_ADDRESS,
  88   AARCH64_OPND_CLASS_IMMEDIATE,
  89   AARCH64_OPND_CLASS_SYSTEM,
  90   AARCH64_OPND_CLASS_COND,
  91 };
  92
  93 /* Operand code that helps both parsing and coding.
  94    Keep AARCH64_OPERANDS synced.  */
  95
  96 enum aarch64_opnd
  97 {
  98   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
  99
 100   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 101   AARCH64_OPND_Rn,      /* Integer register as source.  */
 102   AARCH64_OPND_Rm,      /* Integer register as source.  */
 103   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 104   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 105   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 106   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 107   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 108
 109   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 110   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 111   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 112   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 113   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 114
 115   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 116   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 117   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 118   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 119   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 120   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 121
 122   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 123   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 124   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 125
 126   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 127   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 128   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 129   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 130   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 131   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 132   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 133   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 134   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 135   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 136   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 137                            structure to all lanes.  */
 138   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 139
 140   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 141   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 142
 143   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 144   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 145   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 146   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 147   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 148   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 149   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 150                            (no encoding).  */
 151   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 152   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 153   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 154   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 155   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 156   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 157   AARCH64_OPND_IMM,     /* Immediate.  */
 158   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 159   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 160   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 161   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 162   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 163   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 164   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 165   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 166                            each condition flag.  */
 167
 168   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 169   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 170   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 171   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 172   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 173
 174   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 175   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 176
 177   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 178   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 179   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 180   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 181   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 182
 183   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 184   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 185   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 186   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 187   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 188                                    negative or unaligned and there is
 189                                    no writeback allowed.  This operand code
 190                                    is only used to support the programmer-
 191                                    friendly feature of using LDR/STR as the
 192                                    the mnemonic name for LDUR/STUR instructions
 193                                    wherever there is no ambiguity.  */
 194   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 195   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 196   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 197
 198   AARCH64_OPND_SYSREG,          /* System register operand.  */
 199   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 200   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 201   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 202   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 203   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 204   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 205   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 206   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 207 };
 208
 209 /* Qualifier constrains an operand.  It either specifies a variant of an
 210    operand type or limits values available to an operand type.
 211
 212    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 213
 214 enum aarch64_opnd_qualifier
 215 {
 216   /* Indicating no further qualification on an operand.  */
 217   AARCH64_OPND_QLF_NIL,
 218
 219   /* Qualifying an operand which is a general purpose (integer) register;
 220      indicating the operand data size or a specific register.  */
 221   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 222   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 223   AARCH64_OPND_QLF_WSP, /* WSP.  */
 224   AARCH64_OPND_QLF_SP,  /* SP.  */
 225
 226   /* Qualifying an operand which is a floating-point register, a SIMD
 227      vector element or a SIMD vector element list; indicating operand data
 228      size or the size of each SIMD vector element in the case of a SIMD
 229      vector element list.
 230      These qualifiers are also used to qualify an address operand to
 231      indicate the size of data element a load/store instruction is
 232      accessing.
 233      They are also used for the immediate shift operand in e.g. SSHR.  Such
 234      a use is only for the ease of operand encoding/decoding and qualifier
 235      sequence matching; such a use should not be applied widely; use the value
 236      constraint qualifiers for immediate operands wherever possible.  */
 237   AARCH64_OPND_QLF_S_B,
 238   AARCH64_OPND_QLF_S_H,
 239   AARCH64_OPND_QLF_S_S,
 240   AARCH64_OPND_QLF_S_D,
 241   AARCH64_OPND_QLF_S_Q,
 242
 243   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 244      register list; indicating register shape.
 245      They are also used for the immediate shift operand in e.g. SSHR.  Such
 246      a use is only for the ease of operand encoding/decoding and qualifier
 247      sequence matching; such a use should not be applied widely; use the value
 248      constraint qualifiers for immediate operands wherever possible.  */
 249   AARCH64_OPND_QLF_V_8B,
 250   AARCH64_OPND_QLF_V_16B,
 251   AARCH64_OPND_QLF_V_4H,
 252   AARCH64_OPND_QLF_V_8H,
 253   AARCH64_OPND_QLF_V_2S,
 254   AARCH64_OPND_QLF_V_4S,
 255   AARCH64_OPND_QLF_V_1D,
 256   AARCH64_OPND_QLF_V_2D,
 257   AARCH64_OPND_QLF_V_1Q,
 258
 259   /* Constraint on value.  */
 260   AARCH64_OPND_QLF_imm_0_7,
 261   AARCH64_OPND_QLF_imm_0_15,
 262   AARCH64_OPND_QLF_imm_0_31,
 263   AARCH64_OPND_QLF_imm_0_63,
 264   AARCH64_OPND_QLF_imm_1_32,
 265   AARCH64_OPND_QLF_imm_1_64,
 266
 267   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 268      or shift-ones.  */
 269   AARCH64_OPND_QLF_LSL,
 270   AARCH64_OPND_QLF_MSL,
 271
 272   /* Special qualifier helping retrieve qualifier information during the
 273      decoding time (currently not in use).  */
 274   AARCH64_OPND_QLF_RETRIEVE,
 275 };
 276 \f
 277 /* Instruction class.  */
 278
 279 enum aarch64_insn_class
 280 {
 281   addsub_carry,
 282   addsub_ext,
 283   addsub_imm,
 284   addsub_shift,
 285   asimdall,
 286   asimddiff,
 287   asimdelem,
 288   asimdext,
 289   asimdimm,
 290   asimdins,
 291   asimdmisc,
 292   asimdperm,
 293   asimdsame,
 294   asimdshf,
 295   asimdtbl,
 296   asisddiff,
 297   asisdelem,
 298   asisdlse,
 299   asisdlsep,
 300   asisdlso,
 301   asisdlsop,
 302   asisdmisc,
 303   asisdone,
 304   asisdpair,
 305   asisdsame,
 306   asisdshf,
 307   bitfield,
 308   branch_imm,
 309   branch_reg,
 310   compbranch,
 311   condbranch,
 312   condcmp_imm,
 313   condcmp_reg,
 314   condsel,
 315   cryptoaes,
 316   cryptosha2,
 317   cryptosha3,
 318   dp_1src,
 319   dp_2src,
 320   dp_3src,
 321   exception,
 322   extract,
 323   float2fix,
 324   float2int,
 325   floatccmp,
 326   floatcmp,
 327   floatdp1,
 328   floatdp2,
 329   floatdp3,
 330   floatimm,
 331   floatsel,
 332   ldst_immpost,
 333   ldst_immpre,
 334   ldst_imm9,    /* immpost or immpre */
 335   ldst_pos,
 336   ldst_regoff,
 337   ldst_unpriv,
 338   ldst_unscaled,
 339   ldstexcl,
 340   ldstnapair_offs,
 341   ldstpair_off,
 342   ldstpair_indexed,
 343   loadlit,
 344   log_imm,
 345   log_shift,
 346   lse_atomic,
 347   movewide,
 348   pcreladdr,
 349   ic_system,
 350   testbranch,
 351 };
 352
 353 /* Opcode enumerators.  */
 354
 355 enum aarch64_op
 356 {
 357   OP_NIL,
 358   OP_STRB_POS,
 359   OP_LDRB_POS,
 360   OP_LDRSB_POS,
 361   OP_STRH_POS,
 362   OP_LDRH_POS,
 363   OP_LDRSH_POS,
 364   OP_STR_POS,
 365   OP_LDR_POS,
 366   OP_STRF_POS,
 367   OP_LDRF_POS,
 368   OP_LDRSW_POS,
 369   OP_PRFM_POS,
 370
 371   OP_STURB,
 372   OP_LDURB,
 373   OP_LDURSB,
 374   OP_STURH,
 375   OP_LDURH,
 376   OP_LDURSH,
 377   OP_STUR,
 378   OP_LDUR,
 379   OP_STURV,
 380   OP_LDURV,
 381   OP_LDURSW,
 382   OP_PRFUM,
 383
 384   OP_LDR_LIT,
 385   OP_LDRV_LIT,
 386   OP_LDRSW_LIT,
 387   OP_PRFM_LIT,
 388
 389   OP_ADD,
 390   OP_B,
 391   OP_BL,
 392
 393   OP_MOVN,
 394   OP_MOVZ,
 395   OP_MOVK,
 396
 397   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 398   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 399   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 400
 401   OP_MOV_V,             /* MOV alias for moving vector register.  */
 402
 403   OP_ASR_IMM,
 404   OP_LSR_IMM,
 405   OP_LSL_IMM,
 406
 407   OP_BIC,
 408
 409   OP_UBFX,
 410   OP_BFXIL,
 411   OP_SBFX,
 412   OP_SBFIZ,
 413   OP_BFI,
 414   OP_UBFIZ,
 415   OP_UXTB,
 416   OP_UXTH,
 417   OP_UXTW,
 418
 419   OP_CINC,
 420   OP_CINV,
 421   OP_CNEG,
 422   OP_CSET,
 423   OP_CSETM,
 424
 425   OP_FCVT,
 426   OP_FCVTN,
 427   OP_FCVTN2,
 428   OP_FCVTL,
 429   OP_FCVTL2,
 430   OP_FCVTXN_S,          /* Scalar version.  */
 431
 432   OP_ROR_IMM,
 433
 434   OP_SXTL,
 435   OP_SXTL2,
 436   OP_UXTL,
 437   OP_UXTL2,
 438
 439   OP_TOTAL_NUM,         /* Pseudo.  */
 440 };
 441
 442 /* Maximum number of operands an instruction can have.  */
 443 #define AARCH64_MAX_OPND_NUM 6
 444 /* Maximum number of qualifier sequences an instruction can have.  */
 445 #define AARCH64_MAX_QLF_SEQ_NUM 10
 446 /* Operand qualifier typedef; optimized for the size.  */
 447 typedef unsigned char aarch64_opnd_qualifier_t;
 448 /* Operand qualifier sequence typedef.  */
 449 typedef aarch64_opnd_qualifier_t        \
 450           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 451
 452 /* FIXME: improve the efficiency.  */
 453 static inline bfd_boolean
 454 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 455 {
 456   int i;
 457   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 458     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 459       return FALSE;
 460   return TRUE;
 461 }
 462
 463 /* This structure holds information for a particular opcode.  */
 464
 465 struct aarch64_opcode
 466 {
 467   /* The name of the mnemonic.  */
 468   const char *name;
 469
 470   /* The opcode itself.  Those bits which will be filled in with
 471      operands are zeroes.  */
 472   aarch64_insn opcode;
 473
 474   /* The opcode mask.  This is used by the disassembler.  This is a
 475      mask containing ones indicating those bits which must match the
 476      opcode field, and zeroes indicating those bits which need not
 477      match (and are presumably filled in by operands).  */
 478   aarch64_insn mask;
 479
 480   /* Instruction class.  */
 481   enum aarch64_insn_class iclass;
 482
 483   /* Enumerator identifier.  */
 484   enum aarch64_op op;
 485
 486   /* Which architecture variant provides this instruction.  */
 487   const aarch64_feature_set *avariant;
 488
 489   /* An array of operand codes.  Each code is an index into the
 490      operand table.  They appear in the order which the operands must
 491      appear in assembly code, and are terminated by a zero.  */
 492   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 493
 494   /* A list of operand qualifier code sequence.  Each operand qualifier
 495      code qualifies the corresponding operand code.  Each operand
 496      qualifier sequence specifies a valid opcode variant and related
 497      constraint on operands.  */
 498   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 499
 500   /* Flags providing information about this instruction */
 501   uint32_t flags;
 502 };
 503
 504 typedef struct aarch64_opcode aarch64_opcode;
 505
 506 /* Table describing all the AArch64 opcodes.  */
 507 extern aarch64_opcode aarch64_opcode_table[];
 508
 509 /* Opcode flags.  */
 510 #define F_ALIAS (1 << 0)
 511 #define F_HAS_ALIAS (1 << 1)
 512 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 513    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 514 #define F_P1 (1 << 2)
 515 #define F_P2 (2 << 2)
 516 #define F_P3 (3 << 2)
 517 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 518 #define F_COND (1 << 4)
 519 /* Instruction has the field of 'sf'.  */
 520 #define F_SF (1 << 5)
 521 /* Instruction has the field of 'size:Q'.  */
 522 #define F_SIZEQ (1 << 6)
 523 /* Floating-point instruction has the field of 'type'.  */
 524 #define F_FPTYPE (1 << 7)
 525 /* AdvSIMD scalar instruction has the field of 'size'.  */
 526 #define F_SSIZE (1 << 8)
 527 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 528 #define F_T (1 << 9)
 529 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 530 #define F_GPRSIZE_IN_Q (1 << 10)
 531 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 532 #define F_LDS_SIZE (1 << 11)
 533 /* Optional operand; assume maximum of 1 operand can be optional.  */
 534 #define F_OPD0_OPT (1 << 12)
 535 #define F_OPD1_OPT (2 << 12)
 536 #define F_OPD2_OPT (3 << 12)
 537 #define F_OPD3_OPT (4 << 12)
 538 #define F_OPD4_OPT (5 << 12)
 539 /* Default value for the optional operand when omitted from the assembly.  */
 540 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 541 /* Instruction that is an alias of another instruction needs to be
 542    encoded/decoded by converting it to/from the real form, followed by
 543    the encoding/decoding according to the rules of the real opcode.
 544    This compares to the direct coding using the alias's information.
 545    N.B. this flag requires F_ALIAS to be used together.  */
 546 #define F_CONV (1 << 20)
 547 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 548    friendly pseudo instruction available only in the assembly code (thus will
 549    not show up in the disassembly).  */
 550 #define F_PSEUDO (1 << 21)
 551 /* Instruction has miscellaneous encoding/decoding rules.  */
 552 #define F_MISC (1 << 22)
 553 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 554 #define F_N (1 << 23)
 555 /* Opcode dependent field.  */
 556 #define F_OD(X) (((X) & 0x7) << 24)
 557 /* Instruction has the field of 'sz'.  */
 558 #define F_LSE_SZ (1 << 27)
 559 /* Next bit is 28.  */
 560
 561 static inline bfd_boolean
 562 alias_opcode_p (const aarch64_opcode *opcode)
 563 {
 564   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 565 }
 566
 567 static inline bfd_boolean
 568 opcode_has_alias (const aarch64_opcode *opcode)
 569 {
 570   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 571 }
 572
 573 /* Priority for disassembling preference.  */
 574 static inline int
 575 opcode_priority (const aarch64_opcode *opcode)
 576 {
 577   return (opcode->flags >> 2) & 0x3;
 578 }
 579
 580 static inline bfd_boolean
 581 pseudo_opcode_p (const aarch64_opcode *opcode)
 582 {
 583   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 584 }
 585
 586 static inline bfd_boolean
 587 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 588 {
 589   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 590     ? TRUE : FALSE;
 591 }
 592
 593 static inline aarch64_insn
 594 get_optional_operand_default_value (const aarch64_opcode *opcode)
 595 {
 596   return (opcode->flags >> 15) & 0x1f;
 597 }
 598
 599 static inline unsigned int
 600 get_opcode_dependent_value (const aarch64_opcode *opcode)
 601 {
 602   return (opcode->flags >> 24) & 0x7;
 603 }
 604
 605 static inline bfd_boolean
 606 opcode_has_special_coder (const aarch64_opcode *opcode)
 607 {
 608   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 609           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 610     : FALSE;
 611 }
 612 \f
 613 struct aarch64_name_value_pair
 614 {
 615   const char *  name;
 616   aarch64_insn  value;
 617 };
 618
 619 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 620 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 621 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 622
 623 typedef struct
 624 {
 625   const char *  name;
 626   aarch64_insn  value;
 627   uint32_t      flags;
 628 } aarch64_sys_reg;
 629
 630 extern const aarch64_sys_reg aarch64_sys_regs [];
 631 extern const aarch64_sys_reg aarch64_pstatefields [];
 632 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 633 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 634                                                 const aarch64_sys_reg *);
 635 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 636                                                     const aarch64_sys_reg *);
 637
 638 typedef struct
 639 {
 640   const char *template;
 641   uint32_t value;
 642   int has_xt;
 643 } aarch64_sys_ins_reg;
 644
 645 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 646 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 647 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 648 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 649
 650 /* Shift/extending operator kinds.
 651    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 652 enum aarch64_modifier_kind
 653 {
 654   AARCH64_MOD_NONE,
 655   AARCH64_MOD_MSL,
 656   AARCH64_MOD_ROR,
 657   AARCH64_MOD_ASR,
 658   AARCH64_MOD_LSR,
 659   AARCH64_MOD_LSL,
 660   AARCH64_MOD_UXTB,
 661   AARCH64_MOD_UXTH,
 662   AARCH64_MOD_UXTW,
 663   AARCH64_MOD_UXTX,
 664   AARCH64_MOD_SXTB,
 665   AARCH64_MOD_SXTH,
 666   AARCH64_MOD_SXTW,
 667   AARCH64_MOD_SXTX,
 668 };
 669
 670 bfd_boolean
 671 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 672
 673 enum aarch64_modifier_kind
 674 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 675 /* Condition.  */
 676
 677 typedef struct
 678 {
 679   /* A list of names with the first one as the disassembly preference;
 680      terminated by NULL if fewer than 3.  */
 681   const char *names[3];
 682   aarch64_insn value;
 683 } aarch64_cond;
 684
 685 extern const aarch64_cond aarch64_conds[16];
 686
 687 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 688 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 689 \f
 690 /* Structure representing an operand.  */
 691
 692 struct aarch64_opnd_info
 693 {
 694   enum aarch64_opnd type;
 695   aarch64_opnd_qualifier_t qualifier;
 696   int idx;
 697
 698   union
 699     {
 700       struct
 701         {
 702           unsigned regno;
 703         } reg;
 704       struct
 705         {
 706           unsigned regno : 5;
 707           unsigned index : 4;
 708         } reglane;
 709       /* e.g. LVn.  */
 710       struct
 711         {
 712           unsigned first_regno : 5;
 713           unsigned num_regs : 3;
 714           /* 1 if it is a list of reg element.  */
 715           unsigned has_index : 1;
 716           /* Lane index; valid only when has_index is 1.  */
 717           unsigned index : 4;
 718         } reglist;
 719       /* e.g. immediate or pc relative address offset.  */
 720       struct
 721         {
 722           int64_t value;
 723           unsigned is_fp : 1;
 724         } imm;
 725       /* e.g. address in STR (register offset).  */
 726       struct
 727         {
 728           unsigned base_regno;
 729           struct
 730             {
 731               union
 732                 {
 733                   int imm;
 734                   unsigned regno;
 735                 };
 736               unsigned is_reg;
 737             } offset;
 738           unsigned pcrel : 1;           /* PC-relative.  */
 739           unsigned writeback : 1;
 740           unsigned preind : 1;          /* Pre-indexed.  */
 741           unsigned postind : 1;         /* Post-indexed.  */
 742         } addr;
 743       const aarch64_cond *cond;
 744       /* The encoding of the system register.  */
 745       aarch64_insn sysreg;
 746       /* The encoding of the PSTATE field.  */
 747       aarch64_insn pstatefield;
 748       const aarch64_sys_ins_reg *sysins_op;
 749       const struct aarch64_name_value_pair *barrier;
 750       const struct aarch64_name_value_pair *prfop;
 751     };
 752
 753   /* Operand shifter; in use when the operand is a register offset address,
 754      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 755   struct
 756     {
 757       enum aarch64_modifier_kind kind;
 758       int amount;
 759       unsigned operator_present: 1;     /* Only valid during encoding.  */
 760       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 761       unsigned amount_present: 1;
 762     } shifter;
 763
 764   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 765                            to be done on it.  In some (but not all) of these
 766                            cases, we need to tell libopcodes to skip the
 767                            constraint checking and the encoding for this
 768                            operand, so that the libopcodes can pick up the
 769                            right opcode before the operand is fixed-up.  This
 770                            flag should only be used during the
 771                            assembling/encoding.  */
 772   unsigned present:1;   /* Whether this operand is present in the assembly
 773                            line; not used during the disassembly.  */
 774 };
 775
 776 typedef struct aarch64_opnd_info aarch64_opnd_info;
 777
 778 /* Structure representing an instruction.
 779
 780    It is used during both the assembling and disassembling.  The assembler
 781    fills an aarch64_inst after a successful parsing and then passes it to the
 782    encoding routine to do the encoding.  During the disassembling, the
 783    disassembler calls the decoding routine to decode a binary instruction; on a
 784    successful return, such a structure will be filled with information of the
 785    instruction; then the disassembler uses the information to print out the
 786    instruction.  */
 787
 788 struct aarch64_inst
 789 {
 790   /* The value of the binary instruction.  */
 791   aarch64_insn value;
 792
 793   /* Corresponding opcode entry.  */
 794   const aarch64_opcode *opcode;
 795
 796   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 797   const aarch64_cond *cond;
 798
 799   /* Operands information.  */
 800   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 801 };
 802
 803 typedef struct aarch64_inst aarch64_inst;
 804 \f
 805 /* Diagnosis related declaration and interface.  */
 806
 807 /* Operand error kind enumerators.
 808
 809    AARCH64_OPDE_RECOVERABLE
 810      Less severe error found during the parsing, very possibly because that
 811      GAS has picked up a wrong instruction template for the parsing.
 812
 813    AARCH64_OPDE_SYNTAX_ERROR
 814      General syntax error; it can be either a user error, or simply because
 815      that GAS is trying a wrong instruction template.
 816
 817    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 818      Definitely a user syntax error.
 819
 820    AARCH64_OPDE_INVALID_VARIANT
 821      No syntax error, but the operands are not a valid combination, e.g.
 822      FMOV D0,S0
 823
 824    AARCH64_OPDE_OUT_OF_RANGE
 825      Error about some immediate value out of a valid range.
 826
 827    AARCH64_OPDE_UNALIGNED
 828      Error about some immediate value not properly aligned (i.e. not being a
 829      multiple times of a certain value).
 830
 831    AARCH64_OPDE_REG_LIST
 832      Error about the register list operand having unexpected number of
 833      registers.
 834
 835    AARCH64_OPDE_OTHER_ERROR
 836      Error of the highest severity and used for any severe issue that does not
 837      fall into any of the above categories.
 838
 839    The enumerators are only interesting to GAS.  They are declared here (in
 840    libopcodes) because that some errors are detected (and then notified to GAS)
 841    by libopcodes (rather than by GAS solely).
 842
 843    The first three errors are only deteced by GAS while the
 844    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 845    only libopcodes has the information about the valid variants of each
 846    instruction.
 847
 848    The enumerators have an increasing severity.  This is helpful when there are
 849    multiple instruction templates available for a given mnemonic name (e.g.
 850    FMOV); this mechanism will help choose the most suitable template from which
 851    the generated diagnostics can most closely describe the issues, if any.  */
 852
 853 enum aarch64_operand_error_kind
 854 {
 855   AARCH64_OPDE_NIL,
 856   AARCH64_OPDE_RECOVERABLE,
 857   AARCH64_OPDE_SYNTAX_ERROR,
 858   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 859   AARCH64_OPDE_INVALID_VARIANT,
 860   AARCH64_OPDE_OUT_OF_RANGE,
 861   AARCH64_OPDE_UNALIGNED,
 862   AARCH64_OPDE_REG_LIST,
 863   AARCH64_OPDE_OTHER_ERROR
 864 };
 865
 866 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 867 struct aarch64_operand_error
 868 {
 869   enum aarch64_operand_error_kind kind;
 870   int index;
 871   const char *error;
 872   int data[3];  /* Some data for extra information.  */
 873 };
 874
 875 typedef struct aarch64_operand_error aarch64_operand_error;
 876
 877 /* Encoding entrypoint.  */
 878
 879 extern int
 880 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 881                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 882                        aarch64_operand_error *);
 883
 884 extern const aarch64_opcode *
 885 aarch64_replace_opcode (struct aarch64_inst *,
 886                         const aarch64_opcode *);
 887
 888 /* Given the opcode enumerator OP, return the pointer to the corresponding
 889    opcode entry.  */
 890
 891 extern const aarch64_opcode *
 892 aarch64_get_opcode (enum aarch64_op);
 893
 894 /* Generate the string representation of an operand.  */
 895 extern void
 896 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 897                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 898
 899 /* Miscellaneous interface.  */
 900
 901 extern int
 902 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 903
 904 extern aarch64_opnd_qualifier_t
 905 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 906                                 const aarch64_opnd_qualifier_t, int);
 907
 908 extern int
 909 aarch64_num_of_operands (const aarch64_opcode *);
 910
 911 extern int
 912 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 913
 914 extern
 915 int aarch64_zero_register_p (const aarch64_opnd_info *);
 916
 917 /* Given an operand qualifier, return the expected data element size
 918    of a qualified operand.  */
 919 extern unsigned char
 920 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 921
 922 extern enum aarch64_operand_class
 923 aarch64_get_operand_class (enum aarch64_opnd);
 924
 925 extern const char *
 926 aarch64_get_operand_name (enum aarch64_opnd);
 927
 928 extern const char *
 929 aarch64_get_operand_desc (enum aarch64_opnd);
 930
 931 #ifdef DEBUG_AARCH64
 932 extern int debug_dump;
 933
 934 extern void
 935 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 936
 937 #define DEBUG_TRACE(M, ...)                                     \
 938   {                                                             \
 939     if (debug_dump)                                             \
 940       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 941   }
 942
 943 #define DEBUG_TRACE_IF(C, M, ...)                               \
 944   {                                                             \
 945     if (debug_dump && (C))                                      \
 946       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 947   }
 948 #else  /* !DEBUG_AARCH64 */
 949 #define DEBUG_TRACE(M, ...) ;
 950 #define DEBUG_TRACE_IF(C, M, ...) ;
 951 #endif /* DEBUG_AARCH64 */
 952
 953 #endif /* OPCODE_AARCH64_H */