include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  54
  55 /* Architectures are the sum of the base and extensions.  */
  56 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  57                                                  AARCH64_FEATURE_FP  \
  58                                                  | AARCH64_FEATURE_SIMD)
  59 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  60                                                  AARCH64_FEATURE_FP  \
  61                                                  | AARCH64_FEATURE_SIMD \
  62                                                  | AARCH64_FEATURE_CRC  \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS  \
  72                                                  | AARCH64_FEATURE_FP   \
  73                                                  | AARCH64_FEATURE_SIMD \
  74                                                  | AARCH64_FEATURE_CRC  \
  75                                                  | AARCH64_FEATURE_V8_1 \
  76                                                  | AARCH64_FEATURE_LSE  \
  77                                                  | AARCH64_FEATURE_PAN  \
  78                                                  | AARCH64_FEATURE_LOR  \
  79                                                  | AARCH64_FEATURE_RDMA)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  88   ((~(CPU) & (FEAT)) == 0)
  89
  90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  91   (((CPU) & (FEAT)) != 0)
  92
  93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  94   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  95
  96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) | (F2);                     \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 104   do                                            \
 105     {                                           \
 106       (TARG) = (F1) &~ (F2);                    \
 107     }                                           \
 108   while (0)
 109
 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 111
 112 enum aarch64_operand_class
 113 {
 114   AARCH64_OPND_CLASS_NIL,
 115   AARCH64_OPND_CLASS_INT_REG,
 116   AARCH64_OPND_CLASS_MODIFIED_REG,
 117   AARCH64_OPND_CLASS_FP_REG,
 118   AARCH64_OPND_CLASS_SIMD_REG,
 119   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 120   AARCH64_OPND_CLASS_SISD_REG,
 121   AARCH64_OPND_CLASS_SIMD_REGLIST,
 122   AARCH64_OPND_CLASS_CP_REG,
 123   AARCH64_OPND_CLASS_SVE_REG,
 124   AARCH64_OPND_CLASS_PRED_REG,
 125   AARCH64_OPND_CLASS_ADDRESS,
 126   AARCH64_OPND_CLASS_IMMEDIATE,
 127   AARCH64_OPND_CLASS_SYSTEM,
 128   AARCH64_OPND_CLASS_COND,
 129 };
 130
 131 /* Operand code that helps both parsing and coding.
 132    Keep AARCH64_OPERANDS synced.  */
 133
 134 enum aarch64_opnd
 135 {
 136   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 137
 138   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 139   AARCH64_OPND_Rn,      /* Integer register as source.  */
 140   AARCH64_OPND_Rm,      /* Integer register as source.  */
 141   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 142   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 143   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 144   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 145   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 146
 147   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 148   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 149   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 150   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 151   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 152
 153   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 154   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 155   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 156   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 157   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 158   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 159
 160   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 161   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 162   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 163
 164   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 165   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 166   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 167   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 169   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 170   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 171   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 172   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 173   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 174   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 175                            structure to all lanes.  */
 176   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 177
 178   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 179   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 180
 181   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 182   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 183   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 184   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 185   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 186   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 187   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 188                            (no encoding).  */
 189   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 190   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 191   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 192   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 193   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 194   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 195   AARCH64_OPND_IMM,     /* Immediate.  */
 196   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 197   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 198   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 199   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 200   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 201   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 202   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 203   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 204                            each condition flag.  */
 205
 206   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 207   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 208   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 209   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 210   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 211
 212   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 213   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 214
 215   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 216   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 217   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 218   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 219   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 220
 221   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 222   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 223   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 224   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 225   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 226                                    negative or unaligned and there is
 227                                    no writeback allowed.  This operand code
 228                                    is only used to support the programmer-
 229                                    friendly feature of using LDR/STR as the
 230                                    the mnemonic name for LDUR/STUR instructions
 231                                    wherever there is no ambiguity.  */
 232   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 233   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 234   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 235
 236   AARCH64_OPND_SYSREG,          /* System register operand.  */
 237   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 238   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 239   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 240   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 241   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 242   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 243   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 244   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 245   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 246
 247   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 248   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 249   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 250   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 251   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 252   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 253   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 254   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 255   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 256   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 257   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 258   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 259   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 260   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 261   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 262   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 263   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 264   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 265 };
 266
 267 /* Qualifier constrains an operand.  It either specifies a variant of an
 268    operand type or limits values available to an operand type.
 269
 270    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 271
 272 enum aarch64_opnd_qualifier
 273 {
 274   /* Indicating no further qualification on an operand.  */
 275   AARCH64_OPND_QLF_NIL,
 276
 277   /* Qualifying an operand which is a general purpose (integer) register;
 278      indicating the operand data size or a specific register.  */
 279   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 280   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 281   AARCH64_OPND_QLF_WSP, /* WSP.  */
 282   AARCH64_OPND_QLF_SP,  /* SP.  */
 283
 284   /* Qualifying an operand which is a floating-point register, a SIMD
 285      vector element or a SIMD vector element list; indicating operand data
 286      size or the size of each SIMD vector element in the case of a SIMD
 287      vector element list.
 288      These qualifiers are also used to qualify an address operand to
 289      indicate the size of data element a load/store instruction is
 290      accessing.
 291      They are also used for the immediate shift operand in e.g. SSHR.  Such
 292      a use is only for the ease of operand encoding/decoding and qualifier
 293      sequence matching; such a use should not be applied widely; use the value
 294      constraint qualifiers for immediate operands wherever possible.  */
 295   AARCH64_OPND_QLF_S_B,
 296   AARCH64_OPND_QLF_S_H,
 297   AARCH64_OPND_QLF_S_S,
 298   AARCH64_OPND_QLF_S_D,
 299   AARCH64_OPND_QLF_S_Q,
 300
 301   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 302      register list; indicating register shape.
 303      They are also used for the immediate shift operand in e.g. SSHR.  Such
 304      a use is only for the ease of operand encoding/decoding and qualifier
 305      sequence matching; such a use should not be applied widely; use the value
 306      constraint qualifiers for immediate operands wherever possible.  */
 307   AARCH64_OPND_QLF_V_8B,
 308   AARCH64_OPND_QLF_V_16B,
 309   AARCH64_OPND_QLF_V_2H,
 310   AARCH64_OPND_QLF_V_4H,
 311   AARCH64_OPND_QLF_V_8H,
 312   AARCH64_OPND_QLF_V_2S,
 313   AARCH64_OPND_QLF_V_4S,
 314   AARCH64_OPND_QLF_V_1D,
 315   AARCH64_OPND_QLF_V_2D,
 316   AARCH64_OPND_QLF_V_1Q,
 317
 318   /* Constraint on value.  */
 319   AARCH64_OPND_QLF_imm_0_7,
 320   AARCH64_OPND_QLF_imm_0_15,
 321   AARCH64_OPND_QLF_imm_0_31,
 322   AARCH64_OPND_QLF_imm_0_63,
 323   AARCH64_OPND_QLF_imm_1_32,
 324   AARCH64_OPND_QLF_imm_1_64,
 325
 326   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 327      or shift-ones.  */
 328   AARCH64_OPND_QLF_LSL,
 329   AARCH64_OPND_QLF_MSL,
 330
 331   /* Special qualifier helping retrieve qualifier information during the
 332      decoding time (currently not in use).  */
 333   AARCH64_OPND_QLF_RETRIEVE,
 334 };
 335 \f
 336 /* Instruction class.  */
 337
 338 enum aarch64_insn_class
 339 {
 340   addsub_carry,
 341   addsub_ext,
 342   addsub_imm,
 343   addsub_shift,
 344   asimdall,
 345   asimddiff,
 346   asimdelem,
 347   asimdext,
 348   asimdimm,
 349   asimdins,
 350   asimdmisc,
 351   asimdperm,
 352   asimdsame,
 353   asimdshf,
 354   asimdtbl,
 355   asisddiff,
 356   asisdelem,
 357   asisdlse,
 358   asisdlsep,
 359   asisdlso,
 360   asisdlsop,
 361   asisdmisc,
 362   asisdone,
 363   asisdpair,
 364   asisdsame,
 365   asisdshf,
 366   bitfield,
 367   branch_imm,
 368   branch_reg,
 369   compbranch,
 370   condbranch,
 371   condcmp_imm,
 372   condcmp_reg,
 373   condsel,
 374   cryptoaes,
 375   cryptosha2,
 376   cryptosha3,
 377   dp_1src,
 378   dp_2src,
 379   dp_3src,
 380   exception,
 381   extract,
 382   float2fix,
 383   float2int,
 384   floatccmp,
 385   floatcmp,
 386   floatdp1,
 387   floatdp2,
 388   floatdp3,
 389   floatimm,
 390   floatsel,
 391   ldst_immpost,
 392   ldst_immpre,
 393   ldst_imm9,    /* immpost or immpre */
 394   ldst_pos,
 395   ldst_regoff,
 396   ldst_unpriv,
 397   ldst_unscaled,
 398   ldstexcl,
 399   ldstnapair_offs,
 400   ldstpair_off,
 401   ldstpair_indexed,
 402   loadlit,
 403   log_imm,
 404   log_shift,
 405   lse_atomic,
 406   movewide,
 407   pcreladdr,
 408   ic_system,
 409   testbranch,
 410 };
 411
 412 /* Opcode enumerators.  */
 413
 414 enum aarch64_op
 415 {
 416   OP_NIL,
 417   OP_STRB_POS,
 418   OP_LDRB_POS,
 419   OP_LDRSB_POS,
 420   OP_STRH_POS,
 421   OP_LDRH_POS,
 422   OP_LDRSH_POS,
 423   OP_STR_POS,
 424   OP_LDR_POS,
 425   OP_STRF_POS,
 426   OP_LDRF_POS,
 427   OP_LDRSW_POS,
 428   OP_PRFM_POS,
 429
 430   OP_STURB,
 431   OP_LDURB,
 432   OP_LDURSB,
 433   OP_STURH,
 434   OP_LDURH,
 435   OP_LDURSH,
 436   OP_STUR,
 437   OP_LDUR,
 438   OP_STURV,
 439   OP_LDURV,
 440   OP_LDURSW,
 441   OP_PRFUM,
 442
 443   OP_LDR_LIT,
 444   OP_LDRV_LIT,
 445   OP_LDRSW_LIT,
 446   OP_PRFM_LIT,
 447
 448   OP_ADD,
 449   OP_B,
 450   OP_BL,
 451
 452   OP_MOVN,
 453   OP_MOVZ,
 454   OP_MOVK,
 455
 456   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 457   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 458   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 459
 460   OP_MOV_V,             /* MOV alias for moving vector register.  */
 461
 462   OP_ASR_IMM,
 463   OP_LSR_IMM,
 464   OP_LSL_IMM,
 465
 466   OP_BIC,
 467
 468   OP_UBFX,
 469   OP_BFXIL,
 470   OP_SBFX,
 471   OP_SBFIZ,
 472   OP_BFI,
 473   OP_BFC,               /* ARMv8.2.  */
 474   OP_UBFIZ,
 475   OP_UXTB,
 476   OP_UXTH,
 477   OP_UXTW,
 478
 479   OP_CINC,
 480   OP_CINV,
 481   OP_CNEG,
 482   OP_CSET,
 483   OP_CSETM,
 484
 485   OP_FCVT,
 486   OP_FCVTN,
 487   OP_FCVTN2,
 488   OP_FCVTL,
 489   OP_FCVTL2,
 490   OP_FCVTXN_S,          /* Scalar version.  */
 491
 492   OP_ROR_IMM,
 493
 494   OP_SXTL,
 495   OP_SXTL2,
 496   OP_UXTL,
 497   OP_UXTL2,
 498
 499   OP_TOTAL_NUM,         /* Pseudo.  */
 500 };
 501
 502 /* Maximum number of operands an instruction can have.  */
 503 #define AARCH64_MAX_OPND_NUM 6
 504 /* Maximum number of qualifier sequences an instruction can have.  */
 505 #define AARCH64_MAX_QLF_SEQ_NUM 10
 506 /* Operand qualifier typedef; optimized for the size.  */
 507 typedef unsigned char aarch64_opnd_qualifier_t;
 508 /* Operand qualifier sequence typedef.  */
 509 typedef aarch64_opnd_qualifier_t        \
 510           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 511
 512 /* FIXME: improve the efficiency.  */
 513 static inline bfd_boolean
 514 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 515 {
 516   int i;
 517   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 518     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 519       return FALSE;
 520   return TRUE;
 521 }
 522
 523 /* This structure holds information for a particular opcode.  */
 524
 525 struct aarch64_opcode
 526 {
 527   /* The name of the mnemonic.  */
 528   const char *name;
 529
 530   /* The opcode itself.  Those bits which will be filled in with
 531      operands are zeroes.  */
 532   aarch64_insn opcode;
 533
 534   /* The opcode mask.  This is used by the disassembler.  This is a
 535      mask containing ones indicating those bits which must match the
 536      opcode field, and zeroes indicating those bits which need not
 537      match (and are presumably filled in by operands).  */
 538   aarch64_insn mask;
 539
 540   /* Instruction class.  */
 541   enum aarch64_insn_class iclass;
 542
 543   /* Enumerator identifier.  */
 544   enum aarch64_op op;
 545
 546   /* Which architecture variant provides this instruction.  */
 547   const aarch64_feature_set *avariant;
 548
 549   /* An array of operand codes.  Each code is an index into the
 550      operand table.  They appear in the order which the operands must
 551      appear in assembly code, and are terminated by a zero.  */
 552   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 553
 554   /* A list of operand qualifier code sequence.  Each operand qualifier
 555      code qualifies the corresponding operand code.  Each operand
 556      qualifier sequence specifies a valid opcode variant and related
 557      constraint on operands.  */
 558   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 559
 560   /* Flags providing information about this instruction */
 561   uint32_t flags;
 562
 563   /* If nonzero, this operand and operand 0 are both registers and
 564      are required to have the same register number.  */
 565   unsigned char tied_operand;
 566
 567   /* If non-NULL, a function to verify that a given instruction is valid.  */
 568   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 569 };
 570
 571 typedef struct aarch64_opcode aarch64_opcode;
 572
 573 /* Table describing all the AArch64 opcodes.  */
 574 extern aarch64_opcode aarch64_opcode_table[];
 575
 576 /* Opcode flags.  */
 577 #define F_ALIAS (1 << 0)
 578 #define F_HAS_ALIAS (1 << 1)
 579 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 580    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 581 #define F_P1 (1 << 2)
 582 #define F_P2 (2 << 2)
 583 #define F_P3 (3 << 2)
 584 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 585 #define F_COND (1 << 4)
 586 /* Instruction has the field of 'sf'.  */
 587 #define F_SF (1 << 5)
 588 /* Instruction has the field of 'size:Q'.  */
 589 #define F_SIZEQ (1 << 6)
 590 /* Floating-point instruction has the field of 'type'.  */
 591 #define F_FPTYPE (1 << 7)
 592 /* AdvSIMD scalar instruction has the field of 'size'.  */
 593 #define F_SSIZE (1 << 8)
 594 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 595 #define F_T (1 << 9)
 596 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 597 #define F_GPRSIZE_IN_Q (1 << 10)
 598 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 599 #define F_LDS_SIZE (1 << 11)
 600 /* Optional operand; assume maximum of 1 operand can be optional.  */
 601 #define F_OPD0_OPT (1 << 12)
 602 #define F_OPD1_OPT (2 << 12)
 603 #define F_OPD2_OPT (3 << 12)
 604 #define F_OPD3_OPT (4 << 12)
 605 #define F_OPD4_OPT (5 << 12)
 606 /* Default value for the optional operand when omitted from the assembly.  */
 607 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 608 /* Instruction that is an alias of another instruction needs to be
 609    encoded/decoded by converting it to/from the real form, followed by
 610    the encoding/decoding according to the rules of the real opcode.
 611    This compares to the direct coding using the alias's information.
 612    N.B. this flag requires F_ALIAS to be used together.  */
 613 #define F_CONV (1 << 20)
 614 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 615    friendly pseudo instruction available only in the assembly code (thus will
 616    not show up in the disassembly).  */
 617 #define F_PSEUDO (1 << 21)
 618 /* Instruction has miscellaneous encoding/decoding rules.  */
 619 #define F_MISC (1 << 22)
 620 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 621 #define F_N (1 << 23)
 622 /* Opcode dependent field.  */
 623 #define F_OD(X) (((X) & 0x7) << 24)
 624 /* Instruction has the field of 'sz'.  */
 625 #define F_LSE_SZ (1 << 27)
 626 /* Require an exact qualifier match, even for NIL qualifiers.  */
 627 #define F_STRICT (1ULL << 28)
 628 /* Next bit is 29.  */
 629
 630 static inline bfd_boolean
 631 alias_opcode_p (const aarch64_opcode *opcode)
 632 {
 633   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 634 }
 635
 636 static inline bfd_boolean
 637 opcode_has_alias (const aarch64_opcode *opcode)
 638 {
 639   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 640 }
 641
 642 /* Priority for disassembling preference.  */
 643 static inline int
 644 opcode_priority (const aarch64_opcode *opcode)
 645 {
 646   return (opcode->flags >> 2) & 0x3;
 647 }
 648
 649 static inline bfd_boolean
 650 pseudo_opcode_p (const aarch64_opcode *opcode)
 651 {
 652   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 653 }
 654
 655 static inline bfd_boolean
 656 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 657 {
 658   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 659     ? TRUE : FALSE;
 660 }
 661
 662 static inline aarch64_insn
 663 get_optional_operand_default_value (const aarch64_opcode *opcode)
 664 {
 665   return (opcode->flags >> 15) & 0x1f;
 666 }
 667
 668 static inline unsigned int
 669 get_opcode_dependent_value (const aarch64_opcode *opcode)
 670 {
 671   return (opcode->flags >> 24) & 0x7;
 672 }
 673
 674 static inline bfd_boolean
 675 opcode_has_special_coder (const aarch64_opcode *opcode)
 676 {
 677   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 678           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 679     : FALSE;
 680 }
 681 \f
 682 struct aarch64_name_value_pair
 683 {
 684   const char *  name;
 685   aarch64_insn  value;
 686 };
 687
 688 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 689 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 690 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 691 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 692
 693 typedef struct
 694 {
 695   const char *  name;
 696   aarch64_insn  value;
 697   uint32_t      flags;
 698 } aarch64_sys_reg;
 699
 700 extern const aarch64_sys_reg aarch64_sys_regs [];
 701 extern const aarch64_sys_reg aarch64_pstatefields [];
 702 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 703 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 704                                                 const aarch64_sys_reg *);
 705 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 706                                                     const aarch64_sys_reg *);
 707
 708 typedef struct
 709 {
 710   const char *name;
 711   uint32_t value;
 712   uint32_t flags ;
 713 } aarch64_sys_ins_reg;
 714
 715 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 716 extern bfd_boolean
 717 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 718                                  const aarch64_sys_ins_reg *);
 719
 720 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 721 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 722 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 723 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 724
 725 /* Shift/extending operator kinds.
 726    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 727 enum aarch64_modifier_kind
 728 {
 729   AARCH64_MOD_NONE,
 730   AARCH64_MOD_MSL,
 731   AARCH64_MOD_ROR,
 732   AARCH64_MOD_ASR,
 733   AARCH64_MOD_LSR,
 734   AARCH64_MOD_LSL,
 735   AARCH64_MOD_UXTB,
 736   AARCH64_MOD_UXTH,
 737   AARCH64_MOD_UXTW,
 738   AARCH64_MOD_UXTX,
 739   AARCH64_MOD_SXTB,
 740   AARCH64_MOD_SXTH,
 741   AARCH64_MOD_SXTW,
 742   AARCH64_MOD_SXTX,
 743 };
 744
 745 bfd_boolean
 746 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 747
 748 enum aarch64_modifier_kind
 749 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 750 /* Condition.  */
 751
 752 typedef struct
 753 {
 754   /* A list of names with the first one as the disassembly preference;
 755      terminated by NULL if fewer than 3.  */
 756   const char *names[3];
 757   aarch64_insn value;
 758 } aarch64_cond;
 759
 760 extern const aarch64_cond aarch64_conds[16];
 761
 762 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 763 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 764 \f
 765 /* Structure representing an operand.  */
 766
 767 struct aarch64_opnd_info
 768 {
 769   enum aarch64_opnd type;
 770   aarch64_opnd_qualifier_t qualifier;
 771   int idx;
 772
 773   union
 774     {
 775       struct
 776         {
 777           unsigned regno;
 778         } reg;
 779       struct
 780         {
 781           unsigned int regno;
 782           int64_t index;
 783         } reglane;
 784       /* e.g. LVn.  */
 785       struct
 786         {
 787           unsigned first_regno : 5;
 788           unsigned num_regs : 3;
 789           /* 1 if it is a list of reg element.  */
 790           unsigned has_index : 1;
 791           /* Lane index; valid only when has_index is 1.  */
 792           int64_t index;
 793         } reglist;
 794       /* e.g. immediate or pc relative address offset.  */
 795       struct
 796         {
 797           int64_t value;
 798           unsigned is_fp : 1;
 799         } imm;
 800       /* e.g. address in STR (register offset).  */
 801       struct
 802         {
 803           unsigned base_regno;
 804           struct
 805             {
 806               union
 807                 {
 808                   int imm;
 809                   unsigned regno;
 810                 };
 811               unsigned is_reg;
 812             } offset;
 813           unsigned pcrel : 1;           /* PC-relative.  */
 814           unsigned writeback : 1;
 815           unsigned preind : 1;          /* Pre-indexed.  */
 816           unsigned postind : 1;         /* Post-indexed.  */
 817         } addr;
 818       const aarch64_cond *cond;
 819       /* The encoding of the system register.  */
 820       aarch64_insn sysreg;
 821       /* The encoding of the PSTATE field.  */
 822       aarch64_insn pstatefield;
 823       const aarch64_sys_ins_reg *sysins_op;
 824       const struct aarch64_name_value_pair *barrier;
 825       const struct aarch64_name_value_pair *hint_option;
 826       const struct aarch64_name_value_pair *prfop;
 827     };
 828
 829   /* Operand shifter; in use when the operand is a register offset address,
 830      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 831   struct
 832     {
 833       enum aarch64_modifier_kind kind;
 834       int amount;
 835       unsigned operator_present: 1;     /* Only valid during encoding.  */
 836       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 837       unsigned amount_present: 1;
 838     } shifter;
 839
 840   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 841                            to be done on it.  In some (but not all) of these
 842                            cases, we need to tell libopcodes to skip the
 843                            constraint checking and the encoding for this
 844                            operand, so that the libopcodes can pick up the
 845                            right opcode before the operand is fixed-up.  This
 846                            flag should only be used during the
 847                            assembling/encoding.  */
 848   unsigned present:1;   /* Whether this operand is present in the assembly
 849                            line; not used during the disassembly.  */
 850 };
 851
 852 typedef struct aarch64_opnd_info aarch64_opnd_info;
 853
 854 /* Structure representing an instruction.
 855
 856    It is used during both the assembling and disassembling.  The assembler
 857    fills an aarch64_inst after a successful parsing and then passes it to the
 858    encoding routine to do the encoding.  During the disassembling, the
 859    disassembler calls the decoding routine to decode a binary instruction; on a
 860    successful return, such a structure will be filled with information of the
 861    instruction; then the disassembler uses the information to print out the
 862    instruction.  */
 863
 864 struct aarch64_inst
 865 {
 866   /* The value of the binary instruction.  */
 867   aarch64_insn value;
 868
 869   /* Corresponding opcode entry.  */
 870   const aarch64_opcode *opcode;
 871
 872   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 873   const aarch64_cond *cond;
 874
 875   /* Operands information.  */
 876   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 877 };
 878
 879 typedef struct aarch64_inst aarch64_inst;
 880 \f
 881 /* Diagnosis related declaration and interface.  */
 882
 883 /* Operand error kind enumerators.
 884
 885    AARCH64_OPDE_RECOVERABLE
 886      Less severe error found during the parsing, very possibly because that
 887      GAS has picked up a wrong instruction template for the parsing.
 888
 889    AARCH64_OPDE_SYNTAX_ERROR
 890      General syntax error; it can be either a user error, or simply because
 891      that GAS is trying a wrong instruction template.
 892
 893    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 894      Definitely a user syntax error.
 895
 896    AARCH64_OPDE_INVALID_VARIANT
 897      No syntax error, but the operands are not a valid combination, e.g.
 898      FMOV D0,S0
 899
 900    AARCH64_OPDE_UNTIED_OPERAND
 901      The asm failed to use the same register for a destination operand
 902      and a tied source operand.
 903
 904    AARCH64_OPDE_OUT_OF_RANGE
 905      Error about some immediate value out of a valid range.
 906
 907    AARCH64_OPDE_UNALIGNED
 908      Error about some immediate value not properly aligned (i.e. not being a
 909      multiple times of a certain value).
 910
 911    AARCH64_OPDE_REG_LIST
 912      Error about the register list operand having unexpected number of
 913      registers.
 914
 915    AARCH64_OPDE_OTHER_ERROR
 916      Error of the highest severity and used for any severe issue that does not
 917      fall into any of the above categories.
 918
 919    The enumerators are only interesting to GAS.  They are declared here (in
 920    libopcodes) because that some errors are detected (and then notified to GAS)
 921    by libopcodes (rather than by GAS solely).
 922
 923    The first three errors are only deteced by GAS while the
 924    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 925    only libopcodes has the information about the valid variants of each
 926    instruction.
 927
 928    The enumerators have an increasing severity.  This is helpful when there are
 929    multiple instruction templates available for a given mnemonic name (e.g.
 930    FMOV); this mechanism will help choose the most suitable template from which
 931    the generated diagnostics can most closely describe the issues, if any.  */
 932
 933 enum aarch64_operand_error_kind
 934 {
 935   AARCH64_OPDE_NIL,
 936   AARCH64_OPDE_RECOVERABLE,
 937   AARCH64_OPDE_SYNTAX_ERROR,
 938   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 939   AARCH64_OPDE_INVALID_VARIANT,
 940   AARCH64_OPDE_UNTIED_OPERAND,
 941   AARCH64_OPDE_OUT_OF_RANGE,
 942   AARCH64_OPDE_UNALIGNED,
 943   AARCH64_OPDE_REG_LIST,
 944   AARCH64_OPDE_OTHER_ERROR
 945 };
 946
 947 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 948 struct aarch64_operand_error
 949 {
 950   enum aarch64_operand_error_kind kind;
 951   int index;
 952   const char *error;
 953   int data[3];  /* Some data for extra information.  */
 954 };
 955
 956 typedef struct aarch64_operand_error aarch64_operand_error;
 957
 958 /* Encoding entrypoint.  */
 959
 960 extern int
 961 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 962                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 963                        aarch64_operand_error *);
 964
 965 extern const aarch64_opcode *
 966 aarch64_replace_opcode (struct aarch64_inst *,
 967                         const aarch64_opcode *);
 968
 969 /* Given the opcode enumerator OP, return the pointer to the corresponding
 970    opcode entry.  */
 971
 972 extern const aarch64_opcode *
 973 aarch64_get_opcode (enum aarch64_op);
 974
 975 /* Generate the string representation of an operand.  */
 976 extern void
 977 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 978                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 979
 980 /* Miscellaneous interface.  */
 981
 982 extern int
 983 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 984
 985 extern aarch64_opnd_qualifier_t
 986 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 987                                 const aarch64_opnd_qualifier_t, int);
 988
 989 extern int
 990 aarch64_num_of_operands (const aarch64_opcode *);
 991
 992 extern int
 993 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 994
 995 extern int
 996 aarch64_zero_register_p (const aarch64_opnd_info *);
 997
 998 extern int
 999 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1000
1001 /* Given an operand qualifier, return the expected data element size
1002    of a qualified operand.  */
1003 extern unsigned char
1004 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1005
1006 extern enum aarch64_operand_class
1007 aarch64_get_operand_class (enum aarch64_opnd);
1008
1009 extern const char *
1010 aarch64_get_operand_name (enum aarch64_opnd);
1011
1012 extern const char *
1013 aarch64_get_operand_desc (enum aarch64_opnd);
1014
1015 #ifdef DEBUG_AARCH64
1016 extern int debug_dump;
1017
1018 extern void
1019 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1020
1021 #define DEBUG_TRACE(M, ...)                                     \
1022   {                                                             \
1023     if (debug_dump)                                             \
1024       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1025   }
1026
1027 #define DEBUG_TRACE_IF(C, M, ...)                               \
1028   {                                                             \
1029     if (debug_dump && (C))                                      \
1030       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1031   }
1032 #else  /* !DEBUG_AARCH64 */
1033 #define DEBUG_TRACE(M, ...) ;
1034 #define DEBUG_TRACE_IF(C, M, ...) ;
1035 #endif /* DEBUG_AARCH64 */
1036
1037 #ifdef __cplusplus
1038 }
1039 #endif
1040
1041 #endif /* OPCODE_AARCH64_H */