include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Flag Manipulation insns.  */
  68 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  69 /* FRINT[32,64][Z,X] insns.  */
  70 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  71 /* SB instruction.  */
  72 #define AARCH64_FEATURE_SB              0x10000000000ULL
  73 /* Execution and Data Prediction Restriction instructions.  */
  74 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  75 /* DC CVADP.  */
  76 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  77 /* Random Number instructions.  */
  78 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  79 /* BTI instructions.  */
  80 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  81 /* SCXTNUM_ELx.  */
  82 #define AARCH64_FEATURE_SCXTNUM         0x200000000000ULL
  83 /* ID_PFR2 instructions.  */
  84 #define AARCH64_FEATURE_ID_PFR2         0x400000000000ULL
  85 /* SSBS mechanism enabled.  */
  86 #define AARCH64_FEATURE_SSBS            0x800000000000ULL
  87 /* Memory Tagging Extension.  */
  88 #define AARCH64_FEATURE_MEMTAG          0x1000000000000ULL
  89 /* Transactional Memory Extension.  */
  90 #define AARCH64_FEATURE_TME             0x2000000000000ULL
  91
  92 /* SVE2 instructions.  */
  93 #define AARCH64_FEATURE_SVE2            0x000000010
  94 #define AARCH64_FEATURE_SVE2_AES                0x000000080
  95 #define AARCH64_FEATURE_SVE2_BITPERM    0x000000100
  96 #define AARCH64_FEATURE_SVE2_SM4                0x000000200
  97 #define AARCH64_FEATURE_SVE2_SHA3       0x000000400
  98
  99 /* Architectures are the sum of the base and extensions.  */
 100 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
 101                                                  AARCH64_FEATURE_FP  \
 102                                                  | AARCH64_FEATURE_SIMD)
 103 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 104                                                  AARCH64_FEATURE_CRC    \
 105                                                  | AARCH64_FEATURE_V8_1 \
 106                                                  | AARCH64_FEATURE_LSE  \
 107                                                  | AARCH64_FEATURE_PAN  \
 108                                                  | AARCH64_FEATURE_LOR  \
 109                                                  | AARCH64_FEATURE_RDMA)
 110 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 111                                                  AARCH64_FEATURE_V8_2   \
 112                                                  | AARCH64_FEATURE_RAS)
 113 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 114                                                  AARCH64_FEATURE_V8_3   \
 115                                                  | AARCH64_FEATURE_RCPC \
 116                                                  | AARCH64_FEATURE_COMPNUM)
 117 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 118                                                  AARCH64_FEATURE_V8_4   \
 119                                                  | AARCH64_FEATURE_DOTPROD \
 120                                                  | AARCH64_FEATURE_F16_FML)
 121 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 122                                                  AARCH64_FEATURE_V8_5   \
 123                                                  | AARCH64_FEATURE_FLAGMANIP \
 124                                                  | AARCH64_FEATURE_FRINTTS \
 125                                                  | AARCH64_FEATURE_SB   \
 126                                                  | AARCH64_FEATURE_PREDRES \
 127                                                  | AARCH64_FEATURE_CVADP \
 128                                                  | AARCH64_FEATURE_BTI  \
 129                                                  | AARCH64_FEATURE_SCXTNUM \
 130                                                  | AARCH64_FEATURE_ID_PFR2 \
 131                                                  | AARCH64_FEATURE_SSBS)
 132
 133
 134 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 135 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 136
 137 /* CPU-specific features.  */
 138 typedef unsigned long long aarch64_feature_set;
 139
 140 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 141   ((~(CPU) & (FEAT)) == 0)
 142
 143 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 144   (((CPU) & (FEAT)) != 0)
 145
 146 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 147   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 148
 149 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 150   do                                            \
 151     {                                           \
 152       (TARG) = (F1) | (F2);                     \
 153     }                                           \
 154   while (0)
 155
 156 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 157   do                                            \
 158     {                                           \
 159       (TARG) = (F1) &~ (F2);                    \
 160     }                                           \
 161   while (0)
 162
 163 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 164
 165 enum aarch64_operand_class
 166 {
 167   AARCH64_OPND_CLASS_NIL,
 168   AARCH64_OPND_CLASS_INT_REG,
 169   AARCH64_OPND_CLASS_MODIFIED_REG,
 170   AARCH64_OPND_CLASS_FP_REG,
 171   AARCH64_OPND_CLASS_SIMD_REG,
 172   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 173   AARCH64_OPND_CLASS_SISD_REG,
 174   AARCH64_OPND_CLASS_SIMD_REGLIST,
 175   AARCH64_OPND_CLASS_SVE_REG,
 176   AARCH64_OPND_CLASS_PRED_REG,
 177   AARCH64_OPND_CLASS_ADDRESS,
 178   AARCH64_OPND_CLASS_IMMEDIATE,
 179   AARCH64_OPND_CLASS_SYSTEM,
 180   AARCH64_OPND_CLASS_COND,
 181 };
 182
 183 /* Operand code that helps both parsing and coding.
 184    Keep AARCH64_OPERANDS synced.  */
 185
 186 enum aarch64_opnd
 187 {
 188   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 189
 190   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 191   AARCH64_OPND_Rn,      /* Integer register as source.  */
 192   AARCH64_OPND_Rm,      /* Integer register as source.  */
 193   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 194   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 195   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 196   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 197   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 198   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 199
 200   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 201   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 202   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 203   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 204   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 205   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 206
 207   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 208   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 209   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 210   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 211   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 212   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 213
 214   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 215   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 216   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 217
 218   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 219   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 220   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 221   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 222   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 223   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 224   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 225   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 226   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 227   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 228                            qualifier is S_H.  */
 229   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 230   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 231   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 232                            structure to all lanes.  */
 233   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 234
 235   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 236   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 237
 238   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 239   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 240   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 241   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 242   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 243   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 244   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 245   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 246                            (no encoding).  */
 247   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 248   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 249   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 250   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 251   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 252   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 253   AARCH64_OPND_IMM,     /* Immediate.  */
 254   AARCH64_OPND_IMM_2,   /* Immediate.  */
 255   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 256   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 257   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 258   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 259   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 260   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 261   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 262   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 263   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 264   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 265   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 266                            each condition flag.  */
 267
 268   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 269   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 270   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 271   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 272   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 273   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 274   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 275   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 276
 277   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 278   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 279
 280   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 281   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 282   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 283   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 284   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 285
 286   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 287   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 288   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 289   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 290   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 291                                    negative or unaligned and there is
 292                                    no writeback allowed.  This operand code
 293                                    is only used to support the programmer-
 294                                    friendly feature of using LDR/STR as the
 295                                    the mnemonic name for LDUR/STUR instructions
 296                                    wherever there is no ambiguity.  */
 297   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 298   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 299                                    16) immediate.  */
 300   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 301   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 302                                    16) immediate.  */
 303   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 304   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 305   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 306
 307   AARCH64_OPND_SYSREG,          /* System register operand.  */
 308   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 309   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 310   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 311   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 312   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 313   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 314   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 315   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 316   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 317   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 318   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 319
 320   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 321   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 322   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 323   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 324   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 325   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 326   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 327   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 328   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 329   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 330   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 331   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 332   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 333   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 334   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 335   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 336   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 337   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 338   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 339   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 340   AARCH64_OPND_SVE_ADDR_ZX,         /* SVE [Zn.<T>{, <Xm>}].  */
 341   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 342   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 343   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 344   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 345   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 346                                        Bit 14 controls S/U choice.  */
 347   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 348                                        Bit 22 controls S/U choice.  */
 349   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 350                                        Bit 14 controls S/U choice.  */
 351   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 352                                        Bit 22 controls S/U choice.  */
 353   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 354                                        Bit 14 controls S/U choice.  */
 355   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 356                                        Bit 22 controls S/U choice.  */
 357   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 358                                        Bit 14 controls S/U choice.  */
 359   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 360                                        Bit 22 controls S/U choice.  */
 361   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 362   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 363   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 364   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 365   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 366   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 367   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 368   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 369   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 370   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 371   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 372   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 373   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 374   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 375   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 376   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 377   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 378   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 379   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 380   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 381   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 382   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 383   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 384   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 385   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 386   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 387   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 388   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 389   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 390   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 391   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 392   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 393   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 394   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 395   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 396   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 397   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,    /* SVE 3 bit shift right unpred.  */
 398   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 399   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 400   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 401   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 402   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 403   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 404   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 405   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 406   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 407   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 408   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 409   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 410   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 411   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 412   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 413   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 414   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 415   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 416   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 417   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
 418   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 419   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 420   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 421   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 422   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 423   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 424   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 425   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 426 };
 427
 428 /* Qualifier constrains an operand.  It either specifies a variant of an
 429    operand type or limits values available to an operand type.
 430
 431    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 432
 433 enum aarch64_opnd_qualifier
 434 {
 435   /* Indicating no further qualification on an operand.  */
 436   AARCH64_OPND_QLF_NIL,
 437
 438   /* Qualifying an operand which is a general purpose (integer) register;
 439      indicating the operand data size or a specific register.  */
 440   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 441   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 442   AARCH64_OPND_QLF_WSP, /* WSP.  */
 443   AARCH64_OPND_QLF_SP,  /* SP.  */
 444
 445   /* Qualifying an operand which is a floating-point register, a SIMD
 446      vector element or a SIMD vector element list; indicating operand data
 447      size or the size of each SIMD vector element in the case of a SIMD
 448      vector element list.
 449      These qualifiers are also used to qualify an address operand to
 450      indicate the size of data element a load/store instruction is
 451      accessing.
 452      They are also used for the immediate shift operand in e.g. SSHR.  Such
 453      a use is only for the ease of operand encoding/decoding and qualifier
 454      sequence matching; such a use should not be applied widely; use the value
 455      constraint qualifiers for immediate operands wherever possible.  */
 456   AARCH64_OPND_QLF_S_B,
 457   AARCH64_OPND_QLF_S_H,
 458   AARCH64_OPND_QLF_S_S,
 459   AARCH64_OPND_QLF_S_D,
 460   AARCH64_OPND_QLF_S_Q,
 461   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 462      are selected by the instruction.  Other than that it has no difference
 463      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 464      reasons and is an exception from normal AArch64 disassembly scheme.  */
 465   AARCH64_OPND_QLF_S_4B,
 466
 467   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 468      register list; indicating register shape.
 469      They are also used for the immediate shift operand in e.g. SSHR.  Such
 470      a use is only for the ease of operand encoding/decoding and qualifier
 471      sequence matching; such a use should not be applied widely; use the value
 472      constraint qualifiers for immediate operands wherever possible.  */
 473   AARCH64_OPND_QLF_V_4B,
 474   AARCH64_OPND_QLF_V_8B,
 475   AARCH64_OPND_QLF_V_16B,
 476   AARCH64_OPND_QLF_V_2H,
 477   AARCH64_OPND_QLF_V_4H,
 478   AARCH64_OPND_QLF_V_8H,
 479   AARCH64_OPND_QLF_V_2S,
 480   AARCH64_OPND_QLF_V_4S,
 481   AARCH64_OPND_QLF_V_1D,
 482   AARCH64_OPND_QLF_V_2D,
 483   AARCH64_OPND_QLF_V_1Q,
 484
 485   AARCH64_OPND_QLF_P_Z,
 486   AARCH64_OPND_QLF_P_M,
 487
 488   /* Used in scaled signed immediate that are scaled by a Tag granule
 489      like in stg, st2g, etc.   */
 490   AARCH64_OPND_QLF_imm_tag,
 491
 492   /* Constraint on value.  */
 493   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 494   AARCH64_OPND_QLF_imm_0_7,
 495   AARCH64_OPND_QLF_imm_0_15,
 496   AARCH64_OPND_QLF_imm_0_31,
 497   AARCH64_OPND_QLF_imm_0_63,
 498   AARCH64_OPND_QLF_imm_1_32,
 499   AARCH64_OPND_QLF_imm_1_64,
 500
 501   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 502      or shift-ones.  */
 503   AARCH64_OPND_QLF_LSL,
 504   AARCH64_OPND_QLF_MSL,
 505
 506   /* Special qualifier helping retrieve qualifier information during the
 507      decoding time (currently not in use).  */
 508   AARCH64_OPND_QLF_RETRIEVE,
 509 };
 510 \f
 511 /* Instruction class.  */
 512
 513 enum aarch64_insn_class
 514 {
 515   addsub_carry,
 516   addsub_ext,
 517   addsub_imm,
 518   addsub_shift,
 519   asimdall,
 520   asimddiff,
 521   asimdelem,
 522   asimdext,
 523   asimdimm,
 524   asimdins,
 525   asimdmisc,
 526   asimdperm,
 527   asimdsame,
 528   asimdshf,
 529   asimdtbl,
 530   asisddiff,
 531   asisdelem,
 532   asisdlse,
 533   asisdlsep,
 534   asisdlso,
 535   asisdlsop,
 536   asisdmisc,
 537   asisdone,
 538   asisdpair,
 539   asisdsame,
 540   asisdshf,
 541   bitfield,
 542   branch_imm,
 543   branch_reg,
 544   compbranch,
 545   condbranch,
 546   condcmp_imm,
 547   condcmp_reg,
 548   condsel,
 549   cryptoaes,
 550   cryptosha2,
 551   cryptosha3,
 552   dp_1src,
 553   dp_2src,
 554   dp_3src,
 555   exception,
 556   extract,
 557   float2fix,
 558   float2int,
 559   floatccmp,
 560   floatcmp,
 561   floatdp1,
 562   floatdp2,
 563   floatdp3,
 564   floatimm,
 565   floatsel,
 566   ldst_immpost,
 567   ldst_immpre,
 568   ldst_imm9,    /* immpost or immpre */
 569   ldst_imm10,   /* LDRAA/LDRAB */
 570   ldst_pos,
 571   ldst_regoff,
 572   ldst_unpriv,
 573   ldst_unscaled,
 574   ldstexcl,
 575   ldstnapair_offs,
 576   ldstpair_off,
 577   ldstpair_indexed,
 578   loadlit,
 579   log_imm,
 580   log_shift,
 581   lse_atomic,
 582   movewide,
 583   pcreladdr,
 584   ic_system,
 585   sve_cpy,
 586   sve_index,
 587   sve_limm,
 588   sve_misc,
 589   sve_movprfx,
 590   sve_pred_zm,
 591   sve_shift_pred,
 592   sve_shift_unpred,
 593   sve_size_bhs,
 594   sve_size_bhsd,
 595   sve_size_hsd,
 596   sve_size_hsd2,
 597   sve_size_sd,
 598   sve_size_bh,
 599   sve_size_sd2,
 600   sve_size_013,
 601   sve_shift_tsz_hsd,
 602   testbranch,
 603   cryptosm3,
 604   cryptosm4,
 605   dotproduct,
 606 };
 607
 608 /* Opcode enumerators.  */
 609
 610 enum aarch64_op
 611 {
 612   OP_NIL,
 613   OP_STRB_POS,
 614   OP_LDRB_POS,
 615   OP_LDRSB_POS,
 616   OP_STRH_POS,
 617   OP_LDRH_POS,
 618   OP_LDRSH_POS,
 619   OP_STR_POS,
 620   OP_LDR_POS,
 621   OP_STRF_POS,
 622   OP_LDRF_POS,
 623   OP_LDRSW_POS,
 624   OP_PRFM_POS,
 625
 626   OP_STURB,
 627   OP_LDURB,
 628   OP_LDURSB,
 629   OP_STURH,
 630   OP_LDURH,
 631   OP_LDURSH,
 632   OP_STUR,
 633   OP_LDUR,
 634   OP_STURV,
 635   OP_LDURV,
 636   OP_LDURSW,
 637   OP_PRFUM,
 638
 639   OP_LDR_LIT,
 640   OP_LDRV_LIT,
 641   OP_LDRSW_LIT,
 642   OP_PRFM_LIT,
 643
 644   OP_ADD,
 645   OP_B,
 646   OP_BL,
 647
 648   OP_MOVN,
 649   OP_MOVZ,
 650   OP_MOVK,
 651
 652   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 653   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 654   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 655
 656   OP_MOV_V,             /* MOV alias for moving vector register.  */
 657
 658   OP_ASR_IMM,
 659   OP_LSR_IMM,
 660   OP_LSL_IMM,
 661
 662   OP_BIC,
 663
 664   OP_UBFX,
 665   OP_BFXIL,
 666   OP_SBFX,
 667   OP_SBFIZ,
 668   OP_BFI,
 669   OP_BFC,               /* ARMv8.2.  */
 670   OP_UBFIZ,
 671   OP_UXTB,
 672   OP_UXTH,
 673   OP_UXTW,
 674
 675   OP_CINC,
 676   OP_CINV,
 677   OP_CNEG,
 678   OP_CSET,
 679   OP_CSETM,
 680
 681   OP_FCVT,
 682   OP_FCVTN,
 683   OP_FCVTN2,
 684   OP_FCVTL,
 685   OP_FCVTL2,
 686   OP_FCVTXN_S,          /* Scalar version.  */
 687
 688   OP_ROR_IMM,
 689
 690   OP_SXTL,
 691   OP_SXTL2,
 692   OP_UXTL,
 693   OP_UXTL2,
 694
 695   OP_MOV_P_P,
 696   OP_MOV_Z_P_Z,
 697   OP_MOV_Z_V,
 698   OP_MOV_Z_Z,
 699   OP_MOV_Z_Zi,
 700   OP_MOVM_P_P_P,
 701   OP_MOVS_P_P,
 702   OP_MOVZS_P_P_P,
 703   OP_MOVZ_P_P_P,
 704   OP_NOTS_P_P_P_Z,
 705   OP_NOT_P_P_P_Z,
 706
 707   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 708
 709   OP_TOTAL_NUM,         /* Pseudo.  */
 710 };
 711
 712 /* Error types.  */
 713 enum err_type
 714 {
 715   ERR_OK,
 716   ERR_UND,
 717   ERR_UNP,
 718   ERR_NYI,
 719   ERR_VFI,
 720   ERR_NR_ENTRIES
 721 };
 722
 723 /* Maximum number of operands an instruction can have.  */
 724 #define AARCH64_MAX_OPND_NUM 6
 725 /* Maximum number of qualifier sequences an instruction can have.  */
 726 #define AARCH64_MAX_QLF_SEQ_NUM 10
 727 /* Operand qualifier typedef; optimized for the size.  */
 728 typedef unsigned char aarch64_opnd_qualifier_t;
 729 /* Operand qualifier sequence typedef.  */
 730 typedef aarch64_opnd_qualifier_t        \
 731           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 732
 733 /* FIXME: improve the efficiency.  */
 734 static inline bfd_boolean
 735 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 736 {
 737   int i;
 738   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 739     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 740       return FALSE;
 741   return TRUE;
 742 }
 743
 744 /*  Forward declare error reporting type.  */
 745 typedef struct aarch64_operand_error aarch64_operand_error;
 746 /* Forward declare instruction sequence type.  */
 747 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 748 /* Forward declare instruction definition.  */
 749 typedef struct aarch64_inst aarch64_inst;
 750
 751 /* This structure holds information for a particular opcode.  */
 752
 753 struct aarch64_opcode
 754 {
 755   /* The name of the mnemonic.  */
 756   const char *name;
 757
 758   /* The opcode itself.  Those bits which will be filled in with
 759      operands are zeroes.  */
 760   aarch64_insn opcode;
 761
 762   /* The opcode mask.  This is used by the disassembler.  This is a
 763      mask containing ones indicating those bits which must match the
 764      opcode field, and zeroes indicating those bits which need not
 765      match (and are presumably filled in by operands).  */
 766   aarch64_insn mask;
 767
 768   /* Instruction class.  */
 769   enum aarch64_insn_class iclass;
 770
 771   /* Enumerator identifier.  */
 772   enum aarch64_op op;
 773
 774   /* Which architecture variant provides this instruction.  */
 775   const aarch64_feature_set *avariant;
 776
 777   /* An array of operand codes.  Each code is an index into the
 778      operand table.  They appear in the order which the operands must
 779      appear in assembly code, and are terminated by a zero.  */
 780   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 781
 782   /* A list of operand qualifier code sequence.  Each operand qualifier
 783      code qualifies the corresponding operand code.  Each operand
 784      qualifier sequence specifies a valid opcode variant and related
 785      constraint on operands.  */
 786   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 787
 788   /* Flags providing information about this instruction */
 789   uint64_t flags;
 790
 791   /* Extra constraints on the instruction that the verifier checks.  */
 792   uint32_t constraints;
 793
 794   /* If nonzero, this operand and operand 0 are both registers and
 795      are required to have the same register number.  */
 796   unsigned char tied_operand;
 797
 798   /* If non-NULL, a function to verify that a given instruction is valid.  */
 799   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 800                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 801                               struct aarch64_instr_sequence *);
 802 };
 803
 804 typedef struct aarch64_opcode aarch64_opcode;
 805
 806 /* Table describing all the AArch64 opcodes.  */
 807 extern aarch64_opcode aarch64_opcode_table[];
 808
 809 /* Opcode flags.  */
 810 #define F_ALIAS (1 << 0)
 811 #define F_HAS_ALIAS (1 << 1)
 812 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 813    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 814 #define F_P1 (1 << 2)
 815 #define F_P2 (2 << 2)
 816 #define F_P3 (3 << 2)
 817 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 818 #define F_COND (1 << 4)
 819 /* Instruction has the field of 'sf'.  */
 820 #define F_SF (1 << 5)
 821 /* Instruction has the field of 'size:Q'.  */
 822 #define F_SIZEQ (1 << 6)
 823 /* Floating-point instruction has the field of 'type'.  */
 824 #define F_FPTYPE (1 << 7)
 825 /* AdvSIMD scalar instruction has the field of 'size'.  */
 826 #define F_SSIZE (1 << 8)
 827 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 828 #define F_T (1 << 9)
 829 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 830 #define F_GPRSIZE_IN_Q (1 << 10)
 831 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 832 #define F_LDS_SIZE (1 << 11)
 833 /* Optional operand; assume maximum of 1 operand can be optional.  */
 834 #define F_OPD0_OPT (1 << 12)
 835 #define F_OPD1_OPT (2 << 12)
 836 #define F_OPD2_OPT (3 << 12)
 837 #define F_OPD3_OPT (4 << 12)
 838 #define F_OPD4_OPT (5 << 12)
 839 /* Default value for the optional operand when omitted from the assembly.  */
 840 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 841 /* Instruction that is an alias of another instruction needs to be
 842    encoded/decoded by converting it to/from the real form, followed by
 843    the encoding/decoding according to the rules of the real opcode.
 844    This compares to the direct coding using the alias's information.
 845    N.B. this flag requires F_ALIAS to be used together.  */
 846 #define F_CONV (1 << 20)
 847 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 848    friendly pseudo instruction available only in the assembly code (thus will
 849    not show up in the disassembly).  */
 850 #define F_PSEUDO (1 << 21)
 851 /* Instruction has miscellaneous encoding/decoding rules.  */
 852 #define F_MISC (1 << 22)
 853 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 854 #define F_N (1 << 23)
 855 /* Opcode dependent field.  */
 856 #define F_OD(X) (((X) & 0x7) << 24)
 857 /* Instruction has the field of 'sz'.  */
 858 #define F_LSE_SZ (1 << 27)
 859 /* Require an exact qualifier match, even for NIL qualifiers.  */
 860 #define F_STRICT (1ULL << 28)
 861 /* This system instruction is used to read system registers.  */
 862 #define F_SYS_READ (1ULL << 29)
 863 /* This system instruction is used to write system registers.  */
 864 #define F_SYS_WRITE (1ULL << 30)
 865 /* This instruction has an extra constraint on it that imposes a requirement on
 866    subsequent instructions.  */
 867 #define F_SCAN (1ULL << 31)
 868 /* Next bit is 32.  */
 869
 870 /* Instruction constraints.  */
 871 /* This instruction has a predication constraint on the instruction at PC+4.  */
 872 #define C_SCAN_MOVPRFX (1U << 0)
 873 /* This instruction's operation width is determined by the operand with the
 874    largest element size.  */
 875 #define C_MAX_ELEM (1U << 1)
 876 /* Next bit is 2.  */
 877
 878 static inline bfd_boolean
 879 alias_opcode_p (const aarch64_opcode *opcode)
 880 {
 881   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 882 }
 883
 884 static inline bfd_boolean
 885 opcode_has_alias (const aarch64_opcode *opcode)
 886 {
 887   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 888 }
 889
 890 /* Priority for disassembling preference.  */
 891 static inline int
 892 opcode_priority (const aarch64_opcode *opcode)
 893 {
 894   return (opcode->flags >> 2) & 0x3;
 895 }
 896
 897 static inline bfd_boolean
 898 pseudo_opcode_p (const aarch64_opcode *opcode)
 899 {
 900   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 901 }
 902
 903 static inline bfd_boolean
 904 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 905 {
 906   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 907     ? TRUE : FALSE;
 908 }
 909
 910 static inline aarch64_insn
 911 get_optional_operand_default_value (const aarch64_opcode *opcode)
 912 {
 913   return (opcode->flags >> 15) & 0x1f;
 914 }
 915
 916 static inline unsigned int
 917 get_opcode_dependent_value (const aarch64_opcode *opcode)
 918 {
 919   return (opcode->flags >> 24) & 0x7;
 920 }
 921
 922 static inline bfd_boolean
 923 opcode_has_special_coder (const aarch64_opcode *opcode)
 924 {
 925   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 926           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 927     : FALSE;
 928 }
 929 \f
 930 struct aarch64_name_value_pair
 931 {
 932   const char *  name;
 933   aarch64_insn  value;
 934 };
 935
 936 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 937 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 938 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 939 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 940
 941 typedef struct
 942 {
 943   const char *  name;
 944   aarch64_insn  value;
 945   uint32_t      flags;
 946 } aarch64_sys_reg;
 947
 948 extern const aarch64_sys_reg aarch64_sys_regs [];
 949 extern const aarch64_sys_reg aarch64_pstatefields [];
 950 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 951 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 952                                                 const aarch64_sys_reg *);
 953 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 954                                                     const aarch64_sys_reg *);
 955
 956 typedef struct
 957 {
 958   const char *name;
 959   uint32_t value;
 960   uint32_t flags ;
 961 } aarch64_sys_ins_reg;
 962
 963 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 964 extern bfd_boolean
 965 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 966                                  const aarch64_sys_ins_reg *);
 967
 968 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 969 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 970 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 971 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 972 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 973
 974 /* Shift/extending operator kinds.
 975    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 976 enum aarch64_modifier_kind
 977 {
 978   AARCH64_MOD_NONE,
 979   AARCH64_MOD_MSL,
 980   AARCH64_MOD_ROR,
 981   AARCH64_MOD_ASR,
 982   AARCH64_MOD_LSR,
 983   AARCH64_MOD_LSL,
 984   AARCH64_MOD_UXTB,
 985   AARCH64_MOD_UXTH,
 986   AARCH64_MOD_UXTW,
 987   AARCH64_MOD_UXTX,
 988   AARCH64_MOD_SXTB,
 989   AARCH64_MOD_SXTH,
 990   AARCH64_MOD_SXTW,
 991   AARCH64_MOD_SXTX,
 992   AARCH64_MOD_MUL,
 993   AARCH64_MOD_MUL_VL,
 994 };
 995
 996 bfd_boolean
 997 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 998
 999 enum aarch64_modifier_kind
1000 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1001 /* Condition.  */
1002
1003 typedef struct
1004 {
1005   /* A list of names with the first one as the disassembly preference;
1006      terminated by NULL if fewer than 3.  */
1007   const char *names[4];
1008   aarch64_insn value;
1009 } aarch64_cond;
1010
1011 extern const aarch64_cond aarch64_conds[16];
1012
1013 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1014 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1015 \f
1016 /* Structure representing an operand.  */
1017
1018 struct aarch64_opnd_info
1019 {
1020   enum aarch64_opnd type;
1021   aarch64_opnd_qualifier_t qualifier;
1022   int idx;
1023
1024   union
1025     {
1026       struct
1027         {
1028           unsigned regno;
1029         } reg;
1030       struct
1031         {
1032           unsigned int regno;
1033           int64_t index;
1034         } reglane;
1035       /* e.g. LVn.  */
1036       struct
1037         {
1038           unsigned first_regno : 5;
1039           unsigned num_regs : 3;
1040           /* 1 if it is a list of reg element.  */
1041           unsigned has_index : 1;
1042           /* Lane index; valid only when has_index is 1.  */
1043           int64_t index;
1044         } reglist;
1045       /* e.g. immediate or pc relative address offset.  */
1046       struct
1047         {
1048           int64_t value;
1049           unsigned is_fp : 1;
1050         } imm;
1051       /* e.g. address in STR (register offset).  */
1052       struct
1053         {
1054           unsigned base_regno;
1055           struct
1056             {
1057               union
1058                 {
1059                   int imm;
1060                   unsigned regno;
1061                 };
1062               unsigned is_reg;
1063             } offset;
1064           unsigned pcrel : 1;           /* PC-relative.  */
1065           unsigned writeback : 1;
1066           unsigned preind : 1;          /* Pre-indexed.  */
1067           unsigned postind : 1;         /* Post-indexed.  */
1068         } addr;
1069
1070       struct
1071         {
1072           /* The encoding of the system register.  */
1073           aarch64_insn value;
1074
1075           /* The system register flags.  */
1076           uint32_t flags;
1077         } sysreg;
1078
1079       const aarch64_cond *cond;
1080       /* The encoding of the PSTATE field.  */
1081       aarch64_insn pstatefield;
1082       const aarch64_sys_ins_reg *sysins_op;
1083       const struct aarch64_name_value_pair *barrier;
1084       const struct aarch64_name_value_pair *hint_option;
1085       const struct aarch64_name_value_pair *prfop;
1086     };
1087
1088   /* Operand shifter; in use when the operand is a register offset address,
1089      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1090   struct
1091     {
1092       enum aarch64_modifier_kind kind;
1093       unsigned operator_present: 1;     /* Only valid during encoding.  */
1094       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1095       unsigned amount_present: 1;
1096       int64_t amount;
1097     } shifter;
1098
1099   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1100                            to be done on it.  In some (but not all) of these
1101                            cases, we need to tell libopcodes to skip the
1102                            constraint checking and the encoding for this
1103                            operand, so that the libopcodes can pick up the
1104                            right opcode before the operand is fixed-up.  This
1105                            flag should only be used during the
1106                            assembling/encoding.  */
1107   unsigned present:1;   /* Whether this operand is present in the assembly
1108                            line; not used during the disassembly.  */
1109 };
1110
1111 typedef struct aarch64_opnd_info aarch64_opnd_info;
1112
1113 /* Structure representing an instruction.
1114
1115    It is used during both the assembling and disassembling.  The assembler
1116    fills an aarch64_inst after a successful parsing and then passes it to the
1117    encoding routine to do the encoding.  During the disassembling, the
1118    disassembler calls the decoding routine to decode a binary instruction; on a
1119    successful return, such a structure will be filled with information of the
1120    instruction; then the disassembler uses the information to print out the
1121    instruction.  */
1122
1123 struct aarch64_inst
1124 {
1125   /* The value of the binary instruction.  */
1126   aarch64_insn value;
1127
1128   /* Corresponding opcode entry.  */
1129   const aarch64_opcode *opcode;
1130
1131   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1132   const aarch64_cond *cond;
1133
1134   /* Operands information.  */
1135   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1136 };
1137
1138 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1139 #define HINT_OPD_CSYNC  0x11
1140 #define HINT_OPD_C      0x22
1141 #define HINT_OPD_J      0x24
1142 #define HINT_OPD_JC     0x26
1143 #define HINT_OPD_NULL   0x00
1144
1145 \f
1146 /* Diagnosis related declaration and interface.  */
1147
1148 /* Operand error kind enumerators.
1149
1150    AARCH64_OPDE_RECOVERABLE
1151      Less severe error found during the parsing, very possibly because that
1152      GAS has picked up a wrong instruction template for the parsing.
1153
1154    AARCH64_OPDE_SYNTAX_ERROR
1155      General syntax error; it can be either a user error, or simply because
1156      that GAS is trying a wrong instruction template.
1157
1158    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1159      Definitely a user syntax error.
1160
1161    AARCH64_OPDE_INVALID_VARIANT
1162      No syntax error, but the operands are not a valid combination, e.g.
1163      FMOV D0,S0
1164
1165    AARCH64_OPDE_UNTIED_OPERAND
1166      The asm failed to use the same register for a destination operand
1167      and a tied source operand.
1168
1169    AARCH64_OPDE_OUT_OF_RANGE
1170      Error about some immediate value out of a valid range.
1171
1172    AARCH64_OPDE_UNALIGNED
1173      Error about some immediate value not properly aligned (i.e. not being a
1174      multiple times of a certain value).
1175
1176    AARCH64_OPDE_REG_LIST
1177      Error about the register list operand having unexpected number of
1178      registers.
1179
1180    AARCH64_OPDE_OTHER_ERROR
1181      Error of the highest severity and used for any severe issue that does not
1182      fall into any of the above categories.
1183
1184    The enumerators are only interesting to GAS.  They are declared here (in
1185    libopcodes) because that some errors are detected (and then notified to GAS)
1186    by libopcodes (rather than by GAS solely).
1187
1188    The first three errors are only deteced by GAS while the
1189    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1190    only libopcodes has the information about the valid variants of each
1191    instruction.
1192
1193    The enumerators have an increasing severity.  This is helpful when there are
1194    multiple instruction templates available for a given mnemonic name (e.g.
1195    FMOV); this mechanism will help choose the most suitable template from which
1196    the generated diagnostics can most closely describe the issues, if any.  */
1197
1198 enum aarch64_operand_error_kind
1199 {
1200   AARCH64_OPDE_NIL,
1201   AARCH64_OPDE_RECOVERABLE,
1202   AARCH64_OPDE_SYNTAX_ERROR,
1203   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1204   AARCH64_OPDE_INVALID_VARIANT,
1205   AARCH64_OPDE_UNTIED_OPERAND,
1206   AARCH64_OPDE_OUT_OF_RANGE,
1207   AARCH64_OPDE_UNALIGNED,
1208   AARCH64_OPDE_REG_LIST,
1209   AARCH64_OPDE_OTHER_ERROR
1210 };
1211
1212 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1213 struct aarch64_operand_error
1214 {
1215   enum aarch64_operand_error_kind kind;
1216   int index;
1217   const char *error;
1218   int data[3];  /* Some data for extra information.  */
1219   bfd_boolean non_fatal;
1220 };
1221
1222 /* AArch64 sequence structure used to track instructions with F_SCAN
1223    dependencies for both assembler and disassembler.  */
1224 struct aarch64_instr_sequence
1225 {
1226   /* The instruction that caused this sequence to be opened.  */
1227   aarch64_inst *instr;
1228   /* The number of instructions the above instruction allows to be kept in the
1229      sequence before an automatic close is done.  */
1230   int num_insns;
1231   /* The instructions currently added to the sequence.  */
1232   aarch64_inst **current_insns;
1233   /* The number of instructions already in the sequence.  */
1234   int next_insn;
1235 };
1236
1237 /* Encoding entrypoint.  */
1238
1239 extern int
1240 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1241                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1242                        aarch64_operand_error *, aarch64_instr_sequence *);
1243
1244 extern const aarch64_opcode *
1245 aarch64_replace_opcode (struct aarch64_inst *,
1246                         const aarch64_opcode *);
1247
1248 /* Given the opcode enumerator OP, return the pointer to the corresponding
1249    opcode entry.  */
1250
1251 extern const aarch64_opcode *
1252 aarch64_get_opcode (enum aarch64_op);
1253
1254 /* Generate the string representation of an operand.  */
1255 extern void
1256 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1257                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1258                        char **);
1259
1260 /* Miscellaneous interface.  */
1261
1262 extern int
1263 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1264
1265 extern aarch64_opnd_qualifier_t
1266 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1267                                 const aarch64_opnd_qualifier_t, int);
1268
1269 extern bfd_boolean
1270 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1271
1272 extern int
1273 aarch64_num_of_operands (const aarch64_opcode *);
1274
1275 extern int
1276 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1277
1278 extern int
1279 aarch64_zero_register_p (const aarch64_opnd_info *);
1280
1281 extern enum err_type
1282 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1283                      aarch64_operand_error *);
1284
1285 extern void
1286 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1287
1288 /* Given an operand qualifier, return the expected data element size
1289    of a qualified operand.  */
1290 extern unsigned char
1291 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1292
1293 extern enum aarch64_operand_class
1294 aarch64_get_operand_class (enum aarch64_opnd);
1295
1296 extern const char *
1297 aarch64_get_operand_name (enum aarch64_opnd);
1298
1299 extern const char *
1300 aarch64_get_operand_desc (enum aarch64_opnd);
1301
1302 extern bfd_boolean
1303 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1304
1305 #ifdef DEBUG_AARCH64
1306 extern int debug_dump;
1307
1308 extern void
1309 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1310
1311 #define DEBUG_TRACE(M, ...)                                     \
1312   {                                                             \
1313     if (debug_dump)                                             \
1314       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1315   }
1316
1317 #define DEBUG_TRACE_IF(C, M, ...)                               \
1318   {                                                             \
1319     if (debug_dump && (C))                                      \
1320       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1321   }
1322 #else  /* !DEBUG_AARCH64 */
1323 #define DEBUG_TRACE(M, ...) ;
1324 #define DEBUG_TRACE_IF(C, M, ...) ;
1325 #endif /* DEBUG_AARCH64 */
1326
1327 extern const char *const aarch64_sve_pattern_array[32];
1328 extern const char *const aarch64_sve_prfop_array[16];
1329
1330 #ifdef __cplusplus
1331 }
1332 #endif
1333
1334 #endif /* OPCODE_AARCH64_H */