1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn
;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41 #define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
42 #define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43 #define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44 #define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
45 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
46 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
47 #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
48 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
51 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
52 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
53 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
54 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
55 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
56 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
57 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
58 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
59 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
60 #define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
61 #define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
62 #define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
63 #define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
65 #define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
67 /* Flag Manipulation insns. */
68 #define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69 /* FRINT[32,64][Z,X] insns. */
70 #define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
72 #define AARCH64_FEATURE_SB 0x10000000000ULL
73 /* Execution and Data Prediction Restriction instructions. */
74 #define AARCH64_FEATURE_PREDRES 0x20000000000ULL
76 #define AARCH64_FEATURE_CVADP 0x40000000000ULL
77 /* Random Number instructions. */
78 #define AARCH64_FEATURE_RNG 0x80000000000ULL
79 /* BTI instructions. */
80 #define AARCH64_FEATURE_BTI 0x100000000000ULL
82 #define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83 /* ID_PFR2 instructions. */
84 #define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
85 /* SSBS mechanism enabled. */
86 #define AARCH64_FEATURE_SSBS 0x800000000000ULL
87 /* Memory Tagging Extension. */
88 #define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
91 /* Architectures are the sum of the base and extensions. */
92 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
94 | AARCH64_FEATURE_SIMD)
95 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
97 | AARCH64_FEATURE_V8_1 \
98 | AARCH64_FEATURE_LSE \
99 | AARCH64_FEATURE_PAN \
100 | AARCH64_FEATURE_LOR \
101 | AARCH64_FEATURE_RDMA)
102 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
103 AARCH64_FEATURE_V8_2 \
104 | AARCH64_FEATURE_RAS)
105 #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
106 AARCH64_FEATURE_V8_3 \
107 | AARCH64_FEATURE_RCPC \
108 | AARCH64_FEATURE_COMPNUM)
109 #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
110 AARCH64_FEATURE_V8_4 \
111 | AARCH64_FEATURE_DOTPROD \
112 | AARCH64_FEATURE_F16_FML)
113 #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
114 AARCH64_FEATURE_V8_5 \
115 | AARCH64_FEATURE_FLAGMANIP \
116 | AARCH64_FEATURE_FRINTTS \
117 | AARCH64_FEATURE_SB \
118 | AARCH64_FEATURE_PREDRES \
119 | AARCH64_FEATURE_CVADP \
120 | AARCH64_FEATURE_BTI \
121 | AARCH64_FEATURE_SCXTNUM \
122 | AARCH64_FEATURE_ID_PFR2 \
123 | AARCH64_FEATURE_SSBS)
126 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
127 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
129 /* CPU-specific features. */
130 typedef unsigned long long aarch64_feature_set
;
132 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
133 ((~(CPU) & (FEAT)) == 0)
135 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
136 (((CPU) & (FEAT)) != 0)
138 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
139 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
141 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
144 (TARG) = (F1) | (F2); \
148 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
151 (TARG) = (F1) &~ (F2); \
155 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
157 enum aarch64_operand_class
159 AARCH64_OPND_CLASS_NIL
,
160 AARCH64_OPND_CLASS_INT_REG
,
161 AARCH64_OPND_CLASS_MODIFIED_REG
,
162 AARCH64_OPND_CLASS_FP_REG
,
163 AARCH64_OPND_CLASS_SIMD_REG
,
164 AARCH64_OPND_CLASS_SIMD_ELEMENT
,
165 AARCH64_OPND_CLASS_SISD_REG
,
166 AARCH64_OPND_CLASS_SIMD_REGLIST
,
167 AARCH64_OPND_CLASS_SVE_REG
,
168 AARCH64_OPND_CLASS_PRED_REG
,
169 AARCH64_OPND_CLASS_ADDRESS
,
170 AARCH64_OPND_CLASS_IMMEDIATE
,
171 AARCH64_OPND_CLASS_SYSTEM
,
172 AARCH64_OPND_CLASS_COND
,
175 /* Operand code that helps both parsing and coding.
176 Keep AARCH64_OPERANDS synced. */
180 AARCH64_OPND_NIL
, /* no operand---MUST BE FIRST!*/
182 AARCH64_OPND_Rd
, /* Integer register as destination. */
183 AARCH64_OPND_Rn
, /* Integer register as source. */
184 AARCH64_OPND_Rm
, /* Integer register as source. */
185 AARCH64_OPND_Rt
, /* Integer register used in ld/st instructions. */
186 AARCH64_OPND_Rt2
, /* Integer register used in ld/st pair instructions. */
187 AARCH64_OPND_Rs
, /* Integer register used in ld/st exclusive. */
188 AARCH64_OPND_Ra
, /* Integer register used in ddp_3src instructions. */
189 AARCH64_OPND_Rt_SYS
, /* Integer register used in system instructions. */
191 AARCH64_OPND_Rd_SP
, /* Integer Rd or SP. */
192 AARCH64_OPND_Rn_SP
, /* Integer Rn or SP. */
193 AARCH64_OPND_Rm_SP
, /* Integer Rm or SP. */
194 AARCH64_OPND_PAIRREG
, /* Paired register operand. */
195 AARCH64_OPND_Rm_EXT
, /* Integer Rm extended. */
196 AARCH64_OPND_Rm_SFT
, /* Integer Rm shifted. */
198 AARCH64_OPND_Fd
, /* Floating-point Fd. */
199 AARCH64_OPND_Fn
, /* Floating-point Fn. */
200 AARCH64_OPND_Fm
, /* Floating-point Fm. */
201 AARCH64_OPND_Fa
, /* Floating-point Fa. */
202 AARCH64_OPND_Ft
, /* Floating-point Ft. */
203 AARCH64_OPND_Ft2
, /* Floating-point Ft2. */
205 AARCH64_OPND_Sd
, /* AdvSIMD Scalar Sd. */
206 AARCH64_OPND_Sn
, /* AdvSIMD Scalar Sn. */
207 AARCH64_OPND_Sm
, /* AdvSIMD Scalar Sm. */
209 AARCH64_OPND_Va
, /* AdvSIMD Vector Va. */
210 AARCH64_OPND_Vd
, /* AdvSIMD Vector Vd. */
211 AARCH64_OPND_Vn
, /* AdvSIMD Vector Vn. */
212 AARCH64_OPND_Vm
, /* AdvSIMD Vector Vm. */
213 AARCH64_OPND_VdD1
, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
214 AARCH64_OPND_VnD1
, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
215 AARCH64_OPND_Ed
, /* AdvSIMD Vector Element Vd. */
216 AARCH64_OPND_En
, /* AdvSIMD Vector Element Vn. */
217 AARCH64_OPND_Em
, /* AdvSIMD Vector Element Vm. */
218 AARCH64_OPND_Em16
, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
220 AARCH64_OPND_LVn
, /* AdvSIMD Vector register list used in e.g. TBL. */
221 AARCH64_OPND_LVt
, /* AdvSIMD Vector register list used in ld/st. */
222 AARCH64_OPND_LVt_AL
, /* AdvSIMD Vector register list for loading single
223 structure to all lanes. */
224 AARCH64_OPND_LEt
, /* AdvSIMD Vector Element list. */
226 AARCH64_OPND_CRn
, /* Co-processor register in CRn field. */
227 AARCH64_OPND_CRm
, /* Co-processor register in CRm field. */
229 AARCH64_OPND_IDX
, /* AdvSIMD EXT index operand. */
230 AARCH64_OPND_MASK
, /* AdvSIMD EXT index operand. */
231 AARCH64_OPND_IMM_VLSL
,/* Immediate for shifting vector registers left. */
232 AARCH64_OPND_IMM_VLSR
,/* Immediate for shifting vector registers right. */
233 AARCH64_OPND_SIMD_IMM
,/* AdvSIMD modified immediate without shift. */
234 AARCH64_OPND_SIMD_IMM_SFT
, /* AdvSIMD modified immediate with shift. */
235 AARCH64_OPND_SIMD_FPIMM
,/* AdvSIMD 8-bit fp immediate. */
236 AARCH64_OPND_SHLL_IMM
,/* Immediate shift for AdvSIMD SHLL instruction
238 AARCH64_OPND_IMM0
, /* Immediate for #0. */
239 AARCH64_OPND_FPIMM0
, /* Immediate for #0.0. */
240 AARCH64_OPND_FPIMM
, /* Floating-point Immediate. */
241 AARCH64_OPND_IMMR
, /* Immediate #<immr> in e.g. BFM. */
242 AARCH64_OPND_IMMS
, /* Immediate #<imms> in e.g. BFM. */
243 AARCH64_OPND_WIDTH
, /* Immediate #<width> in e.g. BFI. */
244 AARCH64_OPND_IMM
, /* Immediate. */
245 AARCH64_OPND_IMM_2
, /* Immediate. */
246 AARCH64_OPND_UIMM3_OP1
,/* Unsigned 3-bit immediate in the op1 field. */
247 AARCH64_OPND_UIMM3_OP2
,/* Unsigned 3-bit immediate in the op2 field. */
248 AARCH64_OPND_UIMM4
, /* Unsigned 4-bit immediate in the CRm field. */
249 AARCH64_OPND_UIMM4_ADDG
,/* Unsigned 4-bit immediate in addg/subg. */
250 AARCH64_OPND_UIMM7
, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
251 AARCH64_OPND_UIMM10
, /* Unsigned 10-bit immediate in addg/subg. */
252 AARCH64_OPND_BIT_NUM
, /* Immediate. */
253 AARCH64_OPND_EXCEPTION
,/* imm16 operand in exception instructions. */
254 AARCH64_OPND_CCMP_IMM
,/* Immediate in conditional compare instructions. */
255 AARCH64_OPND_SIMM5
, /* 5-bit signed immediate in the imm5 field. */
256 AARCH64_OPND_NZCV
, /* Flag bit specifier giving an alternative value for
257 each condition flag. */
259 AARCH64_OPND_LIMM
, /* Logical Immediate. */
260 AARCH64_OPND_AIMM
, /* Arithmetic immediate. */
261 AARCH64_OPND_HALF
, /* #<imm16>{, LSL #<shift>} operand in move wide. */
262 AARCH64_OPND_FBITS
, /* FP #<fbits> operand in e.g. SCVTF */
263 AARCH64_OPND_IMM_MOV
, /* Immediate operand for the MOV alias. */
264 AARCH64_OPND_IMM_ROT1
, /* Immediate rotate operand for FCMLA. */
265 AARCH64_OPND_IMM_ROT2
, /* Immediate rotate operand for indexed FCMLA. */
266 AARCH64_OPND_IMM_ROT3
, /* Immediate rotate operand for FCADD. */
268 AARCH64_OPND_COND
, /* Standard condition as the last operand. */
269 AARCH64_OPND_COND1
, /* Same as the above, but excluding AL and NV. */
271 AARCH64_OPND_ADDR_ADRP
, /* Memory address for ADRP */
272 AARCH64_OPND_ADDR_PCREL14
, /* 14-bit PC-relative address for e.g. TBZ. */
273 AARCH64_OPND_ADDR_PCREL19
, /* 19-bit PC-relative address for e.g. LDR. */
274 AARCH64_OPND_ADDR_PCREL21
, /* 21-bit PC-relative address for e.g. ADR. */
275 AARCH64_OPND_ADDR_PCREL26
, /* 26-bit PC-relative address for e.g. BL. */
277 AARCH64_OPND_ADDR_SIMPLE
, /* Address of ld/st exclusive. */
278 AARCH64_OPND_ADDR_REGOFF
, /* Address of register offset. */
279 AARCH64_OPND_ADDR_SIMM7
, /* Address of signed 7-bit immediate. */
280 AARCH64_OPND_ADDR_SIMM9
, /* Address of signed 9-bit immediate. */
281 AARCH64_OPND_ADDR_SIMM9_2
, /* Same as the above, but the immediate is
282 negative or unaligned and there is
283 no writeback allowed. This operand code
284 is only used to support the programmer-
285 friendly feature of using LDR/STR as the
286 the mnemonic name for LDUR/STUR instructions
287 wherever there is no ambiguity. */
288 AARCH64_OPND_ADDR_SIMM10
, /* Address of signed 10-bit immediate. */
289 AARCH64_OPND_ADDR_UIMM12
, /* Address of unsigned 12-bit immediate. */
290 AARCH64_OPND_SIMD_ADDR_SIMPLE
,/* Address of ld/st multiple structures. */
291 AARCH64_OPND_ADDR_OFFSET
, /* Address with an optional 9-bit immediate. */
292 AARCH64_OPND_SIMD_ADDR_POST
, /* Address of ld/st multiple post-indexed. */
294 AARCH64_OPND_SYSREG
, /* System register operand. */
295 AARCH64_OPND_PSTATEFIELD
, /* PSTATE field name operand. */
296 AARCH64_OPND_SYSREG_AT
, /* System register <at_op> operand. */
297 AARCH64_OPND_SYSREG_DC
, /* System register <dc_op> operand. */
298 AARCH64_OPND_SYSREG_IC
, /* System register <ic_op> operand. */
299 AARCH64_OPND_SYSREG_TLBI
, /* System register <tlbi_op> operand. */
300 AARCH64_OPND_SYSREG_SR
, /* System register RCTX operand. */
301 AARCH64_OPND_BARRIER
, /* Barrier operand. */
302 AARCH64_OPND_BARRIER_ISB
, /* Barrier operand for ISB. */
303 AARCH64_OPND_PRFOP
, /* Prefetch operation. */
304 AARCH64_OPND_BARRIER_PSB
, /* Barrier operand for PSB. */
305 AARCH64_OPND_BTI_TARGET
, /* BTI {<target>}. */
307 AARCH64_OPND_SVE_ADDR_RI_S4x16
, /* SVE [<Xn|SP>, #<simm4>*16]. */
308 AARCH64_OPND_SVE_ADDR_RI_S4xVL
, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
309 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
310 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
311 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
312 AARCH64_OPND_SVE_ADDR_RI_S6xVL
, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
313 AARCH64_OPND_SVE_ADDR_RI_S9xVL
, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
314 AARCH64_OPND_SVE_ADDR_RI_U6
, /* SVE [<Xn|SP>, #<uimm6>]. */
315 AARCH64_OPND_SVE_ADDR_RI_U6x2
, /* SVE [<Xn|SP>, #<uimm6>*2]. */
316 AARCH64_OPND_SVE_ADDR_RI_U6x4
, /* SVE [<Xn|SP>, #<uimm6>*4]. */
317 AARCH64_OPND_SVE_ADDR_RI_U6x8
, /* SVE [<Xn|SP>, #<uimm6>*8]. */
318 AARCH64_OPND_SVE_ADDR_R
, /* SVE [<Xn|SP>]. */
319 AARCH64_OPND_SVE_ADDR_RR
, /* SVE [<Xn|SP>, <Xm|XZR>]. */
320 AARCH64_OPND_SVE_ADDR_RR_LSL1
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
321 AARCH64_OPND_SVE_ADDR_RR_LSL2
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
322 AARCH64_OPND_SVE_ADDR_RR_LSL3
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
323 AARCH64_OPND_SVE_ADDR_RX
, /* SVE [<Xn|SP>, <Xm>]. */
324 AARCH64_OPND_SVE_ADDR_RX_LSL1
, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
325 AARCH64_OPND_SVE_ADDR_RX_LSL2
, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
326 AARCH64_OPND_SVE_ADDR_RX_LSL3
, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
327 AARCH64_OPND_SVE_ADDR_RZ
, /* SVE [<Xn|SP>, Zm.D]. */
328 AARCH64_OPND_SVE_ADDR_RZ_LSL1
, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
329 AARCH64_OPND_SVE_ADDR_RZ_LSL2
, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
330 AARCH64_OPND_SVE_ADDR_RZ_LSL3
, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
331 AARCH64_OPND_SVE_ADDR_RZ_XTW_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
332 Bit 14 controls S/U choice. */
333 AARCH64_OPND_SVE_ADDR_RZ_XTW_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
334 Bit 22 controls S/U choice. */
335 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
336 Bit 14 controls S/U choice. */
337 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
338 Bit 22 controls S/U choice. */
339 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
340 Bit 14 controls S/U choice. */
341 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
342 Bit 22 controls S/U choice. */
343 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
344 Bit 14 controls S/U choice. */
345 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
346 Bit 22 controls S/U choice. */
347 AARCH64_OPND_SVE_ADDR_ZI_U5
, /* SVE [Zn.<T>, #<uimm5>]. */
348 AARCH64_OPND_SVE_ADDR_ZI_U5x2
, /* SVE [Zn.<T>, #<uimm5>*2]. */
349 AARCH64_OPND_SVE_ADDR_ZI_U5x4
, /* SVE [Zn.<T>, #<uimm5>*4]. */
350 AARCH64_OPND_SVE_ADDR_ZI_U5x8
, /* SVE [Zn.<T>, #<uimm5>*8]. */
351 AARCH64_OPND_SVE_ADDR_ZZ_LSL
, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
352 AARCH64_OPND_SVE_ADDR_ZZ_SXTW
, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
353 AARCH64_OPND_SVE_ADDR_ZZ_UXTW
, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
354 AARCH64_OPND_SVE_AIMM
, /* SVE unsigned arithmetic immediate. */
355 AARCH64_OPND_SVE_ASIMM
, /* SVE signed arithmetic immediate. */
356 AARCH64_OPND_SVE_FPIMM8
, /* SVE 8-bit floating-point immediate. */
357 AARCH64_OPND_SVE_I1_HALF_ONE
, /* SVE choice between 0.5 and 1.0. */
358 AARCH64_OPND_SVE_I1_HALF_TWO
, /* SVE choice between 0.5 and 2.0. */
359 AARCH64_OPND_SVE_I1_ZERO_ONE
, /* SVE choice between 0.0 and 1.0. */
360 AARCH64_OPND_SVE_IMM_ROT1
, /* SVE 1-bit rotate operand (90 or 270). */
361 AARCH64_OPND_SVE_IMM_ROT2
, /* SVE 2-bit rotate operand (N*90). */
362 AARCH64_OPND_SVE_INV_LIMM
, /* SVE inverted logical immediate. */
363 AARCH64_OPND_SVE_LIMM
, /* SVE logical immediate. */
364 AARCH64_OPND_SVE_LIMM_MOV
, /* SVE logical immediate for MOV. */
365 AARCH64_OPND_SVE_PATTERN
, /* SVE vector pattern enumeration. */
366 AARCH64_OPND_SVE_PATTERN_SCALED
, /* Likewise, with additional MUL factor. */
367 AARCH64_OPND_SVE_PRFOP
, /* SVE prefetch operation. */
368 AARCH64_OPND_SVE_Pd
, /* SVE p0-p15 in Pd. */
369 AARCH64_OPND_SVE_Pg3
, /* SVE p0-p7 in Pg. */
370 AARCH64_OPND_SVE_Pg4_5
, /* SVE p0-p15 in Pg, bits [8,5]. */
371 AARCH64_OPND_SVE_Pg4_10
, /* SVE p0-p15 in Pg, bits [13,10]. */
372 AARCH64_OPND_SVE_Pg4_16
, /* SVE p0-p15 in Pg, bits [19,16]. */
373 AARCH64_OPND_SVE_Pm
, /* SVE p0-p15 in Pm. */
374 AARCH64_OPND_SVE_Pn
, /* SVE p0-p15 in Pn. */
375 AARCH64_OPND_SVE_Pt
, /* SVE p0-p15 in Pt. */
376 AARCH64_OPND_SVE_Rm
, /* Integer Rm or ZR, alt. SVE position. */
377 AARCH64_OPND_SVE_Rn_SP
, /* Integer Rn or SP, alt. SVE position. */
378 AARCH64_OPND_SVE_SHLIMM_PRED
, /* SVE shift left amount (predicated). */
379 AARCH64_OPND_SVE_SHLIMM_UNPRED
, /* SVE shift left amount (unpredicated). */
380 AARCH64_OPND_SVE_SHRIMM_PRED
, /* SVE shift right amount (predicated). */
381 AARCH64_OPND_SVE_SHRIMM_UNPRED
, /* SVE shift right amount (unpredicated). */
382 AARCH64_OPND_SVE_SIMM5
, /* SVE signed 5-bit immediate. */
383 AARCH64_OPND_SVE_SIMM5B
, /* SVE secondary signed 5-bit immediate. */
384 AARCH64_OPND_SVE_SIMM6
, /* SVE signed 6-bit immediate. */
385 AARCH64_OPND_SVE_SIMM8
, /* SVE signed 8-bit immediate. */
386 AARCH64_OPND_SVE_UIMM3
, /* SVE unsigned 3-bit immediate. */
387 AARCH64_OPND_SVE_UIMM7
, /* SVE unsigned 7-bit immediate. */
388 AARCH64_OPND_SVE_UIMM8
, /* SVE unsigned 8-bit immediate. */
389 AARCH64_OPND_SVE_UIMM8_53
, /* SVE split unsigned 8-bit immediate. */
390 AARCH64_OPND_SVE_VZn
, /* Scalar SIMD&FP register in Zn field. */
391 AARCH64_OPND_SVE_Vd
, /* Scalar SIMD&FP register in Vd. */
392 AARCH64_OPND_SVE_Vm
, /* Scalar SIMD&FP register in Vm. */
393 AARCH64_OPND_SVE_Vn
, /* Scalar SIMD&FP register in Vn. */
394 AARCH64_OPND_SVE_Za_5
, /* SVE vector register in Za, bits [9,5]. */
395 AARCH64_OPND_SVE_Za_16
, /* SVE vector register in Za, bits [20,16]. */
396 AARCH64_OPND_SVE_Zd
, /* SVE vector register in Zd. */
397 AARCH64_OPND_SVE_Zm_5
, /* SVE vector register in Zm, bits [9,5]. */
398 AARCH64_OPND_SVE_Zm_16
, /* SVE vector register in Zm, bits [20,16]. */
399 AARCH64_OPND_SVE_Zm3_INDEX
, /* z0-z7[0-3] in Zm, bits [20,16]. */
400 AARCH64_OPND_SVE_Zm3_22_INDEX
, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
401 AARCH64_OPND_SVE_Zm4_INDEX
, /* z0-z15[0-1] in Zm, bits [20,16]. */
402 AARCH64_OPND_SVE_Zn
, /* SVE vector register in Zn. */
403 AARCH64_OPND_SVE_Zn_INDEX
, /* Indexed SVE vector register, for DUP. */
404 AARCH64_OPND_SVE_ZnxN
, /* SVE vector register list in Zn. */
405 AARCH64_OPND_SVE_Zt
, /* SVE vector register in Zt. */
406 AARCH64_OPND_SVE_ZtxN
, /* SVE vector register list in Zt. */
407 AARCH64_OPND_SM3_IMM2
, /* SM3 encodes lane in bits [13, 14]. */
410 /* Qualifier constrains an operand. It either specifies a variant of an
411 operand type or limits values available to an operand type.
413 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
415 enum aarch64_opnd_qualifier
417 /* Indicating no further qualification on an operand. */
418 AARCH64_OPND_QLF_NIL
,
420 /* Qualifying an operand which is a general purpose (integer) register;
421 indicating the operand data size or a specific register. */
422 AARCH64_OPND_QLF_W
, /* Wn, WZR or WSP. */
423 AARCH64_OPND_QLF_X
, /* Xn, XZR or XSP. */
424 AARCH64_OPND_QLF_WSP
, /* WSP. */
425 AARCH64_OPND_QLF_SP
, /* SP. */
427 /* Qualifying an operand which is a floating-point register, a SIMD
428 vector element or a SIMD vector element list; indicating operand data
429 size or the size of each SIMD vector element in the case of a SIMD
431 These qualifiers are also used to qualify an address operand to
432 indicate the size of data element a load/store instruction is
434 They are also used for the immediate shift operand in e.g. SSHR. Such
435 a use is only for the ease of operand encoding/decoding and qualifier
436 sequence matching; such a use should not be applied widely; use the value
437 constraint qualifiers for immediate operands wherever possible. */
438 AARCH64_OPND_QLF_S_B
,
439 AARCH64_OPND_QLF_S_H
,
440 AARCH64_OPND_QLF_S_S
,
441 AARCH64_OPND_QLF_S_D
,
442 AARCH64_OPND_QLF_S_Q
,
443 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
444 are selected by the instruction. Other than that it has no difference
445 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
446 reasons and is an exception from normal AArch64 disassembly scheme. */
447 AARCH64_OPND_QLF_S_4B
,
449 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
450 register list; indicating register shape.
451 They are also used for the immediate shift operand in e.g. SSHR. Such
452 a use is only for the ease of operand encoding/decoding and qualifier
453 sequence matching; such a use should not be applied widely; use the value
454 constraint qualifiers for immediate operands wherever possible. */
455 AARCH64_OPND_QLF_V_4B
,
456 AARCH64_OPND_QLF_V_8B
,
457 AARCH64_OPND_QLF_V_16B
,
458 AARCH64_OPND_QLF_V_2H
,
459 AARCH64_OPND_QLF_V_4H
,
460 AARCH64_OPND_QLF_V_8H
,
461 AARCH64_OPND_QLF_V_2S
,
462 AARCH64_OPND_QLF_V_4S
,
463 AARCH64_OPND_QLF_V_1D
,
464 AARCH64_OPND_QLF_V_2D
,
465 AARCH64_OPND_QLF_V_1Q
,
467 AARCH64_OPND_QLF_P_Z
,
468 AARCH64_OPND_QLF_P_M
,
470 /* Constraint on value. */
471 AARCH64_OPND_QLF_CR
, /* CRn, CRm. */
472 AARCH64_OPND_QLF_imm_0_7
,
473 AARCH64_OPND_QLF_imm_0_15
,
474 AARCH64_OPND_QLF_imm_0_31
,
475 AARCH64_OPND_QLF_imm_0_63
,
476 AARCH64_OPND_QLF_imm_1_32
,
477 AARCH64_OPND_QLF_imm_1_64
,
479 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
481 AARCH64_OPND_QLF_LSL
,
482 AARCH64_OPND_QLF_MSL
,
484 /* Special qualifier helping retrieve qualifier information during the
485 decoding time (currently not in use). */
486 AARCH64_OPND_QLF_RETRIEVE
,
489 /* Instruction class. */
491 enum aarch64_insn_class
546 ldst_imm9
, /* immpost or immpre */
547 ldst_imm10
, /* LDRAA/LDRAB */
581 /* Opcode enumerators. */
625 OP_MOV_IMM_LOG
, /* MOV alias for moving bitmask immediate. */
626 OP_MOV_IMM_WIDE
, /* MOV alias for moving wide immediate. */
627 OP_MOV_IMM_WIDEN
, /* MOV alias for moving wide immediate (negated). */
629 OP_MOV_V
, /* MOV alias for moving vector register. */
642 OP_BFC
, /* ARMv8.2. */
659 OP_FCVTXN_S
, /* Scalar version. */
680 OP_FCMLA_ELEM
, /* ARMv8.3, indexed element version. */
682 OP_TOTAL_NUM
, /* Pseudo. */
696 /* Maximum number of operands an instruction can have. */
697 #define AARCH64_MAX_OPND_NUM 6
698 /* Maximum number of qualifier sequences an instruction can have. */
699 #define AARCH64_MAX_QLF_SEQ_NUM 10
700 /* Operand qualifier typedef; optimized for the size. */
701 typedef unsigned char aarch64_opnd_qualifier_t
;
702 /* Operand qualifier sequence typedef. */
703 typedef aarch64_opnd_qualifier_t \
704 aarch64_opnd_qualifier_seq_t
[AARCH64_MAX_OPND_NUM
];
706 /* FIXME: improve the efficiency. */
707 static inline bfd_boolean
708 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t
*qualifiers
)
711 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
712 if (qualifiers
[i
] != AARCH64_OPND_QLF_NIL
)
717 /* Forward declare error reporting type. */
718 typedef struct aarch64_operand_error aarch64_operand_error
;
719 /* Forward declare instruction sequence type. */
720 typedef struct aarch64_instr_sequence aarch64_instr_sequence
;
721 /* Forward declare instruction definition. */
722 typedef struct aarch64_inst aarch64_inst
;
724 /* This structure holds information for a particular opcode. */
726 struct aarch64_opcode
728 /* The name of the mnemonic. */
731 /* The opcode itself. Those bits which will be filled in with
732 operands are zeroes. */
735 /* The opcode mask. This is used by the disassembler. This is a
736 mask containing ones indicating those bits which must match the
737 opcode field, and zeroes indicating those bits which need not
738 match (and are presumably filled in by operands). */
741 /* Instruction class. */
742 enum aarch64_insn_class iclass
;
744 /* Enumerator identifier. */
747 /* Which architecture variant provides this instruction. */
748 const aarch64_feature_set
*avariant
;
750 /* An array of operand codes. Each code is an index into the
751 operand table. They appear in the order which the operands must
752 appear in assembly code, and are terminated by a zero. */
753 enum aarch64_opnd operands
[AARCH64_MAX_OPND_NUM
];
755 /* A list of operand qualifier code sequence. Each operand qualifier
756 code qualifies the corresponding operand code. Each operand
757 qualifier sequence specifies a valid opcode variant and related
758 constraint on operands. */
759 aarch64_opnd_qualifier_seq_t qualifiers_list
[AARCH64_MAX_QLF_SEQ_NUM
];
761 /* Flags providing information about this instruction */
764 /* Extra constraints on the instruction that the verifier checks. */
765 uint32_t constraints
;
767 /* If nonzero, this operand and operand 0 are both registers and
768 are required to have the same register number. */
769 unsigned char tied_operand
;
771 /* If non-NULL, a function to verify that a given instruction is valid. */
772 enum err_type (* verifier
) (const struct aarch64_inst
*, const aarch64_insn
,
773 bfd_vma
, bfd_boolean
, aarch64_operand_error
*,
774 struct aarch64_instr_sequence
*);
777 typedef struct aarch64_opcode aarch64_opcode
;
779 /* Table describing all the AArch64 opcodes. */
780 extern aarch64_opcode aarch64_opcode_table
[];
783 #define F_ALIAS (1 << 0)
784 #define F_HAS_ALIAS (1 << 1)
785 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
786 is specified, it is the priority 0 by default, i.e. the lowest priority. */
787 #define F_P1 (1 << 2)
788 #define F_P2 (2 << 2)
789 #define F_P3 (3 << 2)
790 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
791 #define F_COND (1 << 4)
792 /* Instruction has the field of 'sf'. */
793 #define F_SF (1 << 5)
794 /* Instruction has the field of 'size:Q'. */
795 #define F_SIZEQ (1 << 6)
796 /* Floating-point instruction has the field of 'type'. */
797 #define F_FPTYPE (1 << 7)
798 /* AdvSIMD scalar instruction has the field of 'size'. */
799 #define F_SSIZE (1 << 8)
800 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
802 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
803 #define F_GPRSIZE_IN_Q (1 << 10)
804 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
805 #define F_LDS_SIZE (1 << 11)
806 /* Optional operand; assume maximum of 1 operand can be optional. */
807 #define F_OPD0_OPT (1 << 12)
808 #define F_OPD1_OPT (2 << 12)
809 #define F_OPD2_OPT (3 << 12)
810 #define F_OPD3_OPT (4 << 12)
811 #define F_OPD4_OPT (5 << 12)
812 /* Default value for the optional operand when omitted from the assembly. */
813 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
814 /* Instruction that is an alias of another instruction needs to be
815 encoded/decoded by converting it to/from the real form, followed by
816 the encoding/decoding according to the rules of the real opcode.
817 This compares to the direct coding using the alias's information.
818 N.B. this flag requires F_ALIAS to be used together. */
819 #define F_CONV (1 << 20)
820 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
821 friendly pseudo instruction available only in the assembly code (thus will
822 not show up in the disassembly). */
823 #define F_PSEUDO (1 << 21)
824 /* Instruction has miscellaneous encoding/decoding rules. */
825 #define F_MISC (1 << 22)
826 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
827 #define F_N (1 << 23)
828 /* Opcode dependent field. */
829 #define F_OD(X) (((X) & 0x7) << 24)
830 /* Instruction has the field of 'sz'. */
831 #define F_LSE_SZ (1 << 27)
832 /* Require an exact qualifier match, even for NIL qualifiers. */
833 #define F_STRICT (1ULL << 28)
834 /* This system instruction is used to read system registers. */
835 #define F_SYS_READ (1ULL << 29)
836 /* This system instruction is used to write system registers. */
837 #define F_SYS_WRITE (1ULL << 30)
838 /* This instruction has an extra constraint on it that imposes a requirement on
839 subsequent instructions. */
840 #define F_SCAN (1ULL << 31)
841 /* Next bit is 32. */
843 /* Instruction constraints. */
844 /* This instruction has a predication constraint on the instruction at PC+4. */
845 #define C_SCAN_MOVPRFX (1U << 0)
846 /* This instruction's operation width is determined by the operand with the
847 largest element size. */
848 #define C_MAX_ELEM (1U << 1)
851 static inline bfd_boolean
852 alias_opcode_p (const aarch64_opcode
*opcode
)
854 return (opcode
->flags
& F_ALIAS
) ? TRUE
: FALSE
;
857 static inline bfd_boolean
858 opcode_has_alias (const aarch64_opcode
*opcode
)
860 return (opcode
->flags
& F_HAS_ALIAS
) ? TRUE
: FALSE
;
863 /* Priority for disassembling preference. */
865 opcode_priority (const aarch64_opcode
*opcode
)
867 return (opcode
->flags
>> 2) & 0x3;
870 static inline bfd_boolean
871 pseudo_opcode_p (const aarch64_opcode
*opcode
)
873 return (opcode
->flags
& F_PSEUDO
) != 0lu ? TRUE
: FALSE
;
876 static inline bfd_boolean
877 optional_operand_p (const aarch64_opcode
*opcode
, unsigned int idx
)
879 return (((opcode
->flags
>> 12) & 0x7) == idx
+ 1)
883 static inline aarch64_insn
884 get_optional_operand_default_value (const aarch64_opcode
*opcode
)
886 return (opcode
->flags
>> 15) & 0x1f;
889 static inline unsigned int
890 get_opcode_dependent_value (const aarch64_opcode
*opcode
)
892 return (opcode
->flags
>> 24) & 0x7;
895 static inline bfd_boolean
896 opcode_has_special_coder (const aarch64_opcode
*opcode
)
898 return (opcode
->flags
& (F_SF
| F_LSE_SZ
| F_SIZEQ
| F_FPTYPE
| F_SSIZE
| F_T
899 | F_GPRSIZE_IN_Q
| F_LDS_SIZE
| F_MISC
| F_N
| F_COND
)) ? TRUE
903 struct aarch64_name_value_pair
909 extern const struct aarch64_name_value_pair aarch64_operand_modifiers
[];
910 extern const struct aarch64_name_value_pair aarch64_barrier_options
[16];
911 extern const struct aarch64_name_value_pair aarch64_prfops
[32];
912 extern const struct aarch64_name_value_pair aarch64_hint_options
[];
921 extern const aarch64_sys_reg aarch64_sys_regs
[];
922 extern const aarch64_sys_reg aarch64_pstatefields
[];
923 extern bfd_boolean
aarch64_sys_reg_deprecated_p (const aarch64_sys_reg
*);
924 extern bfd_boolean
aarch64_sys_reg_supported_p (const aarch64_feature_set
,
925 const aarch64_sys_reg
*);
926 extern bfd_boolean
aarch64_pstatefield_supported_p (const aarch64_feature_set
,
927 const aarch64_sys_reg
*);
934 } aarch64_sys_ins_reg
;
936 extern bfd_boolean
aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg
*);
938 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set
,
939 const aarch64_sys_ins_reg
*);
941 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic
[];
942 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc
[];
943 extern const aarch64_sys_ins_reg aarch64_sys_regs_at
[];
944 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi
[];
945 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr
[];
947 /* Shift/extending operator kinds.
948 N.B. order is important; keep aarch64_operand_modifiers synced. */
949 enum aarch64_modifier_kind
970 aarch64_extend_operator_p (enum aarch64_modifier_kind
);
972 enum aarch64_modifier_kind
973 aarch64_get_operand_modifier (const struct aarch64_name_value_pair
*);
978 /* A list of names with the first one as the disassembly preference;
979 terminated by NULL if fewer than 3. */
980 const char *names
[4];
984 extern const aarch64_cond aarch64_conds
[16];
986 const aarch64_cond
* get_cond_from_value (aarch64_insn value
);
987 const aarch64_cond
* get_inverted_cond (const aarch64_cond
*cond
);
989 /* Structure representing an operand. */
991 struct aarch64_opnd_info
993 enum aarch64_opnd type
;
994 aarch64_opnd_qualifier_t qualifier
;
1011 unsigned first_regno
: 5;
1012 unsigned num_regs
: 3;
1013 /* 1 if it is a list of reg element. */
1014 unsigned has_index
: 1;
1015 /* Lane index; valid only when has_index is 1. */
1018 /* e.g. immediate or pc relative address offset. */
1024 /* e.g. address in STR (register offset). */
1027 unsigned base_regno
;
1037 unsigned pcrel
: 1; /* PC-relative. */
1038 unsigned writeback
: 1;
1039 unsigned preind
: 1; /* Pre-indexed. */
1040 unsigned postind
: 1; /* Post-indexed. */
1045 /* The encoding of the system register. */
1048 /* The system register flags. */
1052 const aarch64_cond
*cond
;
1053 /* The encoding of the PSTATE field. */
1054 aarch64_insn pstatefield
;
1055 const aarch64_sys_ins_reg
*sysins_op
;
1056 const struct aarch64_name_value_pair
*barrier
;
1057 const struct aarch64_name_value_pair
*hint_option
;
1058 const struct aarch64_name_value_pair
*prfop
;
1061 /* Operand shifter; in use when the operand is a register offset address,
1062 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1065 enum aarch64_modifier_kind kind
;
1066 unsigned operator_present
: 1; /* Only valid during encoding. */
1067 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1068 unsigned amount_present
: 1;
1072 unsigned skip
:1; /* Operand is not completed if there is a fixup needed
1073 to be done on it. In some (but not all) of these
1074 cases, we need to tell libopcodes to skip the
1075 constraint checking and the encoding for this
1076 operand, so that the libopcodes can pick up the
1077 right opcode before the operand is fixed-up. This
1078 flag should only be used during the
1079 assembling/encoding. */
1080 unsigned present
:1; /* Whether this operand is present in the assembly
1081 line; not used during the disassembly. */
1084 typedef struct aarch64_opnd_info aarch64_opnd_info
;
1086 /* Structure representing an instruction.
1088 It is used during both the assembling and disassembling. The assembler
1089 fills an aarch64_inst after a successful parsing and then passes it to the
1090 encoding routine to do the encoding. During the disassembling, the
1091 disassembler calls the decoding routine to decode a binary instruction; on a
1092 successful return, such a structure will be filled with information of the
1093 instruction; then the disassembler uses the information to print out the
1098 /* The value of the binary instruction. */
1101 /* Corresponding opcode entry. */
1102 const aarch64_opcode
*opcode
;
1104 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1105 const aarch64_cond
*cond
;
1107 /* Operands information. */
1108 aarch64_opnd_info operands
[AARCH64_MAX_OPND_NUM
];
1111 /* Defining the HINT #imm values for the aarch64_hint_options. */
1112 #define HINT_OPD_CSYNC 0x11
1113 #define HINT_OPD_C 0x22
1114 #define HINT_OPD_J 0x24
1115 #define HINT_OPD_JC 0x26
1116 #define HINT_OPD_NULL 0x00
1119 /* Diagnosis related declaration and interface. */
1121 /* Operand error kind enumerators.
1123 AARCH64_OPDE_RECOVERABLE
1124 Less severe error found during the parsing, very possibly because that
1125 GAS has picked up a wrong instruction template for the parsing.
1127 AARCH64_OPDE_SYNTAX_ERROR
1128 General syntax error; it can be either a user error, or simply because
1129 that GAS is trying a wrong instruction template.
1131 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1132 Definitely a user syntax error.
1134 AARCH64_OPDE_INVALID_VARIANT
1135 No syntax error, but the operands are not a valid combination, e.g.
1138 AARCH64_OPDE_UNTIED_OPERAND
1139 The asm failed to use the same register for a destination operand
1140 and a tied source operand.
1142 AARCH64_OPDE_OUT_OF_RANGE
1143 Error about some immediate value out of a valid range.
1145 AARCH64_OPDE_UNALIGNED
1146 Error about some immediate value not properly aligned (i.e. not being a
1147 multiple times of a certain value).
1149 AARCH64_OPDE_REG_LIST
1150 Error about the register list operand having unexpected number of
1153 AARCH64_OPDE_OTHER_ERROR
1154 Error of the highest severity and used for any severe issue that does not
1155 fall into any of the above categories.
1157 The enumerators are only interesting to GAS. They are declared here (in
1158 libopcodes) because that some errors are detected (and then notified to GAS)
1159 by libopcodes (rather than by GAS solely).
1161 The first three errors are only deteced by GAS while the
1162 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1163 only libopcodes has the information about the valid variants of each
1166 The enumerators have an increasing severity. This is helpful when there are
1167 multiple instruction templates available for a given mnemonic name (e.g.
1168 FMOV); this mechanism will help choose the most suitable template from which
1169 the generated diagnostics can most closely describe the issues, if any. */
1171 enum aarch64_operand_error_kind
1174 AARCH64_OPDE_RECOVERABLE
,
1175 AARCH64_OPDE_SYNTAX_ERROR
,
1176 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
1177 AARCH64_OPDE_INVALID_VARIANT
,
1178 AARCH64_OPDE_UNTIED_OPERAND
,
1179 AARCH64_OPDE_OUT_OF_RANGE
,
1180 AARCH64_OPDE_UNALIGNED
,
1181 AARCH64_OPDE_REG_LIST
,
1182 AARCH64_OPDE_OTHER_ERROR
1185 /* N.B. GAS assumes that this structure work well with shallow copy. */
1186 struct aarch64_operand_error
1188 enum aarch64_operand_error_kind kind
;
1191 int data
[3]; /* Some data for extra information. */
1192 bfd_boolean non_fatal
;
1195 /* AArch64 sequence structure used to track instructions with F_SCAN
1196 dependencies for both assembler and disassembler. */
1197 struct aarch64_instr_sequence
1199 /* The instruction that caused this sequence to be opened. */
1200 aarch64_inst
*instr
;
1201 /* The number of instructions the above instruction allows to be kept in the
1202 sequence before an automatic close is done. */
1204 /* The instructions currently added to the sequence. */
1205 aarch64_inst
**current_insns
;
1206 /* The number of instructions already in the sequence. */
1210 /* Encoding entrypoint. */
1213 aarch64_opcode_encode (const aarch64_opcode
*, const aarch64_inst
*,
1214 aarch64_insn
*, aarch64_opnd_qualifier_t
*,
1215 aarch64_operand_error
*, aarch64_instr_sequence
*);
1217 extern const aarch64_opcode
*
1218 aarch64_replace_opcode (struct aarch64_inst
*,
1219 const aarch64_opcode
*);
1221 /* Given the opcode enumerator OP, return the pointer to the corresponding
1224 extern const aarch64_opcode
*
1225 aarch64_get_opcode (enum aarch64_op
);
1227 /* Generate the string representation of an operand. */
1229 aarch64_print_operand (char *, size_t, bfd_vma
, const aarch64_opcode
*,
1230 const aarch64_opnd_info
*, int, int *, bfd_vma
*,
1233 /* Miscellaneous interface. */
1236 aarch64_operand_index (const enum aarch64_opnd
*, enum aarch64_opnd
);
1238 extern aarch64_opnd_qualifier_t
1239 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t
*, int,
1240 const aarch64_opnd_qualifier_t
, int);
1243 aarch64_is_destructive_by_operands (const aarch64_opcode
*);
1246 aarch64_num_of_operands (const aarch64_opcode
*);
1249 aarch64_stack_pointer_p (const aarch64_opnd_info
*);
1252 aarch64_zero_register_p (const aarch64_opnd_info
*);
1254 extern enum err_type
1255 aarch64_decode_insn (aarch64_insn
, aarch64_inst
*, bfd_boolean
,
1256 aarch64_operand_error
*);
1259 init_insn_sequence (const struct aarch64_inst
*, aarch64_instr_sequence
*);
1261 /* Given an operand qualifier, return the expected data element size
1262 of a qualified operand. */
1263 extern unsigned char
1264 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t
);
1266 extern enum aarch64_operand_class
1267 aarch64_get_operand_class (enum aarch64_opnd
);
1270 aarch64_get_operand_name (enum aarch64_opnd
);
1273 aarch64_get_operand_desc (enum aarch64_opnd
);
1276 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1278 #ifdef DEBUG_AARCH64
1279 extern int debug_dump
;
1282 aarch64_verbose (const char *, ...) __attribute__ ((format (printf
, 1, 2)));
1284 #define DEBUG_TRACE(M, ...) \
1287 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1290 #define DEBUG_TRACE_IF(C, M, ...) \
1292 if (debug_dump && (C)) \
1293 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1295 #else /* !DEBUG_AARCH64 */
1296 #define DEBUG_TRACE(M, ...) ;
1297 #define DEBUG_TRACE_IF(C, M, ...) ;
1298 #endif /* DEBUG_AARCH64 */
1300 extern const char *const aarch64_sve_pattern_array
[32];
1301 extern const char *const aarch64_sve_prfop_array
[16];
1307 #endif /* OPCODE_AARCH64_H */