include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  54
  55 /* Architectures are the sum of the base and extensions.  */
  56 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  57                                                  AARCH64_FEATURE_FP  \
  58                                                  | AARCH64_FEATURE_SIMD)
  59 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  60                                                  AARCH64_FEATURE_FP  \
  61                                                  | AARCH64_FEATURE_SIMD \
  62                                                  | AARCH64_FEATURE_CRC  \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS  \
  72                                                  | AARCH64_FEATURE_FP   \
  73                                                  | AARCH64_FEATURE_SIMD \
  74                                                  | AARCH64_FEATURE_CRC  \
  75                                                  | AARCH64_FEATURE_V8_1 \
  76                                                  | AARCH64_FEATURE_LSE  \
  77                                                  | AARCH64_FEATURE_PAN  \
  78                                                  | AARCH64_FEATURE_LOR  \
  79                                                  | AARCH64_FEATURE_RDMA)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  88   ((~(CPU) & (FEAT)) == 0)
  89
  90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  91   (((CPU) & (FEAT)) != 0)
  92
  93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  94   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  95
  96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) | (F2);                     \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 104   do                                            \
 105     {                                           \
 106       (TARG) = (F1) &~ (F2);                    \
 107     }                                           \
 108   while (0)
 109
 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 111
 112 enum aarch64_operand_class
 113 {
 114   AARCH64_OPND_CLASS_NIL,
 115   AARCH64_OPND_CLASS_INT_REG,
 116   AARCH64_OPND_CLASS_MODIFIED_REG,
 117   AARCH64_OPND_CLASS_FP_REG,
 118   AARCH64_OPND_CLASS_SIMD_REG,
 119   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 120   AARCH64_OPND_CLASS_SISD_REG,
 121   AARCH64_OPND_CLASS_SIMD_REGLIST,
 122   AARCH64_OPND_CLASS_CP_REG,
 123   AARCH64_OPND_CLASS_SVE_REG,
 124   AARCH64_OPND_CLASS_PRED_REG,
 125   AARCH64_OPND_CLASS_ADDRESS,
 126   AARCH64_OPND_CLASS_IMMEDIATE,
 127   AARCH64_OPND_CLASS_SYSTEM,
 128   AARCH64_OPND_CLASS_COND,
 129 };
 130
 131 /* Operand code that helps both parsing and coding.
 132    Keep AARCH64_OPERANDS synced.  */
 133
 134 enum aarch64_opnd
 135 {
 136   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 137
 138   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 139   AARCH64_OPND_Rn,      /* Integer register as source.  */
 140   AARCH64_OPND_Rm,      /* Integer register as source.  */
 141   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 142   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 143   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 144   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 145   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 146
 147   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 148   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 149   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 150   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 151   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 152
 153   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 154   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 155   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 156   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 157   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 158   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 159
 160   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 161   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 162   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 163
 164   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 165   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 166   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 167   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 169   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 170   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 171   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 172   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 173   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 174   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 175                            structure to all lanes.  */
 176   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 177
 178   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 179   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 180
 181   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 182   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 183   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 184   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 185   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 186   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 187   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 188                            (no encoding).  */
 189   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 190   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 191   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 192   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 193   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 194   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 195   AARCH64_OPND_IMM,     /* Immediate.  */
 196   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 197   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 198   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 199   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 200   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 201   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 202   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 203   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 204                            each condition flag.  */
 205
 206   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 207   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 208   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 209   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 210   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 211
 212   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 213   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 214
 215   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 216   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 217   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 218   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 219   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 220
 221   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 222   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 223   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 224   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 225   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 226                                    negative or unaligned and there is
 227                                    no writeback allowed.  This operand code
 228                                    is only used to support the programmer-
 229                                    friendly feature of using LDR/STR as the
 230                                    the mnemonic name for LDUR/STUR instructions
 231                                    wherever there is no ambiguity.  */
 232   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 233   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 234   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 235
 236   AARCH64_OPND_SYSREG,          /* System register operand.  */
 237   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 238   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 239   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 240   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 241   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 242   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 243   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 244   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 245   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 246
 247   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 248   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 249   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 250   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 251   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 252   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 253   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 254   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 255   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 256   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 257   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 258   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 259   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 260   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 261   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 262   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 263   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 264   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 265   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 266   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 267 };
 268
 269 /* Qualifier constrains an operand.  It either specifies a variant of an
 270    operand type or limits values available to an operand type.
 271
 272    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 273
 274 enum aarch64_opnd_qualifier
 275 {
 276   /* Indicating no further qualification on an operand.  */
 277   AARCH64_OPND_QLF_NIL,
 278
 279   /* Qualifying an operand which is a general purpose (integer) register;
 280      indicating the operand data size or a specific register.  */
 281   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 282   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 283   AARCH64_OPND_QLF_WSP, /* WSP.  */
 284   AARCH64_OPND_QLF_SP,  /* SP.  */
 285
 286   /* Qualifying an operand which is a floating-point register, a SIMD
 287      vector element or a SIMD vector element list; indicating operand data
 288      size or the size of each SIMD vector element in the case of a SIMD
 289      vector element list.
 290      These qualifiers are also used to qualify an address operand to
 291      indicate the size of data element a load/store instruction is
 292      accessing.
 293      They are also used for the immediate shift operand in e.g. SSHR.  Such
 294      a use is only for the ease of operand encoding/decoding and qualifier
 295      sequence matching; such a use should not be applied widely; use the value
 296      constraint qualifiers for immediate operands wherever possible.  */
 297   AARCH64_OPND_QLF_S_B,
 298   AARCH64_OPND_QLF_S_H,
 299   AARCH64_OPND_QLF_S_S,
 300   AARCH64_OPND_QLF_S_D,
 301   AARCH64_OPND_QLF_S_Q,
 302
 303   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 304      register list; indicating register shape.
 305      They are also used for the immediate shift operand in e.g. SSHR.  Such
 306      a use is only for the ease of operand encoding/decoding and qualifier
 307      sequence matching; such a use should not be applied widely; use the value
 308      constraint qualifiers for immediate operands wherever possible.  */
 309   AARCH64_OPND_QLF_V_8B,
 310   AARCH64_OPND_QLF_V_16B,
 311   AARCH64_OPND_QLF_V_2H,
 312   AARCH64_OPND_QLF_V_4H,
 313   AARCH64_OPND_QLF_V_8H,
 314   AARCH64_OPND_QLF_V_2S,
 315   AARCH64_OPND_QLF_V_4S,
 316   AARCH64_OPND_QLF_V_1D,
 317   AARCH64_OPND_QLF_V_2D,
 318   AARCH64_OPND_QLF_V_1Q,
 319
 320   AARCH64_OPND_QLF_P_Z,
 321   AARCH64_OPND_QLF_P_M,
 322
 323   /* Constraint on value.  */
 324   AARCH64_OPND_QLF_imm_0_7,
 325   AARCH64_OPND_QLF_imm_0_15,
 326   AARCH64_OPND_QLF_imm_0_31,
 327   AARCH64_OPND_QLF_imm_0_63,
 328   AARCH64_OPND_QLF_imm_1_32,
 329   AARCH64_OPND_QLF_imm_1_64,
 330
 331   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 332      or shift-ones.  */
 333   AARCH64_OPND_QLF_LSL,
 334   AARCH64_OPND_QLF_MSL,
 335
 336   /* Special qualifier helping retrieve qualifier information during the
 337      decoding time (currently not in use).  */
 338   AARCH64_OPND_QLF_RETRIEVE,
 339 };
 340 \f
 341 /* Instruction class.  */
 342
 343 enum aarch64_insn_class
 344 {
 345   addsub_carry,
 346   addsub_ext,
 347   addsub_imm,
 348   addsub_shift,
 349   asimdall,
 350   asimddiff,
 351   asimdelem,
 352   asimdext,
 353   asimdimm,
 354   asimdins,
 355   asimdmisc,
 356   asimdperm,
 357   asimdsame,
 358   asimdshf,
 359   asimdtbl,
 360   asisddiff,
 361   asisdelem,
 362   asisdlse,
 363   asisdlsep,
 364   asisdlso,
 365   asisdlsop,
 366   asisdmisc,
 367   asisdone,
 368   asisdpair,
 369   asisdsame,
 370   asisdshf,
 371   bitfield,
 372   branch_imm,
 373   branch_reg,
 374   compbranch,
 375   condbranch,
 376   condcmp_imm,
 377   condcmp_reg,
 378   condsel,
 379   cryptoaes,
 380   cryptosha2,
 381   cryptosha3,
 382   dp_1src,
 383   dp_2src,
 384   dp_3src,
 385   exception,
 386   extract,
 387   float2fix,
 388   float2int,
 389   floatccmp,
 390   floatcmp,
 391   floatdp1,
 392   floatdp2,
 393   floatdp3,
 394   floatimm,
 395   floatsel,
 396   ldst_immpost,
 397   ldst_immpre,
 398   ldst_imm9,    /* immpost or immpre */
 399   ldst_pos,
 400   ldst_regoff,
 401   ldst_unpriv,
 402   ldst_unscaled,
 403   ldstexcl,
 404   ldstnapair_offs,
 405   ldstpair_off,
 406   ldstpair_indexed,
 407   loadlit,
 408   log_imm,
 409   log_shift,
 410   lse_atomic,
 411   movewide,
 412   pcreladdr,
 413   ic_system,
 414   testbranch,
 415 };
 416
 417 /* Opcode enumerators.  */
 418
 419 enum aarch64_op
 420 {
 421   OP_NIL,
 422   OP_STRB_POS,
 423   OP_LDRB_POS,
 424   OP_LDRSB_POS,
 425   OP_STRH_POS,
 426   OP_LDRH_POS,
 427   OP_LDRSH_POS,
 428   OP_STR_POS,
 429   OP_LDR_POS,
 430   OP_STRF_POS,
 431   OP_LDRF_POS,
 432   OP_LDRSW_POS,
 433   OP_PRFM_POS,
 434
 435   OP_STURB,
 436   OP_LDURB,
 437   OP_LDURSB,
 438   OP_STURH,
 439   OP_LDURH,
 440   OP_LDURSH,
 441   OP_STUR,
 442   OP_LDUR,
 443   OP_STURV,
 444   OP_LDURV,
 445   OP_LDURSW,
 446   OP_PRFUM,
 447
 448   OP_LDR_LIT,
 449   OP_LDRV_LIT,
 450   OP_LDRSW_LIT,
 451   OP_PRFM_LIT,
 452
 453   OP_ADD,
 454   OP_B,
 455   OP_BL,
 456
 457   OP_MOVN,
 458   OP_MOVZ,
 459   OP_MOVK,
 460
 461   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 462   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 463   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 464
 465   OP_MOV_V,             /* MOV alias for moving vector register.  */
 466
 467   OP_ASR_IMM,
 468   OP_LSR_IMM,
 469   OP_LSL_IMM,
 470
 471   OP_BIC,
 472
 473   OP_UBFX,
 474   OP_BFXIL,
 475   OP_SBFX,
 476   OP_SBFIZ,
 477   OP_BFI,
 478   OP_BFC,               /* ARMv8.2.  */
 479   OP_UBFIZ,
 480   OP_UXTB,
 481   OP_UXTH,
 482   OP_UXTW,
 483
 484   OP_CINC,
 485   OP_CINV,
 486   OP_CNEG,
 487   OP_CSET,
 488   OP_CSETM,
 489
 490   OP_FCVT,
 491   OP_FCVTN,
 492   OP_FCVTN2,
 493   OP_FCVTL,
 494   OP_FCVTL2,
 495   OP_FCVTXN_S,          /* Scalar version.  */
 496
 497   OP_ROR_IMM,
 498
 499   OP_SXTL,
 500   OP_SXTL2,
 501   OP_UXTL,
 502   OP_UXTL2,
 503
 504   OP_TOTAL_NUM,         /* Pseudo.  */
 505 };
 506
 507 /* Maximum number of operands an instruction can have.  */
 508 #define AARCH64_MAX_OPND_NUM 6
 509 /* Maximum number of qualifier sequences an instruction can have.  */
 510 #define AARCH64_MAX_QLF_SEQ_NUM 10
 511 /* Operand qualifier typedef; optimized for the size.  */
 512 typedef unsigned char aarch64_opnd_qualifier_t;
 513 /* Operand qualifier sequence typedef.  */
 514 typedef aarch64_opnd_qualifier_t        \
 515           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 516
 517 /* FIXME: improve the efficiency.  */
 518 static inline bfd_boolean
 519 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 520 {
 521   int i;
 522   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 523     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 524       return FALSE;
 525   return TRUE;
 526 }
 527
 528 /* This structure holds information for a particular opcode.  */
 529
 530 struct aarch64_opcode
 531 {
 532   /* The name of the mnemonic.  */
 533   const char *name;
 534
 535   /* The opcode itself.  Those bits which will be filled in with
 536      operands are zeroes.  */
 537   aarch64_insn opcode;
 538
 539   /* The opcode mask.  This is used by the disassembler.  This is a
 540      mask containing ones indicating those bits which must match the
 541      opcode field, and zeroes indicating those bits which need not
 542      match (and are presumably filled in by operands).  */
 543   aarch64_insn mask;
 544
 545   /* Instruction class.  */
 546   enum aarch64_insn_class iclass;
 547
 548   /* Enumerator identifier.  */
 549   enum aarch64_op op;
 550
 551   /* Which architecture variant provides this instruction.  */
 552   const aarch64_feature_set *avariant;
 553
 554   /* An array of operand codes.  Each code is an index into the
 555      operand table.  They appear in the order which the operands must
 556      appear in assembly code, and are terminated by a zero.  */
 557   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 558
 559   /* A list of operand qualifier code sequence.  Each operand qualifier
 560      code qualifies the corresponding operand code.  Each operand
 561      qualifier sequence specifies a valid opcode variant and related
 562      constraint on operands.  */
 563   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 564
 565   /* Flags providing information about this instruction */
 566   uint32_t flags;
 567
 568   /* If nonzero, this operand and operand 0 are both registers and
 569      are required to have the same register number.  */
 570   unsigned char tied_operand;
 571
 572   /* If non-NULL, a function to verify that a given instruction is valid.  */
 573   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 574 };
 575
 576 typedef struct aarch64_opcode aarch64_opcode;
 577
 578 /* Table describing all the AArch64 opcodes.  */
 579 extern aarch64_opcode aarch64_opcode_table[];
 580
 581 /* Opcode flags.  */
 582 #define F_ALIAS (1 << 0)
 583 #define F_HAS_ALIAS (1 << 1)
 584 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 585    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 586 #define F_P1 (1 << 2)
 587 #define F_P2 (2 << 2)
 588 #define F_P3 (3 << 2)
 589 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 590 #define F_COND (1 << 4)
 591 /* Instruction has the field of 'sf'.  */
 592 #define F_SF (1 << 5)
 593 /* Instruction has the field of 'size:Q'.  */
 594 #define F_SIZEQ (1 << 6)
 595 /* Floating-point instruction has the field of 'type'.  */
 596 #define F_FPTYPE (1 << 7)
 597 /* AdvSIMD scalar instruction has the field of 'size'.  */
 598 #define F_SSIZE (1 << 8)
 599 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 600 #define F_T (1 << 9)
 601 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 602 #define F_GPRSIZE_IN_Q (1 << 10)
 603 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 604 #define F_LDS_SIZE (1 << 11)
 605 /* Optional operand; assume maximum of 1 operand can be optional.  */
 606 #define F_OPD0_OPT (1 << 12)
 607 #define F_OPD1_OPT (2 << 12)
 608 #define F_OPD2_OPT (3 << 12)
 609 #define F_OPD3_OPT (4 << 12)
 610 #define F_OPD4_OPT (5 << 12)
 611 /* Default value for the optional operand when omitted from the assembly.  */
 612 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 613 /* Instruction that is an alias of another instruction needs to be
 614    encoded/decoded by converting it to/from the real form, followed by
 615    the encoding/decoding according to the rules of the real opcode.
 616    This compares to the direct coding using the alias's information.
 617    N.B. this flag requires F_ALIAS to be used together.  */
 618 #define F_CONV (1 << 20)
 619 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 620    friendly pseudo instruction available only in the assembly code (thus will
 621    not show up in the disassembly).  */
 622 #define F_PSEUDO (1 << 21)
 623 /* Instruction has miscellaneous encoding/decoding rules.  */
 624 #define F_MISC (1 << 22)
 625 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 626 #define F_N (1 << 23)
 627 /* Opcode dependent field.  */
 628 #define F_OD(X) (((X) & 0x7) << 24)
 629 /* Instruction has the field of 'sz'.  */
 630 #define F_LSE_SZ (1 << 27)
 631 /* Require an exact qualifier match, even for NIL qualifiers.  */
 632 #define F_STRICT (1ULL << 28)
 633 /* Next bit is 29.  */
 634
 635 static inline bfd_boolean
 636 alias_opcode_p (const aarch64_opcode *opcode)
 637 {
 638   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 639 }
 640
 641 static inline bfd_boolean
 642 opcode_has_alias (const aarch64_opcode *opcode)
 643 {
 644   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 645 }
 646
 647 /* Priority for disassembling preference.  */
 648 static inline int
 649 opcode_priority (const aarch64_opcode *opcode)
 650 {
 651   return (opcode->flags >> 2) & 0x3;
 652 }
 653
 654 static inline bfd_boolean
 655 pseudo_opcode_p (const aarch64_opcode *opcode)
 656 {
 657   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 658 }
 659
 660 static inline bfd_boolean
 661 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 662 {
 663   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 664     ? TRUE : FALSE;
 665 }
 666
 667 static inline aarch64_insn
 668 get_optional_operand_default_value (const aarch64_opcode *opcode)
 669 {
 670   return (opcode->flags >> 15) & 0x1f;
 671 }
 672
 673 static inline unsigned int
 674 get_opcode_dependent_value (const aarch64_opcode *opcode)
 675 {
 676   return (opcode->flags >> 24) & 0x7;
 677 }
 678
 679 static inline bfd_boolean
 680 opcode_has_special_coder (const aarch64_opcode *opcode)
 681 {
 682   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 683           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 684     : FALSE;
 685 }
 686 \f
 687 struct aarch64_name_value_pair
 688 {
 689   const char *  name;
 690   aarch64_insn  value;
 691 };
 692
 693 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 694 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 695 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 696 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 697
 698 typedef struct
 699 {
 700   const char *  name;
 701   aarch64_insn  value;
 702   uint32_t      flags;
 703 } aarch64_sys_reg;
 704
 705 extern const aarch64_sys_reg aarch64_sys_regs [];
 706 extern const aarch64_sys_reg aarch64_pstatefields [];
 707 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 708 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 709                                                 const aarch64_sys_reg *);
 710 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 711                                                     const aarch64_sys_reg *);
 712
 713 typedef struct
 714 {
 715   const char *name;
 716   uint32_t value;
 717   uint32_t flags ;
 718 } aarch64_sys_ins_reg;
 719
 720 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 721 extern bfd_boolean
 722 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 723                                  const aarch64_sys_ins_reg *);
 724
 725 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 726 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 727 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 728 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 729
 730 /* Shift/extending operator kinds.
 731    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 732 enum aarch64_modifier_kind
 733 {
 734   AARCH64_MOD_NONE,
 735   AARCH64_MOD_MSL,
 736   AARCH64_MOD_ROR,
 737   AARCH64_MOD_ASR,
 738   AARCH64_MOD_LSR,
 739   AARCH64_MOD_LSL,
 740   AARCH64_MOD_UXTB,
 741   AARCH64_MOD_UXTH,
 742   AARCH64_MOD_UXTW,
 743   AARCH64_MOD_UXTX,
 744   AARCH64_MOD_SXTB,
 745   AARCH64_MOD_SXTH,
 746   AARCH64_MOD_SXTW,
 747   AARCH64_MOD_SXTX,
 748 };
 749
 750 bfd_boolean
 751 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 752
 753 enum aarch64_modifier_kind
 754 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 755 /* Condition.  */
 756
 757 typedef struct
 758 {
 759   /* A list of names with the first one as the disassembly preference;
 760      terminated by NULL if fewer than 3.  */
 761   const char *names[3];
 762   aarch64_insn value;
 763 } aarch64_cond;
 764
 765 extern const aarch64_cond aarch64_conds[16];
 766
 767 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 768 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 769 \f
 770 /* Structure representing an operand.  */
 771
 772 struct aarch64_opnd_info
 773 {
 774   enum aarch64_opnd type;
 775   aarch64_opnd_qualifier_t qualifier;
 776   int idx;
 777
 778   union
 779     {
 780       struct
 781         {
 782           unsigned regno;
 783         } reg;
 784       struct
 785         {
 786           unsigned int regno;
 787           int64_t index;
 788         } reglane;
 789       /* e.g. LVn.  */
 790       struct
 791         {
 792           unsigned first_regno : 5;
 793           unsigned num_regs : 3;
 794           /* 1 if it is a list of reg element.  */
 795           unsigned has_index : 1;
 796           /* Lane index; valid only when has_index is 1.  */
 797           int64_t index;
 798         } reglist;
 799       /* e.g. immediate or pc relative address offset.  */
 800       struct
 801         {
 802           int64_t value;
 803           unsigned is_fp : 1;
 804         } imm;
 805       /* e.g. address in STR (register offset).  */
 806       struct
 807         {
 808           unsigned base_regno;
 809           struct
 810             {
 811               union
 812                 {
 813                   int imm;
 814                   unsigned regno;
 815                 };
 816               unsigned is_reg;
 817             } offset;
 818           unsigned pcrel : 1;           /* PC-relative.  */
 819           unsigned writeback : 1;
 820           unsigned preind : 1;          /* Pre-indexed.  */
 821           unsigned postind : 1;         /* Post-indexed.  */
 822         } addr;
 823       const aarch64_cond *cond;
 824       /* The encoding of the system register.  */
 825       aarch64_insn sysreg;
 826       /* The encoding of the PSTATE field.  */
 827       aarch64_insn pstatefield;
 828       const aarch64_sys_ins_reg *sysins_op;
 829       const struct aarch64_name_value_pair *barrier;
 830       const struct aarch64_name_value_pair *hint_option;
 831       const struct aarch64_name_value_pair *prfop;
 832     };
 833
 834   /* Operand shifter; in use when the operand is a register offset address,
 835      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 836   struct
 837     {
 838       enum aarch64_modifier_kind kind;
 839       int amount;
 840       unsigned operator_present: 1;     /* Only valid during encoding.  */
 841       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 842       unsigned amount_present: 1;
 843     } shifter;
 844
 845   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 846                            to be done on it.  In some (but not all) of these
 847                            cases, we need to tell libopcodes to skip the
 848                            constraint checking and the encoding for this
 849                            operand, so that the libopcodes can pick up the
 850                            right opcode before the operand is fixed-up.  This
 851                            flag should only be used during the
 852                            assembling/encoding.  */
 853   unsigned present:1;   /* Whether this operand is present in the assembly
 854                            line; not used during the disassembly.  */
 855 };
 856
 857 typedef struct aarch64_opnd_info aarch64_opnd_info;
 858
 859 /* Structure representing an instruction.
 860
 861    It is used during both the assembling and disassembling.  The assembler
 862    fills an aarch64_inst after a successful parsing and then passes it to the
 863    encoding routine to do the encoding.  During the disassembling, the
 864    disassembler calls the decoding routine to decode a binary instruction; on a
 865    successful return, such a structure will be filled with information of the
 866    instruction; then the disassembler uses the information to print out the
 867    instruction.  */
 868
 869 struct aarch64_inst
 870 {
 871   /* The value of the binary instruction.  */
 872   aarch64_insn value;
 873
 874   /* Corresponding opcode entry.  */
 875   const aarch64_opcode *opcode;
 876
 877   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 878   const aarch64_cond *cond;
 879
 880   /* Operands information.  */
 881   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 882 };
 883
 884 typedef struct aarch64_inst aarch64_inst;
 885 \f
 886 /* Diagnosis related declaration and interface.  */
 887
 888 /* Operand error kind enumerators.
 889
 890    AARCH64_OPDE_RECOVERABLE
 891      Less severe error found during the parsing, very possibly because that
 892      GAS has picked up a wrong instruction template for the parsing.
 893
 894    AARCH64_OPDE_SYNTAX_ERROR
 895      General syntax error; it can be either a user error, or simply because
 896      that GAS is trying a wrong instruction template.
 897
 898    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 899      Definitely a user syntax error.
 900
 901    AARCH64_OPDE_INVALID_VARIANT
 902      No syntax error, but the operands are not a valid combination, e.g.
 903      FMOV D0,S0
 904
 905    AARCH64_OPDE_UNTIED_OPERAND
 906      The asm failed to use the same register for a destination operand
 907      and a tied source operand.
 908
 909    AARCH64_OPDE_OUT_OF_RANGE
 910      Error about some immediate value out of a valid range.
 911
 912    AARCH64_OPDE_UNALIGNED
 913      Error about some immediate value not properly aligned (i.e. not being a
 914      multiple times of a certain value).
 915
 916    AARCH64_OPDE_REG_LIST
 917      Error about the register list operand having unexpected number of
 918      registers.
 919
 920    AARCH64_OPDE_OTHER_ERROR
 921      Error of the highest severity and used for any severe issue that does not
 922      fall into any of the above categories.
 923
 924    The enumerators are only interesting to GAS.  They are declared here (in
 925    libopcodes) because that some errors are detected (and then notified to GAS)
 926    by libopcodes (rather than by GAS solely).
 927
 928    The first three errors are only deteced by GAS while the
 929    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 930    only libopcodes has the information about the valid variants of each
 931    instruction.
 932
 933    The enumerators have an increasing severity.  This is helpful when there are
 934    multiple instruction templates available for a given mnemonic name (e.g.
 935    FMOV); this mechanism will help choose the most suitable template from which
 936    the generated diagnostics can most closely describe the issues, if any.  */
 937
 938 enum aarch64_operand_error_kind
 939 {
 940   AARCH64_OPDE_NIL,
 941   AARCH64_OPDE_RECOVERABLE,
 942   AARCH64_OPDE_SYNTAX_ERROR,
 943   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 944   AARCH64_OPDE_INVALID_VARIANT,
 945   AARCH64_OPDE_UNTIED_OPERAND,
 946   AARCH64_OPDE_OUT_OF_RANGE,
 947   AARCH64_OPDE_UNALIGNED,
 948   AARCH64_OPDE_REG_LIST,
 949   AARCH64_OPDE_OTHER_ERROR
 950 };
 951
 952 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 953 struct aarch64_operand_error
 954 {
 955   enum aarch64_operand_error_kind kind;
 956   int index;
 957   const char *error;
 958   int data[3];  /* Some data for extra information.  */
 959 };
 960
 961 typedef struct aarch64_operand_error aarch64_operand_error;
 962
 963 /* Encoding entrypoint.  */
 964
 965 extern int
 966 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 967                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 968                        aarch64_operand_error *);
 969
 970 extern const aarch64_opcode *
 971 aarch64_replace_opcode (struct aarch64_inst *,
 972                         const aarch64_opcode *);
 973
 974 /* Given the opcode enumerator OP, return the pointer to the corresponding
 975    opcode entry.  */
 976
 977 extern const aarch64_opcode *
 978 aarch64_get_opcode (enum aarch64_op);
 979
 980 /* Generate the string representation of an operand.  */
 981 extern void
 982 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 983                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 984
 985 /* Miscellaneous interface.  */
 986
 987 extern int
 988 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 989
 990 extern aarch64_opnd_qualifier_t
 991 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 992                                 const aarch64_opnd_qualifier_t, int);
 993
 994 extern int
 995 aarch64_num_of_operands (const aarch64_opcode *);
 996
 997 extern int
 998 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 999
1000 extern int
1001 aarch64_zero_register_p (const aarch64_opnd_info *);
1002
1003 extern int
1004 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1005
1006 /* Given an operand qualifier, return the expected data element size
1007    of a qualified operand.  */
1008 extern unsigned char
1009 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1010
1011 extern enum aarch64_operand_class
1012 aarch64_get_operand_class (enum aarch64_opnd);
1013
1014 extern const char *
1015 aarch64_get_operand_name (enum aarch64_opnd);
1016
1017 extern const char *
1018 aarch64_get_operand_desc (enum aarch64_opnd);
1019
1020 #ifdef DEBUG_AARCH64
1021 extern int debug_dump;
1022
1023 extern void
1024 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1025
1026 #define DEBUG_TRACE(M, ...)                                     \
1027   {                                                             \
1028     if (debug_dump)                                             \
1029       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1030   }
1031
1032 #define DEBUG_TRACE_IF(C, M, ...)                               \
1033   {                                                             \
1034     if (debug_dump && (C))                                      \
1035       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1036   }
1037 #else  /* !DEBUG_AARCH64 */
1038 #define DEBUG_TRACE(M, ...) ;
1039 #define DEBUG_TRACE_IF(C, M, ...) ;
1040 #endif /* DEBUG_AARCH64 */
1041
1042 extern const char *const aarch64_sve_pattern_array[32];
1043 extern const char *const aarch64_sve_prfop_array[16];
1044
1045 #ifdef __cplusplus
1046 }
1047 #endif
1048
1049 #endif /* OPCODE_AARCH64_H */