1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn
;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
42 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
43 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
44 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
45 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
46 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
47 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
48 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
49 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
52 /* Architectures are the sum of the base and extensions. */
53 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
55 | AARCH64_FEATURE_SIMD)
56 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
58 | AARCH64_FEATURE_SIMD \
59 | AARCH64_FEATURE_V8_1 \
60 | AARCH64_FEATURE_LSE \
61 | AARCH64_FEATURE_PAN \
62 | AARCH64_FEATURE_LOR \
63 | AARCH64_FEATURE_RDMA)
64 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
65 AARCH64_FEATURE_V8_2 \
66 | AARCH64_FEATURE_FP \
67 | AARCH64_FEATURE_SIMD \
68 | AARCH64_FEATURE_LSE \
69 | AARCH64_FEATURE_PAN \
70 | AARCH64_FEATURE_LOR \
71 | AARCH64_FEATURE_RDMA)
73 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
74 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
76 /* CPU-specific features. */
77 typedef unsigned long aarch64_feature_set
;
79 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
80 (((CPU) & (FEAT)) != 0)
82 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
85 (TARG) = (F1) | (F2); \
89 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
92 (TARG) = (F1) &~ (F2); \
96 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
98 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
99 (((OPC) & (FEAT)) != 0)
101 enum aarch64_operand_class
103 AARCH64_OPND_CLASS_NIL
,
104 AARCH64_OPND_CLASS_INT_REG
,
105 AARCH64_OPND_CLASS_MODIFIED_REG
,
106 AARCH64_OPND_CLASS_FP_REG
,
107 AARCH64_OPND_CLASS_SIMD_REG
,
108 AARCH64_OPND_CLASS_SIMD_ELEMENT
,
109 AARCH64_OPND_CLASS_SISD_REG
,
110 AARCH64_OPND_CLASS_SIMD_REGLIST
,
111 AARCH64_OPND_CLASS_CP_REG
,
112 AARCH64_OPND_CLASS_ADDRESS
,
113 AARCH64_OPND_CLASS_IMMEDIATE
,
114 AARCH64_OPND_CLASS_SYSTEM
,
115 AARCH64_OPND_CLASS_COND
,
118 /* Operand code that helps both parsing and coding.
119 Keep AARCH64_OPERANDS synced. */
123 AARCH64_OPND_NIL
, /* no operand---MUST BE FIRST!*/
125 AARCH64_OPND_Rd
, /* Integer register as destination. */
126 AARCH64_OPND_Rn
, /* Integer register as source. */
127 AARCH64_OPND_Rm
, /* Integer register as source. */
128 AARCH64_OPND_Rt
, /* Integer register used in ld/st instructions. */
129 AARCH64_OPND_Rt2
, /* Integer register used in ld/st pair instructions. */
130 AARCH64_OPND_Rs
, /* Integer register used in ld/st exclusive. */
131 AARCH64_OPND_Ra
, /* Integer register used in ddp_3src instructions. */
132 AARCH64_OPND_Rt_SYS
, /* Integer register used in system instructions. */
134 AARCH64_OPND_Rd_SP
, /* Integer Rd or SP. */
135 AARCH64_OPND_Rn_SP
, /* Integer Rn or SP. */
136 AARCH64_OPND_PAIRREG
, /* Paired register operand. */
137 AARCH64_OPND_Rm_EXT
, /* Integer Rm extended. */
138 AARCH64_OPND_Rm_SFT
, /* Integer Rm shifted. */
140 AARCH64_OPND_Fd
, /* Floating-point Fd. */
141 AARCH64_OPND_Fn
, /* Floating-point Fn. */
142 AARCH64_OPND_Fm
, /* Floating-point Fm. */
143 AARCH64_OPND_Fa
, /* Floating-point Fa. */
144 AARCH64_OPND_Ft
, /* Floating-point Ft. */
145 AARCH64_OPND_Ft2
, /* Floating-point Ft2. */
147 AARCH64_OPND_Sd
, /* AdvSIMD Scalar Sd. */
148 AARCH64_OPND_Sn
, /* AdvSIMD Scalar Sn. */
149 AARCH64_OPND_Sm
, /* AdvSIMD Scalar Sm. */
151 AARCH64_OPND_Vd
, /* AdvSIMD Vector Vd. */
152 AARCH64_OPND_Vn
, /* AdvSIMD Vector Vn. */
153 AARCH64_OPND_Vm
, /* AdvSIMD Vector Vm. */
154 AARCH64_OPND_VdD1
, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
155 AARCH64_OPND_VnD1
, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
156 AARCH64_OPND_Ed
, /* AdvSIMD Vector Element Vd. */
157 AARCH64_OPND_En
, /* AdvSIMD Vector Element Vn. */
158 AARCH64_OPND_Em
, /* AdvSIMD Vector Element Vm. */
159 AARCH64_OPND_LVn
, /* AdvSIMD Vector register list used in e.g. TBL. */
160 AARCH64_OPND_LVt
, /* AdvSIMD Vector register list used in ld/st. */
161 AARCH64_OPND_LVt_AL
, /* AdvSIMD Vector register list for loading single
162 structure to all lanes. */
163 AARCH64_OPND_LEt
, /* AdvSIMD Vector Element list. */
165 AARCH64_OPND_Cn
, /* Co-processor register in CRn field. */
166 AARCH64_OPND_Cm
, /* Co-processor register in CRm field. */
168 AARCH64_OPND_IDX
, /* AdvSIMD EXT index operand. */
169 AARCH64_OPND_IMM_VLSL
,/* Immediate for shifting vector registers left. */
170 AARCH64_OPND_IMM_VLSR
,/* Immediate for shifting vector registers right. */
171 AARCH64_OPND_SIMD_IMM
,/* AdvSIMD modified immediate without shift. */
172 AARCH64_OPND_SIMD_IMM_SFT
, /* AdvSIMD modified immediate with shift. */
173 AARCH64_OPND_SIMD_FPIMM
,/* AdvSIMD 8-bit fp immediate. */
174 AARCH64_OPND_SHLL_IMM
,/* Immediate shift for AdvSIMD SHLL instruction
176 AARCH64_OPND_IMM0
, /* Immediate for #0. */
177 AARCH64_OPND_FPIMM0
, /* Immediate for #0.0. */
178 AARCH64_OPND_FPIMM
, /* Floating-point Immediate. */
179 AARCH64_OPND_IMMR
, /* Immediate #<immr> in e.g. BFM. */
180 AARCH64_OPND_IMMS
, /* Immediate #<imms> in e.g. BFM. */
181 AARCH64_OPND_WIDTH
, /* Immediate #<width> in e.g. BFI. */
182 AARCH64_OPND_IMM
, /* Immediate. */
183 AARCH64_OPND_UIMM3_OP1
,/* Unsigned 3-bit immediate in the op1 field. */
184 AARCH64_OPND_UIMM3_OP2
,/* Unsigned 3-bit immediate in the op2 field. */
185 AARCH64_OPND_UIMM4
, /* Unsigned 4-bit immediate in the CRm field. */
186 AARCH64_OPND_UIMM7
, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
187 AARCH64_OPND_BIT_NUM
, /* Immediate. */
188 AARCH64_OPND_EXCEPTION
,/* imm16 operand in exception instructions. */
189 AARCH64_OPND_CCMP_IMM
,/* Immediate in conditional compare instructions. */
190 AARCH64_OPND_NZCV
, /* Flag bit specifier giving an alternative value for
191 each condition flag. */
193 AARCH64_OPND_LIMM
, /* Logical Immediate. */
194 AARCH64_OPND_AIMM
, /* Arithmetic immediate. */
195 AARCH64_OPND_HALF
, /* #<imm16>{, LSL #<shift>} operand in move wide. */
196 AARCH64_OPND_FBITS
, /* FP #<fbits> operand in e.g. SCVTF */
197 AARCH64_OPND_IMM_MOV
, /* Immediate operand for the MOV alias. */
199 AARCH64_OPND_COND
, /* Standard condition as the last operand. */
200 AARCH64_OPND_COND1
, /* Same as the above, but excluding AL and NV. */
202 AARCH64_OPND_ADDR_ADRP
, /* Memory address for ADRP */
203 AARCH64_OPND_ADDR_PCREL14
, /* 14-bit PC-relative address for e.g. TBZ. */
204 AARCH64_OPND_ADDR_PCREL19
, /* 19-bit PC-relative address for e.g. LDR. */
205 AARCH64_OPND_ADDR_PCREL21
, /* 21-bit PC-relative address for e.g. ADR. */
206 AARCH64_OPND_ADDR_PCREL26
, /* 26-bit PC-relative address for e.g. BL. */
208 AARCH64_OPND_ADDR_SIMPLE
, /* Address of ld/st exclusive. */
209 AARCH64_OPND_ADDR_REGOFF
, /* Address of register offset. */
210 AARCH64_OPND_ADDR_SIMM7
, /* Address of signed 7-bit immediate. */
211 AARCH64_OPND_ADDR_SIMM9
, /* Address of signed 9-bit immediate. */
212 AARCH64_OPND_ADDR_SIMM9_2
, /* Same as the above, but the immediate is
213 negative or unaligned and there is
214 no writeback allowed. This operand code
215 is only used to support the programmer-
216 friendly feature of using LDR/STR as the
217 the mnemonic name for LDUR/STUR instructions
218 wherever there is no ambiguity. */
219 AARCH64_OPND_ADDR_UIMM12
, /* Address of unsigned 12-bit immediate. */
220 AARCH64_OPND_SIMD_ADDR_SIMPLE
,/* Address of ld/st multiple structures. */
221 AARCH64_OPND_SIMD_ADDR_POST
, /* Address of ld/st multiple post-indexed. */
223 AARCH64_OPND_SYSREG
, /* System register operand. */
224 AARCH64_OPND_PSTATEFIELD
, /* PSTATE field name operand. */
225 AARCH64_OPND_SYSREG_AT
, /* System register <at_op> operand. */
226 AARCH64_OPND_SYSREG_DC
, /* System register <dc_op> operand. */
227 AARCH64_OPND_SYSREG_IC
, /* System register <ic_op> operand. */
228 AARCH64_OPND_SYSREG_TLBI
, /* System register <tlbi_op> operand. */
229 AARCH64_OPND_BARRIER
, /* Barrier operand. */
230 AARCH64_OPND_BARRIER_ISB
, /* Barrier operand for ISB. */
231 AARCH64_OPND_PRFOP
, /* Prefetch operation. */
234 /* Qualifier constrains an operand. It either specifies a variant of an
235 operand type or limits values available to an operand type.
237 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
239 enum aarch64_opnd_qualifier
241 /* Indicating no further qualification on an operand. */
242 AARCH64_OPND_QLF_NIL
,
244 /* Qualifying an operand which is a general purpose (integer) register;
245 indicating the operand data size or a specific register. */
246 AARCH64_OPND_QLF_W
, /* Wn, WZR or WSP. */
247 AARCH64_OPND_QLF_X
, /* Xn, XZR or XSP. */
248 AARCH64_OPND_QLF_WSP
, /* WSP. */
249 AARCH64_OPND_QLF_SP
, /* SP. */
251 /* Qualifying an operand which is a floating-point register, a SIMD
252 vector element or a SIMD vector element list; indicating operand data
253 size or the size of each SIMD vector element in the case of a SIMD
255 These qualifiers are also used to qualify an address operand to
256 indicate the size of data element a load/store instruction is
258 They are also used for the immediate shift operand in e.g. SSHR. Such
259 a use is only for the ease of operand encoding/decoding and qualifier
260 sequence matching; such a use should not be applied widely; use the value
261 constraint qualifiers for immediate operands wherever possible. */
262 AARCH64_OPND_QLF_S_B
,
263 AARCH64_OPND_QLF_S_H
,
264 AARCH64_OPND_QLF_S_S
,
265 AARCH64_OPND_QLF_S_D
,
266 AARCH64_OPND_QLF_S_Q
,
268 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
269 register list; indicating register shape.
270 They are also used for the immediate shift operand in e.g. SSHR. Such
271 a use is only for the ease of operand encoding/decoding and qualifier
272 sequence matching; such a use should not be applied widely; use the value
273 constraint qualifiers for immediate operands wherever possible. */
274 AARCH64_OPND_QLF_V_8B
,
275 AARCH64_OPND_QLF_V_16B
,
276 AARCH64_OPND_QLF_V_4H
,
277 AARCH64_OPND_QLF_V_8H
,
278 AARCH64_OPND_QLF_V_2S
,
279 AARCH64_OPND_QLF_V_4S
,
280 AARCH64_OPND_QLF_V_1D
,
281 AARCH64_OPND_QLF_V_2D
,
282 AARCH64_OPND_QLF_V_1Q
,
284 /* Constraint on value. */
285 AARCH64_OPND_QLF_imm_0_7
,
286 AARCH64_OPND_QLF_imm_0_15
,
287 AARCH64_OPND_QLF_imm_0_31
,
288 AARCH64_OPND_QLF_imm_0_63
,
289 AARCH64_OPND_QLF_imm_1_32
,
290 AARCH64_OPND_QLF_imm_1_64
,
292 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
294 AARCH64_OPND_QLF_LSL
,
295 AARCH64_OPND_QLF_MSL
,
297 /* Special qualifier helping retrieve qualifier information during the
298 decoding time (currently not in use). */
299 AARCH64_OPND_QLF_RETRIEVE
,
302 /* Instruction class. */
304 enum aarch64_insn_class
359 ldst_imm9
, /* immpost or immpre */
378 /* Opcode enumerators. */
422 OP_MOV_IMM_LOG
, /* MOV alias for moving bitmask immediate. */
423 OP_MOV_IMM_WIDE
, /* MOV alias for moving wide immediate. */
424 OP_MOV_IMM_WIDEN
, /* MOV alias for moving wide immediate (negated). */
426 OP_MOV_V
, /* MOV alias for moving vector register. */
455 OP_FCVTXN_S
, /* Scalar version. */
464 OP_TOTAL_NUM
, /* Pseudo. */
467 /* Maximum number of operands an instruction can have. */
468 #define AARCH64_MAX_OPND_NUM 6
469 /* Maximum number of qualifier sequences an instruction can have. */
470 #define AARCH64_MAX_QLF_SEQ_NUM 10
471 /* Operand qualifier typedef; optimized for the size. */
472 typedef unsigned char aarch64_opnd_qualifier_t
;
473 /* Operand qualifier sequence typedef. */
474 typedef aarch64_opnd_qualifier_t \
475 aarch64_opnd_qualifier_seq_t
[AARCH64_MAX_OPND_NUM
];
477 /* FIXME: improve the efficiency. */
478 static inline bfd_boolean
479 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t
*qualifiers
)
482 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
483 if (qualifiers
[i
] != AARCH64_OPND_QLF_NIL
)
488 /* This structure holds information for a particular opcode. */
490 struct aarch64_opcode
492 /* The name of the mnemonic. */
495 /* The opcode itself. Those bits which will be filled in with
496 operands are zeroes. */
499 /* The opcode mask. This is used by the disassembler. This is a
500 mask containing ones indicating those bits which must match the
501 opcode field, and zeroes indicating those bits which need not
502 match (and are presumably filled in by operands). */
505 /* Instruction class. */
506 enum aarch64_insn_class iclass
;
508 /* Enumerator identifier. */
511 /* Which architecture variant provides this instruction. */
512 const aarch64_feature_set
*avariant
;
514 /* An array of operand codes. Each code is an index into the
515 operand table. They appear in the order which the operands must
516 appear in assembly code, and are terminated by a zero. */
517 enum aarch64_opnd operands
[AARCH64_MAX_OPND_NUM
];
519 /* A list of operand qualifier code sequence. Each operand qualifier
520 code qualifies the corresponding operand code. Each operand
521 qualifier sequence specifies a valid opcode variant and related
522 constraint on operands. */
523 aarch64_opnd_qualifier_seq_t qualifiers_list
[AARCH64_MAX_QLF_SEQ_NUM
];
525 /* Flags providing information about this instruction */
529 typedef struct aarch64_opcode aarch64_opcode
;
531 /* Table describing all the AArch64 opcodes. */
532 extern aarch64_opcode aarch64_opcode_table
[];
535 #define F_ALIAS (1 << 0)
536 #define F_HAS_ALIAS (1 << 1)
537 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
538 is specified, it is the priority 0 by default, i.e. the lowest priority. */
539 #define F_P1 (1 << 2)
540 #define F_P2 (2 << 2)
541 #define F_P3 (3 << 2)
542 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
543 #define F_COND (1 << 4)
544 /* Instruction has the field of 'sf'. */
545 #define F_SF (1 << 5)
546 /* Instruction has the field of 'size:Q'. */
547 #define F_SIZEQ (1 << 6)
548 /* Floating-point instruction has the field of 'type'. */
549 #define F_FPTYPE (1 << 7)
550 /* AdvSIMD scalar instruction has the field of 'size'. */
551 #define F_SSIZE (1 << 8)
552 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
554 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
555 #define F_GPRSIZE_IN_Q (1 << 10)
556 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
557 #define F_LDS_SIZE (1 << 11)
558 /* Optional operand; assume maximum of 1 operand can be optional. */
559 #define F_OPD0_OPT (1 << 12)
560 #define F_OPD1_OPT (2 << 12)
561 #define F_OPD2_OPT (3 << 12)
562 #define F_OPD3_OPT (4 << 12)
563 #define F_OPD4_OPT (5 << 12)
564 /* Default value for the optional operand when omitted from the assembly. */
565 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
566 /* Instruction that is an alias of another instruction needs to be
567 encoded/decoded by converting it to/from the real form, followed by
568 the encoding/decoding according to the rules of the real opcode.
569 This compares to the direct coding using the alias's information.
570 N.B. this flag requires F_ALIAS to be used together. */
571 #define F_CONV (1 << 20)
572 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
573 friendly pseudo instruction available only in the assembly code (thus will
574 not show up in the disassembly). */
575 #define F_PSEUDO (1 << 21)
576 /* Instruction has miscellaneous encoding/decoding rules. */
577 #define F_MISC (1 << 22)
578 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
579 #define F_N (1 << 23)
580 /* Opcode dependent field. */
581 #define F_OD(X) (((X) & 0x7) << 24)
582 /* Instruction has the field of 'sz'. */
583 #define F_LSE_SZ (1 << 27)
584 /* Next bit is 28. */
586 static inline bfd_boolean
587 alias_opcode_p (const aarch64_opcode
*opcode
)
589 return (opcode
->flags
& F_ALIAS
) ? TRUE
: FALSE
;
592 static inline bfd_boolean
593 opcode_has_alias (const aarch64_opcode
*opcode
)
595 return (opcode
->flags
& F_HAS_ALIAS
) ? TRUE
: FALSE
;
598 /* Priority for disassembling preference. */
600 opcode_priority (const aarch64_opcode
*opcode
)
602 return (opcode
->flags
>> 2) & 0x3;
605 static inline bfd_boolean
606 pseudo_opcode_p (const aarch64_opcode
*opcode
)
608 return (opcode
->flags
& F_PSEUDO
) != 0lu ? TRUE
: FALSE
;
611 static inline bfd_boolean
612 optional_operand_p (const aarch64_opcode
*opcode
, unsigned int idx
)
614 return (((opcode
->flags
>> 12) & 0x7) == idx
+ 1)
618 static inline aarch64_insn
619 get_optional_operand_default_value (const aarch64_opcode
*opcode
)
621 return (opcode
->flags
>> 15) & 0x1f;
624 static inline unsigned int
625 get_opcode_dependent_value (const aarch64_opcode
*opcode
)
627 return (opcode
->flags
>> 24) & 0x7;
630 static inline bfd_boolean
631 opcode_has_special_coder (const aarch64_opcode
*opcode
)
633 return (opcode
->flags
& (F_SF
| F_LSE_SZ
| F_SIZEQ
| F_FPTYPE
| F_SSIZE
| F_T
634 | F_GPRSIZE_IN_Q
| F_LDS_SIZE
| F_MISC
| F_N
| F_COND
)) ? TRUE
638 struct aarch64_name_value_pair
644 extern const struct aarch64_name_value_pair aarch64_operand_modifiers
[];
645 extern const struct aarch64_name_value_pair aarch64_barrier_options
[16];
646 extern const struct aarch64_name_value_pair aarch64_prfops
[32];
655 extern const aarch64_sys_reg aarch64_sys_regs
[];
656 extern const aarch64_sys_reg aarch64_pstatefields
[];
657 extern bfd_boolean
aarch64_sys_reg_deprecated_p (const aarch64_sys_reg
*);
658 extern bfd_boolean
aarch64_sys_reg_supported_p (const aarch64_feature_set
,
659 const aarch64_sys_reg
*);
660 extern bfd_boolean
aarch64_pstatefield_supported_p (const aarch64_feature_set
,
661 const aarch64_sys_reg
*);
668 } aarch64_sys_ins_reg
;
670 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic
[];
671 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc
[];
672 extern const aarch64_sys_ins_reg aarch64_sys_regs_at
[];
673 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi
[];
675 /* Shift/extending operator kinds.
676 N.B. order is important; keep aarch64_operand_modifiers synced. */
677 enum aarch64_modifier_kind
696 aarch64_extend_operator_p (enum aarch64_modifier_kind
);
698 enum aarch64_modifier_kind
699 aarch64_get_operand_modifier (const struct aarch64_name_value_pair
*);
704 /* A list of names with the first one as the disassembly preference;
705 terminated by NULL if fewer than 3. */
706 const char *names
[3];
710 extern const aarch64_cond aarch64_conds
[16];
712 const aarch64_cond
* get_cond_from_value (aarch64_insn value
);
713 const aarch64_cond
* get_inverted_cond (const aarch64_cond
*cond
);
715 /* Structure representing an operand. */
717 struct aarch64_opnd_info
719 enum aarch64_opnd type
;
720 aarch64_opnd_qualifier_t qualifier
;
737 unsigned first_regno
: 5;
738 unsigned num_regs
: 3;
739 /* 1 if it is a list of reg element. */
740 unsigned has_index
: 1;
741 /* Lane index; valid only when has_index is 1. */
744 /* e.g. immediate or pc relative address offset. */
750 /* e.g. address in STR (register offset). */
763 unsigned pcrel
: 1; /* PC-relative. */
764 unsigned writeback
: 1;
765 unsigned preind
: 1; /* Pre-indexed. */
766 unsigned postind
: 1; /* Post-indexed. */
768 const aarch64_cond
*cond
;
769 /* The encoding of the system register. */
771 /* The encoding of the PSTATE field. */
772 aarch64_insn pstatefield
;
773 const aarch64_sys_ins_reg
*sysins_op
;
774 const struct aarch64_name_value_pair
*barrier
;
775 const struct aarch64_name_value_pair
*prfop
;
778 /* Operand shifter; in use when the operand is a register offset address,
779 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
782 enum aarch64_modifier_kind kind
;
784 unsigned operator_present
: 1; /* Only valid during encoding. */
785 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
786 unsigned amount_present
: 1;
789 unsigned skip
:1; /* Operand is not completed if there is a fixup needed
790 to be done on it. In some (but not all) of these
791 cases, we need to tell libopcodes to skip the
792 constraint checking and the encoding for this
793 operand, so that the libopcodes can pick up the
794 right opcode before the operand is fixed-up. This
795 flag should only be used during the
796 assembling/encoding. */
797 unsigned present
:1; /* Whether this operand is present in the assembly
798 line; not used during the disassembly. */
801 typedef struct aarch64_opnd_info aarch64_opnd_info
;
803 /* Structure representing an instruction.
805 It is used during both the assembling and disassembling. The assembler
806 fills an aarch64_inst after a successful parsing and then passes it to the
807 encoding routine to do the encoding. During the disassembling, the
808 disassembler calls the decoding routine to decode a binary instruction; on a
809 successful return, such a structure will be filled with information of the
810 instruction; then the disassembler uses the information to print out the
815 /* The value of the binary instruction. */
818 /* Corresponding opcode entry. */
819 const aarch64_opcode
*opcode
;
821 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
822 const aarch64_cond
*cond
;
824 /* Operands information. */
825 aarch64_opnd_info operands
[AARCH64_MAX_OPND_NUM
];
828 typedef struct aarch64_inst aarch64_inst
;
830 /* Diagnosis related declaration and interface. */
832 /* Operand error kind enumerators.
834 AARCH64_OPDE_RECOVERABLE
835 Less severe error found during the parsing, very possibly because that
836 GAS has picked up a wrong instruction template for the parsing.
838 AARCH64_OPDE_SYNTAX_ERROR
839 General syntax error; it can be either a user error, or simply because
840 that GAS is trying a wrong instruction template.
842 AARCH64_OPDE_FATAL_SYNTAX_ERROR
843 Definitely a user syntax error.
845 AARCH64_OPDE_INVALID_VARIANT
846 No syntax error, but the operands are not a valid combination, e.g.
849 AARCH64_OPDE_OUT_OF_RANGE
850 Error about some immediate value out of a valid range.
852 AARCH64_OPDE_UNALIGNED
853 Error about some immediate value not properly aligned (i.e. not being a
854 multiple times of a certain value).
856 AARCH64_OPDE_REG_LIST
857 Error about the register list operand having unexpected number of
860 AARCH64_OPDE_OTHER_ERROR
861 Error of the highest severity and used for any severe issue that does not
862 fall into any of the above categories.
864 The enumerators are only interesting to GAS. They are declared here (in
865 libopcodes) because that some errors are detected (and then notified to GAS)
866 by libopcodes (rather than by GAS solely).
868 The first three errors are only deteced by GAS while the
869 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
870 only libopcodes has the information about the valid variants of each
873 The enumerators have an increasing severity. This is helpful when there are
874 multiple instruction templates available for a given mnemonic name (e.g.
875 FMOV); this mechanism will help choose the most suitable template from which
876 the generated diagnostics can most closely describe the issues, if any. */
878 enum aarch64_operand_error_kind
881 AARCH64_OPDE_RECOVERABLE
,
882 AARCH64_OPDE_SYNTAX_ERROR
,
883 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
884 AARCH64_OPDE_INVALID_VARIANT
,
885 AARCH64_OPDE_OUT_OF_RANGE
,
886 AARCH64_OPDE_UNALIGNED
,
887 AARCH64_OPDE_REG_LIST
,
888 AARCH64_OPDE_OTHER_ERROR
891 /* N.B. GAS assumes that this structure work well with shallow copy. */
892 struct aarch64_operand_error
894 enum aarch64_operand_error_kind kind
;
897 int data
[3]; /* Some data for extra information. */
900 typedef struct aarch64_operand_error aarch64_operand_error
;
902 /* Encoding entrypoint. */
905 aarch64_opcode_encode (const aarch64_opcode
*, const aarch64_inst
*,
906 aarch64_insn
*, aarch64_opnd_qualifier_t
*,
907 aarch64_operand_error
*);
909 extern const aarch64_opcode
*
910 aarch64_replace_opcode (struct aarch64_inst
*,
911 const aarch64_opcode
*);
913 /* Given the opcode enumerator OP, return the pointer to the corresponding
916 extern const aarch64_opcode
*
917 aarch64_get_opcode (enum aarch64_op
);
919 /* Generate the string representation of an operand. */
921 aarch64_print_operand (char *, size_t, bfd_vma
, const aarch64_opcode
*,
922 const aarch64_opnd_info
*, int, int *, bfd_vma
*);
924 /* Miscellaneous interface. */
927 aarch64_operand_index (const enum aarch64_opnd
*, enum aarch64_opnd
);
929 extern aarch64_opnd_qualifier_t
930 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t
*, int,
931 const aarch64_opnd_qualifier_t
, int);
934 aarch64_num_of_operands (const aarch64_opcode
*);
937 aarch64_stack_pointer_p (const aarch64_opnd_info
*);
940 aarch64_zero_register_p (const aarch64_opnd_info
*);
943 aarch64_decode_insn (aarch64_insn
, aarch64_inst
*, bfd_boolean
);
945 /* Given an operand qualifier, return the expected data element size
946 of a qualified operand. */
948 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t
);
950 extern enum aarch64_operand_class
951 aarch64_get_operand_class (enum aarch64_opnd
);
954 aarch64_get_operand_name (enum aarch64_opnd
);
957 aarch64_get_operand_desc (enum aarch64_opnd
);
960 extern int debug_dump
;
963 aarch64_verbose (const char *, ...) __attribute__ ((format (printf
, 1, 2)));
965 #define DEBUG_TRACE(M, ...) \
968 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
971 #define DEBUG_TRACE_IF(C, M, ...) \
973 if (debug_dump && (C)) \
974 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
976 #else /* !DEBUG_AARCH64 */
977 #define DEBUG_TRACE(M, ...) ;
978 #define DEBUG_TRACE_IF(C, M, ...) ;
979 #endif /* DEBUG_AARCH64 */
985 #endif /* OPCODE_AARCH64_H */