include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Architectures are the sum of the base and extensions.  */
  68 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  69                                                  AARCH64_FEATURE_FP  \
  70                                                  | AARCH64_FEATURE_SIMD)
  71 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  72                                                  AARCH64_FEATURE_CRC    \
  73                                                  | AARCH64_FEATURE_V8_1 \
  74                                                  | AARCH64_FEATURE_LSE  \
  75                                                  | AARCH64_FEATURE_PAN  \
  76                                                  | AARCH64_FEATURE_LOR  \
  77                                                  | AARCH64_FEATURE_RDMA)
  78 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  79                                                  AARCH64_FEATURE_V8_2   \
  80                                                  | AARCH64_FEATURE_RAS)
  81 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  82                                                  AARCH64_FEATURE_V8_3   \
  83                                                  | AARCH64_FEATURE_RCPC \
  84                                                  | AARCH64_FEATURE_COMPNUM)
  85 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
  86                                                  AARCH64_FEATURE_V8_4   \
  87                                                  | AARCH64_FEATURE_DOTPROD \
  88                                                  | AARCH64_FEATURE_F16_FML)
  89 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
  90                                                  AARCH64_FEATURE_V8_5)
  91
  92
  93 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  94 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  95
  96 /* CPU-specific features.  */
  97 typedef unsigned long long aarch64_feature_set;
  98
  99 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 100   ((~(CPU) & (FEAT)) == 0)
 101
 102 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 103   (((CPU) & (FEAT)) != 0)
 104
 105 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 106   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 107
 108 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 109   do                                            \
 110     {                                           \
 111       (TARG) = (F1) | (F2);                     \
 112     }                                           \
 113   while (0)
 114
 115 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 116   do                                            \
 117     {                                           \
 118       (TARG) = (F1) &~ (F2);                    \
 119     }                                           \
 120   while (0)
 121
 122 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 123
 124 enum aarch64_operand_class
 125 {
 126   AARCH64_OPND_CLASS_NIL,
 127   AARCH64_OPND_CLASS_INT_REG,
 128   AARCH64_OPND_CLASS_MODIFIED_REG,
 129   AARCH64_OPND_CLASS_FP_REG,
 130   AARCH64_OPND_CLASS_SIMD_REG,
 131   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 132   AARCH64_OPND_CLASS_SISD_REG,
 133   AARCH64_OPND_CLASS_SIMD_REGLIST,
 134   AARCH64_OPND_CLASS_SVE_REG,
 135   AARCH64_OPND_CLASS_PRED_REG,
 136   AARCH64_OPND_CLASS_ADDRESS,
 137   AARCH64_OPND_CLASS_IMMEDIATE,
 138   AARCH64_OPND_CLASS_SYSTEM,
 139   AARCH64_OPND_CLASS_COND,
 140 };
 141
 142 /* Operand code that helps both parsing and coding.
 143    Keep AARCH64_OPERANDS synced.  */
 144
 145 enum aarch64_opnd
 146 {
 147   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 148
 149   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 150   AARCH64_OPND_Rn,      /* Integer register as source.  */
 151   AARCH64_OPND_Rm,      /* Integer register as source.  */
 152   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 153   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 154   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 155   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 156   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 157
 158   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 159   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 160   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 161   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 162   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 163   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 164
 165   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 166   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 167   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 168   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 169   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 170   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 171
 172   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 173   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 174   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 175
 176   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 177   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 178   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 179   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 180   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 181   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 182   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 183   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 184   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 185   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 186                            qualifier is S_H.  */
 187   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 188   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 189   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 190                            structure to all lanes.  */
 191   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 192
 193   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 194   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 195
 196   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 197   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 198   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 199   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 200   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 201   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 202   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 203   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 204                            (no encoding).  */
 205   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 206   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 207   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 208   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 209   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 210   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 211   AARCH64_OPND_IMM,     /* Immediate.  */
 212   AARCH64_OPND_IMM_2,   /* Immediate.  */
 213   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 214   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 215   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 216   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 217   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 218   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 219   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 220   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 221   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 222                            each condition flag.  */
 223
 224   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 225   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 226   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 227   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 228   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 229   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 230   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 231   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 232
 233   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 234   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 235
 236   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 237   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 238   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 239   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 240   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 241
 242   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 243   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 244   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 245   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 246   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 247                                    negative or unaligned and there is
 248                                    no writeback allowed.  This operand code
 249                                    is only used to support the programmer-
 250                                    friendly feature of using LDR/STR as the
 251                                    the mnemonic name for LDUR/STUR instructions
 252                                    wherever there is no ambiguity.  */
 253   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 254   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 255   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 256   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 257   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 258
 259   AARCH64_OPND_SYSREG,          /* System register operand.  */
 260   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 261   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 262   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 263   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 264   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 265   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 266   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 267   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 268   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 269
 270   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 271   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 272   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 273   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 274   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 275   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 276   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 277   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 278   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 279   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 280   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 281   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 282   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 283   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 284   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 285   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 286   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 287   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 288   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 289   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 290   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 291   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 292   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 293   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 294   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 295                                        Bit 14 controls S/U choice.  */
 296   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 297                                        Bit 22 controls S/U choice.  */
 298   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 299                                        Bit 14 controls S/U choice.  */
 300   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 301                                        Bit 22 controls S/U choice.  */
 302   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 303                                        Bit 14 controls S/U choice.  */
 304   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 305                                        Bit 22 controls S/U choice.  */
 306   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 307                                        Bit 14 controls S/U choice.  */
 308   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 309                                        Bit 22 controls S/U choice.  */
 310   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 311   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 312   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 313   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 314   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 315   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 316   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 317   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 318   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 319   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 320   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 321   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 322   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 323   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 324   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 325   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 326   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 327   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 328   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 329   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 330   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 331   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 332   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 333   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 334   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 335   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 336   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 337   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 338   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 339   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 340   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 341   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 342   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 343   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 344   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 345   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 346   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 347   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 348   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 349   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 350   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 351   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 352   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 353   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 354   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 355   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 356   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 357   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 358   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 359   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 360   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 361   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 362   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 363   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 364   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 365   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 366   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 367   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 368   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 369   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 370   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 371 };
 372
 373 /* Qualifier constrains an operand.  It either specifies a variant of an
 374    operand type or limits values available to an operand type.
 375
 376    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 377
 378 enum aarch64_opnd_qualifier
 379 {
 380   /* Indicating no further qualification on an operand.  */
 381   AARCH64_OPND_QLF_NIL,
 382
 383   /* Qualifying an operand which is a general purpose (integer) register;
 384      indicating the operand data size or a specific register.  */
 385   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 386   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 387   AARCH64_OPND_QLF_WSP, /* WSP.  */
 388   AARCH64_OPND_QLF_SP,  /* SP.  */
 389
 390   /* Qualifying an operand which is a floating-point register, a SIMD
 391      vector element or a SIMD vector element list; indicating operand data
 392      size or the size of each SIMD vector element in the case of a SIMD
 393      vector element list.
 394      These qualifiers are also used to qualify an address operand to
 395      indicate the size of data element a load/store instruction is
 396      accessing.
 397      They are also used for the immediate shift operand in e.g. SSHR.  Such
 398      a use is only for the ease of operand encoding/decoding and qualifier
 399      sequence matching; such a use should not be applied widely; use the value
 400      constraint qualifiers for immediate operands wherever possible.  */
 401   AARCH64_OPND_QLF_S_B,
 402   AARCH64_OPND_QLF_S_H,
 403   AARCH64_OPND_QLF_S_S,
 404   AARCH64_OPND_QLF_S_D,
 405   AARCH64_OPND_QLF_S_Q,
 406   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 407      are selected by the instruction.  Other than that it has no difference
 408      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 409      reasons and is an exception from normal AArch64 disassembly scheme.  */
 410   AARCH64_OPND_QLF_S_4B,
 411
 412   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 413      register list; indicating register shape.
 414      They are also used for the immediate shift operand in e.g. SSHR.  Such
 415      a use is only for the ease of operand encoding/decoding and qualifier
 416      sequence matching; such a use should not be applied widely; use the value
 417      constraint qualifiers for immediate operands wherever possible.  */
 418   AARCH64_OPND_QLF_V_4B,
 419   AARCH64_OPND_QLF_V_8B,
 420   AARCH64_OPND_QLF_V_16B,
 421   AARCH64_OPND_QLF_V_2H,
 422   AARCH64_OPND_QLF_V_4H,
 423   AARCH64_OPND_QLF_V_8H,
 424   AARCH64_OPND_QLF_V_2S,
 425   AARCH64_OPND_QLF_V_4S,
 426   AARCH64_OPND_QLF_V_1D,
 427   AARCH64_OPND_QLF_V_2D,
 428   AARCH64_OPND_QLF_V_1Q,
 429
 430   AARCH64_OPND_QLF_P_Z,
 431   AARCH64_OPND_QLF_P_M,
 432
 433   /* Constraint on value.  */
 434   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 435   AARCH64_OPND_QLF_imm_0_7,
 436   AARCH64_OPND_QLF_imm_0_15,
 437   AARCH64_OPND_QLF_imm_0_31,
 438   AARCH64_OPND_QLF_imm_0_63,
 439   AARCH64_OPND_QLF_imm_1_32,
 440   AARCH64_OPND_QLF_imm_1_64,
 441
 442   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 443      or shift-ones.  */
 444   AARCH64_OPND_QLF_LSL,
 445   AARCH64_OPND_QLF_MSL,
 446
 447   /* Special qualifier helping retrieve qualifier information during the
 448      decoding time (currently not in use).  */
 449   AARCH64_OPND_QLF_RETRIEVE,
 450 };
 451 \f
 452 /* Instruction class.  */
 453
 454 enum aarch64_insn_class
 455 {
 456   addsub_carry,
 457   addsub_ext,
 458   addsub_imm,
 459   addsub_shift,
 460   asimdall,
 461   asimddiff,
 462   asimdelem,
 463   asimdext,
 464   asimdimm,
 465   asimdins,
 466   asimdmisc,
 467   asimdperm,
 468   asimdsame,
 469   asimdshf,
 470   asimdtbl,
 471   asisddiff,
 472   asisdelem,
 473   asisdlse,
 474   asisdlsep,
 475   asisdlso,
 476   asisdlsop,
 477   asisdmisc,
 478   asisdone,
 479   asisdpair,
 480   asisdsame,
 481   asisdshf,
 482   bitfield,
 483   branch_imm,
 484   branch_reg,
 485   compbranch,
 486   condbranch,
 487   condcmp_imm,
 488   condcmp_reg,
 489   condsel,
 490   cryptoaes,
 491   cryptosha2,
 492   cryptosha3,
 493   dp_1src,
 494   dp_2src,
 495   dp_3src,
 496   exception,
 497   extract,
 498   float2fix,
 499   float2int,
 500   floatccmp,
 501   floatcmp,
 502   floatdp1,
 503   floatdp2,
 504   floatdp3,
 505   floatimm,
 506   floatsel,
 507   ldst_immpost,
 508   ldst_immpre,
 509   ldst_imm9,    /* immpost or immpre */
 510   ldst_imm10,   /* LDRAA/LDRAB */
 511   ldst_pos,
 512   ldst_regoff,
 513   ldst_unpriv,
 514   ldst_unscaled,
 515   ldstexcl,
 516   ldstnapair_offs,
 517   ldstpair_off,
 518   ldstpair_indexed,
 519   loadlit,
 520   log_imm,
 521   log_shift,
 522   lse_atomic,
 523   movewide,
 524   pcreladdr,
 525   ic_system,
 526   sve_cpy,
 527   sve_index,
 528   sve_limm,
 529   sve_misc,
 530   sve_movprfx,
 531   sve_pred_zm,
 532   sve_shift_pred,
 533   sve_shift_unpred,
 534   sve_size_bhs,
 535   sve_size_bhsd,
 536   sve_size_hsd,
 537   sve_size_sd,
 538   testbranch,
 539   cryptosm3,
 540   cryptosm4,
 541   dotproduct,
 542 };
 543
 544 /* Opcode enumerators.  */
 545
 546 enum aarch64_op
 547 {
 548   OP_NIL,
 549   OP_STRB_POS,
 550   OP_LDRB_POS,
 551   OP_LDRSB_POS,
 552   OP_STRH_POS,
 553   OP_LDRH_POS,
 554   OP_LDRSH_POS,
 555   OP_STR_POS,
 556   OP_LDR_POS,
 557   OP_STRF_POS,
 558   OP_LDRF_POS,
 559   OP_LDRSW_POS,
 560   OP_PRFM_POS,
 561
 562   OP_STURB,
 563   OP_LDURB,
 564   OP_LDURSB,
 565   OP_STURH,
 566   OP_LDURH,
 567   OP_LDURSH,
 568   OP_STUR,
 569   OP_LDUR,
 570   OP_STURV,
 571   OP_LDURV,
 572   OP_LDURSW,
 573   OP_PRFUM,
 574
 575   OP_LDR_LIT,
 576   OP_LDRV_LIT,
 577   OP_LDRSW_LIT,
 578   OP_PRFM_LIT,
 579
 580   OP_ADD,
 581   OP_B,
 582   OP_BL,
 583
 584   OP_MOVN,
 585   OP_MOVZ,
 586   OP_MOVK,
 587
 588   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 589   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 590   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 591
 592   OP_MOV_V,             /* MOV alias for moving vector register.  */
 593
 594   OP_ASR_IMM,
 595   OP_LSR_IMM,
 596   OP_LSL_IMM,
 597
 598   OP_BIC,
 599
 600   OP_UBFX,
 601   OP_BFXIL,
 602   OP_SBFX,
 603   OP_SBFIZ,
 604   OP_BFI,
 605   OP_BFC,               /* ARMv8.2.  */
 606   OP_UBFIZ,
 607   OP_UXTB,
 608   OP_UXTH,
 609   OP_UXTW,
 610
 611   OP_CINC,
 612   OP_CINV,
 613   OP_CNEG,
 614   OP_CSET,
 615   OP_CSETM,
 616
 617   OP_FCVT,
 618   OP_FCVTN,
 619   OP_FCVTN2,
 620   OP_FCVTL,
 621   OP_FCVTL2,
 622   OP_FCVTXN_S,          /* Scalar version.  */
 623
 624   OP_ROR_IMM,
 625
 626   OP_SXTL,
 627   OP_SXTL2,
 628   OP_UXTL,
 629   OP_UXTL2,
 630
 631   OP_MOV_P_P,
 632   OP_MOV_Z_P_Z,
 633   OP_MOV_Z_V,
 634   OP_MOV_Z_Z,
 635   OP_MOV_Z_Zi,
 636   OP_MOVM_P_P_P,
 637   OP_MOVS_P_P,
 638   OP_MOVZS_P_P_P,
 639   OP_MOVZ_P_P_P,
 640   OP_NOTS_P_P_P_Z,
 641   OP_NOT_P_P_P_Z,
 642
 643   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 644
 645   OP_TOTAL_NUM,         /* Pseudo.  */
 646 };
 647
 648 /* Error types.  */
 649 enum err_type
 650 {
 651   ERR_OK,
 652   ERR_UND,
 653   ERR_UNP,
 654   ERR_NYI,
 655   ERR_VFI,
 656   ERR_NR_ENTRIES
 657 };
 658
 659 /* Maximum number of operands an instruction can have.  */
 660 #define AARCH64_MAX_OPND_NUM 6
 661 /* Maximum number of qualifier sequences an instruction can have.  */
 662 #define AARCH64_MAX_QLF_SEQ_NUM 10
 663 /* Operand qualifier typedef; optimized for the size.  */
 664 typedef unsigned char aarch64_opnd_qualifier_t;
 665 /* Operand qualifier sequence typedef.  */
 666 typedef aarch64_opnd_qualifier_t        \
 667           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 668
 669 /* FIXME: improve the efficiency.  */
 670 static inline bfd_boolean
 671 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 672 {
 673   int i;
 674   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 675     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 676       return FALSE;
 677   return TRUE;
 678 }
 679
 680 /*  Forward declare error reporting type.  */
 681 typedef struct aarch64_operand_error aarch64_operand_error;
 682 /* Forward declare instruction sequence type.  */
 683 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 684 /* Forward declare instruction definition.  */
 685 typedef struct aarch64_inst aarch64_inst;
 686
 687 /* This structure holds information for a particular opcode.  */
 688
 689 struct aarch64_opcode
 690 {
 691   /* The name of the mnemonic.  */
 692   const char *name;
 693
 694   /* The opcode itself.  Those bits which will be filled in with
 695      operands are zeroes.  */
 696   aarch64_insn opcode;
 697
 698   /* The opcode mask.  This is used by the disassembler.  This is a
 699      mask containing ones indicating those bits which must match the
 700      opcode field, and zeroes indicating those bits which need not
 701      match (and are presumably filled in by operands).  */
 702   aarch64_insn mask;
 703
 704   /* Instruction class.  */
 705   enum aarch64_insn_class iclass;
 706
 707   /* Enumerator identifier.  */
 708   enum aarch64_op op;
 709
 710   /* Which architecture variant provides this instruction.  */
 711   const aarch64_feature_set *avariant;
 712
 713   /* An array of operand codes.  Each code is an index into the
 714      operand table.  They appear in the order which the operands must
 715      appear in assembly code, and are terminated by a zero.  */
 716   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 717
 718   /* A list of operand qualifier code sequence.  Each operand qualifier
 719      code qualifies the corresponding operand code.  Each operand
 720      qualifier sequence specifies a valid opcode variant and related
 721      constraint on operands.  */
 722   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 723
 724   /* Flags providing information about this instruction */
 725   uint64_t flags;
 726
 727   /* Extra constraints on the instruction that the verifier checks.  */
 728   uint32_t constraints;
 729
 730   /* If nonzero, this operand and operand 0 are both registers and
 731      are required to have the same register number.  */
 732   unsigned char tied_operand;
 733
 734   /* If non-NULL, a function to verify that a given instruction is valid.  */
 735   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 736                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 737                               struct aarch64_instr_sequence *);
 738 };
 739
 740 typedef struct aarch64_opcode aarch64_opcode;
 741
 742 /* Table describing all the AArch64 opcodes.  */
 743 extern aarch64_opcode aarch64_opcode_table[];
 744
 745 /* Opcode flags.  */
 746 #define F_ALIAS (1 << 0)
 747 #define F_HAS_ALIAS (1 << 1)
 748 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 749    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 750 #define F_P1 (1 << 2)
 751 #define F_P2 (2 << 2)
 752 #define F_P3 (3 << 2)
 753 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 754 #define F_COND (1 << 4)
 755 /* Instruction has the field of 'sf'.  */
 756 #define F_SF (1 << 5)
 757 /* Instruction has the field of 'size:Q'.  */
 758 #define F_SIZEQ (1 << 6)
 759 /* Floating-point instruction has the field of 'type'.  */
 760 #define F_FPTYPE (1 << 7)
 761 /* AdvSIMD scalar instruction has the field of 'size'.  */
 762 #define F_SSIZE (1 << 8)
 763 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 764 #define F_T (1 << 9)
 765 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 766 #define F_GPRSIZE_IN_Q (1 << 10)
 767 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 768 #define F_LDS_SIZE (1 << 11)
 769 /* Optional operand; assume maximum of 1 operand can be optional.  */
 770 #define F_OPD0_OPT (1 << 12)
 771 #define F_OPD1_OPT (2 << 12)
 772 #define F_OPD2_OPT (3 << 12)
 773 #define F_OPD3_OPT (4 << 12)
 774 #define F_OPD4_OPT (5 << 12)
 775 /* Default value for the optional operand when omitted from the assembly.  */
 776 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 777 /* Instruction that is an alias of another instruction needs to be
 778    encoded/decoded by converting it to/from the real form, followed by
 779    the encoding/decoding according to the rules of the real opcode.
 780    This compares to the direct coding using the alias's information.
 781    N.B. this flag requires F_ALIAS to be used together.  */
 782 #define F_CONV (1 << 20)
 783 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 784    friendly pseudo instruction available only in the assembly code (thus will
 785    not show up in the disassembly).  */
 786 #define F_PSEUDO (1 << 21)
 787 /* Instruction has miscellaneous encoding/decoding rules.  */
 788 #define F_MISC (1 << 22)
 789 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 790 #define F_N (1 << 23)
 791 /* Opcode dependent field.  */
 792 #define F_OD(X) (((X) & 0x7) << 24)
 793 /* Instruction has the field of 'sz'.  */
 794 #define F_LSE_SZ (1 << 27)
 795 /* Require an exact qualifier match, even for NIL qualifiers.  */
 796 #define F_STRICT (1ULL << 28)
 797 /* This system instruction is used to read system registers.  */
 798 #define F_SYS_READ (1ULL << 29)
 799 /* This system instruction is used to write system registers.  */
 800 #define F_SYS_WRITE (1ULL << 30)
 801 /* This instruction has an extra constraint on it that imposes a requirement on
 802    subsequent instructions.  */
 803 #define F_SCAN (1ULL << 31)
 804 /* Next bit is 32.  */
 805
 806 /* Instruction constraints.  */
 807 /* This instruction has a predication constraint on the instruction at PC+4.  */
 808 #define C_SCAN_MOVPRFX (1U << 0)
 809 /* This instruction's operation width is determined by the operand with the
 810    largest element size.  */
 811 #define C_MAX_ELEM (1U << 1)
 812 /* Next bit is 2.  */
 813
 814 static inline bfd_boolean
 815 alias_opcode_p (const aarch64_opcode *opcode)
 816 {
 817   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 818 }
 819
 820 static inline bfd_boolean
 821 opcode_has_alias (const aarch64_opcode *opcode)
 822 {
 823   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 824 }
 825
 826 /* Priority for disassembling preference.  */
 827 static inline int
 828 opcode_priority (const aarch64_opcode *opcode)
 829 {
 830   return (opcode->flags >> 2) & 0x3;
 831 }
 832
 833 static inline bfd_boolean
 834 pseudo_opcode_p (const aarch64_opcode *opcode)
 835 {
 836   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 837 }
 838
 839 static inline bfd_boolean
 840 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 841 {
 842   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 843     ? TRUE : FALSE;
 844 }
 845
 846 static inline aarch64_insn
 847 get_optional_operand_default_value (const aarch64_opcode *opcode)
 848 {
 849   return (opcode->flags >> 15) & 0x1f;
 850 }
 851
 852 static inline unsigned int
 853 get_opcode_dependent_value (const aarch64_opcode *opcode)
 854 {
 855   return (opcode->flags >> 24) & 0x7;
 856 }
 857
 858 static inline bfd_boolean
 859 opcode_has_special_coder (const aarch64_opcode *opcode)
 860 {
 861   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 862           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 863     : FALSE;
 864 }
 865 \f
 866 struct aarch64_name_value_pair
 867 {
 868   const char *  name;
 869   aarch64_insn  value;
 870 };
 871
 872 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 873 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 874 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 875 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 876
 877 typedef struct
 878 {
 879   const char *  name;
 880   aarch64_insn  value;
 881   uint32_t      flags;
 882 } aarch64_sys_reg;
 883
 884 extern const aarch64_sys_reg aarch64_sys_regs [];
 885 extern const aarch64_sys_reg aarch64_pstatefields [];
 886 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 887 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 888                                                 const aarch64_sys_reg *);
 889 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 890                                                     const aarch64_sys_reg *);
 891
 892 typedef struct
 893 {
 894   const char *name;
 895   uint32_t value;
 896   uint32_t flags ;
 897 } aarch64_sys_ins_reg;
 898
 899 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 900 extern bfd_boolean
 901 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 902                                  const aarch64_sys_ins_reg *);
 903
 904 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 905 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 906 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 907 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 908
 909 /* Shift/extending operator kinds.
 910    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 911 enum aarch64_modifier_kind
 912 {
 913   AARCH64_MOD_NONE,
 914   AARCH64_MOD_MSL,
 915   AARCH64_MOD_ROR,
 916   AARCH64_MOD_ASR,
 917   AARCH64_MOD_LSR,
 918   AARCH64_MOD_LSL,
 919   AARCH64_MOD_UXTB,
 920   AARCH64_MOD_UXTH,
 921   AARCH64_MOD_UXTW,
 922   AARCH64_MOD_UXTX,
 923   AARCH64_MOD_SXTB,
 924   AARCH64_MOD_SXTH,
 925   AARCH64_MOD_SXTW,
 926   AARCH64_MOD_SXTX,
 927   AARCH64_MOD_MUL,
 928   AARCH64_MOD_MUL_VL,
 929 };
 930
 931 bfd_boolean
 932 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 933
 934 enum aarch64_modifier_kind
 935 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 936 /* Condition.  */
 937
 938 typedef struct
 939 {
 940   /* A list of names with the first one as the disassembly preference;
 941      terminated by NULL if fewer than 3.  */
 942   const char *names[4];
 943   aarch64_insn value;
 944 } aarch64_cond;
 945
 946 extern const aarch64_cond aarch64_conds[16];
 947
 948 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 949 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 950 \f
 951 /* Structure representing an operand.  */
 952
 953 struct aarch64_opnd_info
 954 {
 955   enum aarch64_opnd type;
 956   aarch64_opnd_qualifier_t qualifier;
 957   int idx;
 958
 959   union
 960     {
 961       struct
 962         {
 963           unsigned regno;
 964         } reg;
 965       struct
 966         {
 967           unsigned int regno;
 968           int64_t index;
 969         } reglane;
 970       /* e.g. LVn.  */
 971       struct
 972         {
 973           unsigned first_regno : 5;
 974           unsigned num_regs : 3;
 975           /* 1 if it is a list of reg element.  */
 976           unsigned has_index : 1;
 977           /* Lane index; valid only when has_index is 1.  */
 978           int64_t index;
 979         } reglist;
 980       /* e.g. immediate or pc relative address offset.  */
 981       struct
 982         {
 983           int64_t value;
 984           unsigned is_fp : 1;
 985         } imm;
 986       /* e.g. address in STR (register offset).  */
 987       struct
 988         {
 989           unsigned base_regno;
 990           struct
 991             {
 992               union
 993                 {
 994                   int imm;
 995                   unsigned regno;
 996                 };
 997               unsigned is_reg;
 998             } offset;
 999           unsigned pcrel : 1;           /* PC-relative.  */
1000           unsigned writeback : 1;
1001           unsigned preind : 1;          /* Pre-indexed.  */
1002           unsigned postind : 1;         /* Post-indexed.  */
1003         } addr;
1004
1005       struct
1006         {
1007           /* The encoding of the system register.  */
1008           aarch64_insn value;
1009
1010           /* The system register flags.  */
1011           uint32_t flags;
1012         } sysreg;
1013
1014       const aarch64_cond *cond;
1015       /* The encoding of the PSTATE field.  */
1016       aarch64_insn pstatefield;
1017       const aarch64_sys_ins_reg *sysins_op;
1018       const struct aarch64_name_value_pair *barrier;
1019       const struct aarch64_name_value_pair *hint_option;
1020       const struct aarch64_name_value_pair *prfop;
1021     };
1022
1023   /* Operand shifter; in use when the operand is a register offset address,
1024      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1025   struct
1026     {
1027       enum aarch64_modifier_kind kind;
1028       unsigned operator_present: 1;     /* Only valid during encoding.  */
1029       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1030       unsigned amount_present: 1;
1031       int64_t amount;
1032     } shifter;
1033
1034   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1035                            to be done on it.  In some (but not all) of these
1036                            cases, we need to tell libopcodes to skip the
1037                            constraint checking and the encoding for this
1038                            operand, so that the libopcodes can pick up the
1039                            right opcode before the operand is fixed-up.  This
1040                            flag should only be used during the
1041                            assembling/encoding.  */
1042   unsigned present:1;   /* Whether this operand is present in the assembly
1043                            line; not used during the disassembly.  */
1044 };
1045
1046 typedef struct aarch64_opnd_info aarch64_opnd_info;
1047
1048 /* Structure representing an instruction.
1049
1050    It is used during both the assembling and disassembling.  The assembler
1051    fills an aarch64_inst after a successful parsing and then passes it to the
1052    encoding routine to do the encoding.  During the disassembling, the
1053    disassembler calls the decoding routine to decode a binary instruction; on a
1054    successful return, such a structure will be filled with information of the
1055    instruction; then the disassembler uses the information to print out the
1056    instruction.  */
1057
1058 struct aarch64_inst
1059 {
1060   /* The value of the binary instruction.  */
1061   aarch64_insn value;
1062
1063   /* Corresponding opcode entry.  */
1064   const aarch64_opcode *opcode;
1065
1066   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1067   const aarch64_cond *cond;
1068
1069   /* Operands information.  */
1070   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1071 };
1072
1073 \f
1074 /* Diagnosis related declaration and interface.  */
1075
1076 /* Operand error kind enumerators.
1077
1078    AARCH64_OPDE_RECOVERABLE
1079      Less severe error found during the parsing, very possibly because that
1080      GAS has picked up a wrong instruction template for the parsing.
1081
1082    AARCH64_OPDE_SYNTAX_ERROR
1083      General syntax error; it can be either a user error, or simply because
1084      that GAS is trying a wrong instruction template.
1085
1086    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1087      Definitely a user syntax error.
1088
1089    AARCH64_OPDE_INVALID_VARIANT
1090      No syntax error, but the operands are not a valid combination, e.g.
1091      FMOV D0,S0
1092
1093    AARCH64_OPDE_UNTIED_OPERAND
1094      The asm failed to use the same register for a destination operand
1095      and a tied source operand.
1096
1097    AARCH64_OPDE_OUT_OF_RANGE
1098      Error about some immediate value out of a valid range.
1099
1100    AARCH64_OPDE_UNALIGNED
1101      Error about some immediate value not properly aligned (i.e. not being a
1102      multiple times of a certain value).
1103
1104    AARCH64_OPDE_REG_LIST
1105      Error about the register list operand having unexpected number of
1106      registers.
1107
1108    AARCH64_OPDE_OTHER_ERROR
1109      Error of the highest severity and used for any severe issue that does not
1110      fall into any of the above categories.
1111
1112    The enumerators are only interesting to GAS.  They are declared here (in
1113    libopcodes) because that some errors are detected (and then notified to GAS)
1114    by libopcodes (rather than by GAS solely).
1115
1116    The first three errors are only deteced by GAS while the
1117    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1118    only libopcodes has the information about the valid variants of each
1119    instruction.
1120
1121    The enumerators have an increasing severity.  This is helpful when there are
1122    multiple instruction templates available for a given mnemonic name (e.g.
1123    FMOV); this mechanism will help choose the most suitable template from which
1124    the generated diagnostics can most closely describe the issues, if any.  */
1125
1126 enum aarch64_operand_error_kind
1127 {
1128   AARCH64_OPDE_NIL,
1129   AARCH64_OPDE_RECOVERABLE,
1130   AARCH64_OPDE_SYNTAX_ERROR,
1131   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1132   AARCH64_OPDE_INVALID_VARIANT,
1133   AARCH64_OPDE_UNTIED_OPERAND,
1134   AARCH64_OPDE_OUT_OF_RANGE,
1135   AARCH64_OPDE_UNALIGNED,
1136   AARCH64_OPDE_REG_LIST,
1137   AARCH64_OPDE_OTHER_ERROR
1138 };
1139
1140 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1141 struct aarch64_operand_error
1142 {
1143   enum aarch64_operand_error_kind kind;
1144   int index;
1145   const char *error;
1146   int data[3];  /* Some data for extra information.  */
1147   bfd_boolean non_fatal;
1148 };
1149
1150 /* AArch64 sequence structure used to track instructions with F_SCAN
1151    dependencies for both assembler and disassembler.  */
1152 struct aarch64_instr_sequence
1153 {
1154   /* The instruction that caused this sequence to be opened.  */
1155   aarch64_inst *instr;
1156   /* The number of instructions the above instruction allows to be kept in the
1157      sequence before an automatic close is done.  */
1158   int num_insns;
1159   /* The instructions currently added to the sequence.  */
1160   aarch64_inst **current_insns;
1161   /* The number of instructions already in the sequence.  */
1162   int next_insn;
1163 };
1164
1165 /* Encoding entrypoint.  */
1166
1167 extern int
1168 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1169                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1170                        aarch64_operand_error *, aarch64_instr_sequence *);
1171
1172 extern const aarch64_opcode *
1173 aarch64_replace_opcode (struct aarch64_inst *,
1174                         const aarch64_opcode *);
1175
1176 /* Given the opcode enumerator OP, return the pointer to the corresponding
1177    opcode entry.  */
1178
1179 extern const aarch64_opcode *
1180 aarch64_get_opcode (enum aarch64_op);
1181
1182 /* Generate the string representation of an operand.  */
1183 extern void
1184 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1185                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1186                        char **);
1187
1188 /* Miscellaneous interface.  */
1189
1190 extern int
1191 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1192
1193 extern aarch64_opnd_qualifier_t
1194 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1195                                 const aarch64_opnd_qualifier_t, int);
1196
1197 extern bfd_boolean
1198 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1199
1200 extern int
1201 aarch64_num_of_operands (const aarch64_opcode *);
1202
1203 extern int
1204 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1205
1206 extern int
1207 aarch64_zero_register_p (const aarch64_opnd_info *);
1208
1209 extern enum err_type
1210 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1211                      aarch64_operand_error *);
1212
1213 extern void
1214 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1215
1216 /* Given an operand qualifier, return the expected data element size
1217    of a qualified operand.  */
1218 extern unsigned char
1219 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1220
1221 extern enum aarch64_operand_class
1222 aarch64_get_operand_class (enum aarch64_opnd);
1223
1224 extern const char *
1225 aarch64_get_operand_name (enum aarch64_opnd);
1226
1227 extern const char *
1228 aarch64_get_operand_desc (enum aarch64_opnd);
1229
1230 extern bfd_boolean
1231 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1232
1233 #ifdef DEBUG_AARCH64
1234 extern int debug_dump;
1235
1236 extern void
1237 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1238
1239 #define DEBUG_TRACE(M, ...)                                     \
1240   {                                                             \
1241     if (debug_dump)                                             \
1242       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1243   }
1244
1245 #define DEBUG_TRACE_IF(C, M, ...)                               \
1246   {                                                             \
1247     if (debug_dump && (C))                                      \
1248       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1249   }
1250 #else  /* !DEBUG_AARCH64 */
1251 #define DEBUG_TRACE(M, ...) ;
1252 #define DEBUG_TRACE_IF(C, M, ...) ;
1253 #endif /* DEBUG_AARCH64 */
1254
1255 extern const char *const aarch64_sve_pattern_array[32];
1256 extern const char *const aarch64_sve_prfop_array[16];
1257
1258 #ifdef __cplusplus
1259 }
1260 #endif
1261
1262 #endif /* OPCODE_AARCH64_H */