include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x01000000      /* v8.2 FP16 instructions.  */
  52
  53 /* Architectures are the sum of the base and extensions.  */
  54 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  55                                                  AARCH64_FEATURE_FP  \
  56                                                  | AARCH64_FEATURE_SIMD)
  57 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  58                                                  AARCH64_FEATURE_FP  \
  59                                                  | AARCH64_FEATURE_SIMD \
  60                                                  | AARCH64_FEATURE_V8_1 \
  61                                                  | AARCH64_FEATURE_LSE  \
  62                                                  | AARCH64_FEATURE_PAN  \
  63                                                  | AARCH64_FEATURE_LOR  \
  64                                                  | AARCH64_FEATURE_RDMA)
  65 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  66                                                  AARCH64_FEATURE_V8_2   \
  67                                                  | AARCH64_FEATURE_F16  \
  68                                                  | AARCH64_FEATURE_FP   \
  69                                                  | AARCH64_FEATURE_SIMD \
  70                                                  | AARCH64_FEATURE_LSE  \
  71                                                  | AARCH64_FEATURE_PAN  \
  72                                                  | AARCH64_FEATURE_LOR  \
  73                                                  | AARCH64_FEATURE_RDMA)
  74
  75 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  76 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  77
  78 /* CPU-specific features.  */
  79 typedef unsigned long aarch64_feature_set;
  80
  81 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  82   (((CPU) & (FEAT)) != 0)
  83
  84 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  85   do                                            \
  86     {                                           \
  87       (TARG) = (F1) | (F2);                     \
  88     }                                           \
  89   while (0)
  90
  91 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  92   do                                            \
  93     {                                           \
  94       (TARG) = (F1) &~ (F2);                    \
  95     }                                           \
  96   while (0)
  97
  98 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
  99
 100 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
 101   (((OPC) & (FEAT)) != 0)
 102
 103 enum aarch64_operand_class
 104 {
 105   AARCH64_OPND_CLASS_NIL,
 106   AARCH64_OPND_CLASS_INT_REG,
 107   AARCH64_OPND_CLASS_MODIFIED_REG,
 108   AARCH64_OPND_CLASS_FP_REG,
 109   AARCH64_OPND_CLASS_SIMD_REG,
 110   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 111   AARCH64_OPND_CLASS_SISD_REG,
 112   AARCH64_OPND_CLASS_SIMD_REGLIST,
 113   AARCH64_OPND_CLASS_CP_REG,
 114   AARCH64_OPND_CLASS_ADDRESS,
 115   AARCH64_OPND_CLASS_IMMEDIATE,
 116   AARCH64_OPND_CLASS_SYSTEM,
 117   AARCH64_OPND_CLASS_COND,
 118 };
 119
 120 /* Operand code that helps both parsing and coding.
 121    Keep AARCH64_OPERANDS synced.  */
 122
 123 enum aarch64_opnd
 124 {
 125   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 126
 127   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 128   AARCH64_OPND_Rn,      /* Integer register as source.  */
 129   AARCH64_OPND_Rm,      /* Integer register as source.  */
 130   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 131   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 132   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 133   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 134   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 135
 136   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 137   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 138   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 139   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 140   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 141
 142   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 143   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 144   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 145   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 146   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 147   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 148
 149   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 150   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 151   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 152
 153   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 154   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 155   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 156   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 157   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 158   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 159   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 160   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 161   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 162   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 163   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 164                            structure to all lanes.  */
 165   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 166
 167   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 168   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 169
 170   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 171   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 172   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 173   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 174   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 175   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 176   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 177                            (no encoding).  */
 178   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 179   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 180   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 181   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 182   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 183   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 184   AARCH64_OPND_IMM,     /* Immediate.  */
 185   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 186   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 187   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 188   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 189   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 190   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 191   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 192   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 193                            each condition flag.  */
 194
 195   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 196   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 197   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 198   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 199   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 200
 201   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 202   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 203
 204   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 205   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 206   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 207   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 208   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 209
 210   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 211   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 212   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 213   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 214   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 215                                    negative or unaligned and there is
 216                                    no writeback allowed.  This operand code
 217                                    is only used to support the programmer-
 218                                    friendly feature of using LDR/STR as the
 219                                    the mnemonic name for LDUR/STUR instructions
 220                                    wherever there is no ambiguity.  */
 221   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 222   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 223   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 224
 225   AARCH64_OPND_SYSREG,          /* System register operand.  */
 226   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 227   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 228   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 229   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 230   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 231   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 232   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 233   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 234 };
 235
 236 /* Qualifier constrains an operand.  It either specifies a variant of an
 237    operand type or limits values available to an operand type.
 238
 239    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 240
 241 enum aarch64_opnd_qualifier
 242 {
 243   /* Indicating no further qualification on an operand.  */
 244   AARCH64_OPND_QLF_NIL,
 245
 246   /* Qualifying an operand which is a general purpose (integer) register;
 247      indicating the operand data size or a specific register.  */
 248   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 249   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 250   AARCH64_OPND_QLF_WSP, /* WSP.  */
 251   AARCH64_OPND_QLF_SP,  /* SP.  */
 252
 253   /* Qualifying an operand which is a floating-point register, a SIMD
 254      vector element or a SIMD vector element list; indicating operand data
 255      size or the size of each SIMD vector element in the case of a SIMD
 256      vector element list.
 257      These qualifiers are also used to qualify an address operand to
 258      indicate the size of data element a load/store instruction is
 259      accessing.
 260      They are also used for the immediate shift operand in e.g. SSHR.  Such
 261      a use is only for the ease of operand encoding/decoding and qualifier
 262      sequence matching; such a use should not be applied widely; use the value
 263      constraint qualifiers for immediate operands wherever possible.  */
 264   AARCH64_OPND_QLF_S_B,
 265   AARCH64_OPND_QLF_S_H,
 266   AARCH64_OPND_QLF_S_S,
 267   AARCH64_OPND_QLF_S_D,
 268   AARCH64_OPND_QLF_S_Q,
 269
 270   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 271      register list; indicating register shape.
 272      They are also used for the immediate shift operand in e.g. SSHR.  Such
 273      a use is only for the ease of operand encoding/decoding and qualifier
 274      sequence matching; such a use should not be applied widely; use the value
 275      constraint qualifiers for immediate operands wherever possible.  */
 276   AARCH64_OPND_QLF_V_8B,
 277   AARCH64_OPND_QLF_V_16B,
 278   AARCH64_OPND_QLF_V_4H,
 279   AARCH64_OPND_QLF_V_8H,
 280   AARCH64_OPND_QLF_V_2S,
 281   AARCH64_OPND_QLF_V_4S,
 282   AARCH64_OPND_QLF_V_1D,
 283   AARCH64_OPND_QLF_V_2D,
 284   AARCH64_OPND_QLF_V_1Q,
 285
 286   /* Constraint on value.  */
 287   AARCH64_OPND_QLF_imm_0_7,
 288   AARCH64_OPND_QLF_imm_0_15,
 289   AARCH64_OPND_QLF_imm_0_31,
 290   AARCH64_OPND_QLF_imm_0_63,
 291   AARCH64_OPND_QLF_imm_1_32,
 292   AARCH64_OPND_QLF_imm_1_64,
 293
 294   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 295      or shift-ones.  */
 296   AARCH64_OPND_QLF_LSL,
 297   AARCH64_OPND_QLF_MSL,
 298
 299   /* Special qualifier helping retrieve qualifier information during the
 300      decoding time (currently not in use).  */
 301   AARCH64_OPND_QLF_RETRIEVE,
 302 };
 303 \f
 304 /* Instruction class.  */
 305
 306 enum aarch64_insn_class
 307 {
 308   addsub_carry,
 309   addsub_ext,
 310   addsub_imm,
 311   addsub_shift,
 312   asimdall,
 313   asimddiff,
 314   asimdelem,
 315   asimdext,
 316   asimdimm,
 317   asimdins,
 318   asimdmisc,
 319   asimdperm,
 320   asimdsame,
 321   asimdshf,
 322   asimdtbl,
 323   asisddiff,
 324   asisdelem,
 325   asisdlse,
 326   asisdlsep,
 327   asisdlso,
 328   asisdlsop,
 329   asisdmisc,
 330   asisdone,
 331   asisdpair,
 332   asisdsame,
 333   asisdshf,
 334   bitfield,
 335   branch_imm,
 336   branch_reg,
 337   compbranch,
 338   condbranch,
 339   condcmp_imm,
 340   condcmp_reg,
 341   condsel,
 342   cryptoaes,
 343   cryptosha2,
 344   cryptosha3,
 345   dp_1src,
 346   dp_2src,
 347   dp_3src,
 348   exception,
 349   extract,
 350   float2fix,
 351   float2int,
 352   floatccmp,
 353   floatcmp,
 354   floatdp1,
 355   floatdp2,
 356   floatdp3,
 357   floatimm,
 358   floatsel,
 359   ldst_immpost,
 360   ldst_immpre,
 361   ldst_imm9,    /* immpost or immpre */
 362   ldst_pos,
 363   ldst_regoff,
 364   ldst_unpriv,
 365   ldst_unscaled,
 366   ldstexcl,
 367   ldstnapair_offs,
 368   ldstpair_off,
 369   ldstpair_indexed,
 370   loadlit,
 371   log_imm,
 372   log_shift,
 373   lse_atomic,
 374   movewide,
 375   pcreladdr,
 376   ic_system,
 377   testbranch,
 378 };
 379
 380 /* Opcode enumerators.  */
 381
 382 enum aarch64_op
 383 {
 384   OP_NIL,
 385   OP_STRB_POS,
 386   OP_LDRB_POS,
 387   OP_LDRSB_POS,
 388   OP_STRH_POS,
 389   OP_LDRH_POS,
 390   OP_LDRSH_POS,
 391   OP_STR_POS,
 392   OP_LDR_POS,
 393   OP_STRF_POS,
 394   OP_LDRF_POS,
 395   OP_LDRSW_POS,
 396   OP_PRFM_POS,
 397
 398   OP_STURB,
 399   OP_LDURB,
 400   OP_LDURSB,
 401   OP_STURH,
 402   OP_LDURH,
 403   OP_LDURSH,
 404   OP_STUR,
 405   OP_LDUR,
 406   OP_STURV,
 407   OP_LDURV,
 408   OP_LDURSW,
 409   OP_PRFUM,
 410
 411   OP_LDR_LIT,
 412   OP_LDRV_LIT,
 413   OP_LDRSW_LIT,
 414   OP_PRFM_LIT,
 415
 416   OP_ADD,
 417   OP_B,
 418   OP_BL,
 419
 420   OP_MOVN,
 421   OP_MOVZ,
 422   OP_MOVK,
 423
 424   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 425   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 426   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 427
 428   OP_MOV_V,             /* MOV alias for moving vector register.  */
 429
 430   OP_ASR_IMM,
 431   OP_LSR_IMM,
 432   OP_LSL_IMM,
 433
 434   OP_BIC,
 435
 436   OP_UBFX,
 437   OP_BFXIL,
 438   OP_SBFX,
 439   OP_SBFIZ,
 440   OP_BFI,
 441   OP_UBFIZ,
 442   OP_UXTB,
 443   OP_UXTH,
 444   OP_UXTW,
 445
 446   OP_CINC,
 447   OP_CINV,
 448   OP_CNEG,
 449   OP_CSET,
 450   OP_CSETM,
 451
 452   OP_FCVT,
 453   OP_FCVTN,
 454   OP_FCVTN2,
 455   OP_FCVTL,
 456   OP_FCVTL2,
 457   OP_FCVTXN_S,          /* Scalar version.  */
 458
 459   OP_ROR_IMM,
 460
 461   OP_SXTL,
 462   OP_SXTL2,
 463   OP_UXTL,
 464   OP_UXTL2,
 465
 466   OP_TOTAL_NUM,         /* Pseudo.  */
 467 };
 468
 469 /* Maximum number of operands an instruction can have.  */
 470 #define AARCH64_MAX_OPND_NUM 6
 471 /* Maximum number of qualifier sequences an instruction can have.  */
 472 #define AARCH64_MAX_QLF_SEQ_NUM 10
 473 /* Operand qualifier typedef; optimized for the size.  */
 474 typedef unsigned char aarch64_opnd_qualifier_t;
 475 /* Operand qualifier sequence typedef.  */
 476 typedef aarch64_opnd_qualifier_t        \
 477           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 478
 479 /* FIXME: improve the efficiency.  */
 480 static inline bfd_boolean
 481 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 482 {
 483   int i;
 484   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 485     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 486       return FALSE;
 487   return TRUE;
 488 }
 489
 490 /* This structure holds information for a particular opcode.  */
 491
 492 struct aarch64_opcode
 493 {
 494   /* The name of the mnemonic.  */
 495   const char *name;
 496
 497   /* The opcode itself.  Those bits which will be filled in with
 498      operands are zeroes.  */
 499   aarch64_insn opcode;
 500
 501   /* The opcode mask.  This is used by the disassembler.  This is a
 502      mask containing ones indicating those bits which must match the
 503      opcode field, and zeroes indicating those bits which need not
 504      match (and are presumably filled in by operands).  */
 505   aarch64_insn mask;
 506
 507   /* Instruction class.  */
 508   enum aarch64_insn_class iclass;
 509
 510   /* Enumerator identifier.  */
 511   enum aarch64_op op;
 512
 513   /* Which architecture variant provides this instruction.  */
 514   const aarch64_feature_set *avariant;
 515
 516   /* An array of operand codes.  Each code is an index into the
 517      operand table.  They appear in the order which the operands must
 518      appear in assembly code, and are terminated by a zero.  */
 519   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 520
 521   /* A list of operand qualifier code sequence.  Each operand qualifier
 522      code qualifies the corresponding operand code.  Each operand
 523      qualifier sequence specifies a valid opcode variant and related
 524      constraint on operands.  */
 525   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 526
 527   /* Flags providing information about this instruction */
 528   uint32_t flags;
 529 };
 530
 531 typedef struct aarch64_opcode aarch64_opcode;
 532
 533 /* Table describing all the AArch64 opcodes.  */
 534 extern aarch64_opcode aarch64_opcode_table[];
 535
 536 /* Opcode flags.  */
 537 #define F_ALIAS (1 << 0)
 538 #define F_HAS_ALIAS (1 << 1)
 539 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 540    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 541 #define F_P1 (1 << 2)
 542 #define F_P2 (2 << 2)
 543 #define F_P3 (3 << 2)
 544 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 545 #define F_COND (1 << 4)
 546 /* Instruction has the field of 'sf'.  */
 547 #define F_SF (1 << 5)
 548 /* Instruction has the field of 'size:Q'.  */
 549 #define F_SIZEQ (1 << 6)
 550 /* Floating-point instruction has the field of 'type'.  */
 551 #define F_FPTYPE (1 << 7)
 552 /* AdvSIMD scalar instruction has the field of 'size'.  */
 553 #define F_SSIZE (1 << 8)
 554 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 555 #define F_T (1 << 9)
 556 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 557 #define F_GPRSIZE_IN_Q (1 << 10)
 558 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 559 #define F_LDS_SIZE (1 << 11)
 560 /* Optional operand; assume maximum of 1 operand can be optional.  */
 561 #define F_OPD0_OPT (1 << 12)
 562 #define F_OPD1_OPT (2 << 12)
 563 #define F_OPD2_OPT (3 << 12)
 564 #define F_OPD3_OPT (4 << 12)
 565 #define F_OPD4_OPT (5 << 12)
 566 /* Default value for the optional operand when omitted from the assembly.  */
 567 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 568 /* Instruction that is an alias of another instruction needs to be
 569    encoded/decoded by converting it to/from the real form, followed by
 570    the encoding/decoding according to the rules of the real opcode.
 571    This compares to the direct coding using the alias's information.
 572    N.B. this flag requires F_ALIAS to be used together.  */
 573 #define F_CONV (1 << 20)
 574 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 575    friendly pseudo instruction available only in the assembly code (thus will
 576    not show up in the disassembly).  */
 577 #define F_PSEUDO (1 << 21)
 578 /* Instruction has miscellaneous encoding/decoding rules.  */
 579 #define F_MISC (1 << 22)
 580 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 581 #define F_N (1 << 23)
 582 /* Opcode dependent field.  */
 583 #define F_OD(X) (((X) & 0x7) << 24)
 584 /* Instruction has the field of 'sz'.  */
 585 #define F_LSE_SZ (1 << 27)
 586 /* Next bit is 28.  */
 587
 588 static inline bfd_boolean
 589 alias_opcode_p (const aarch64_opcode *opcode)
 590 {
 591   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 592 }
 593
 594 static inline bfd_boolean
 595 opcode_has_alias (const aarch64_opcode *opcode)
 596 {
 597   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 598 }
 599
 600 /* Priority for disassembling preference.  */
 601 static inline int
 602 opcode_priority (const aarch64_opcode *opcode)
 603 {
 604   return (opcode->flags >> 2) & 0x3;
 605 }
 606
 607 static inline bfd_boolean
 608 pseudo_opcode_p (const aarch64_opcode *opcode)
 609 {
 610   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 611 }
 612
 613 static inline bfd_boolean
 614 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 615 {
 616   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 617     ? TRUE : FALSE;
 618 }
 619
 620 static inline aarch64_insn
 621 get_optional_operand_default_value (const aarch64_opcode *opcode)
 622 {
 623   return (opcode->flags >> 15) & 0x1f;
 624 }
 625
 626 static inline unsigned int
 627 get_opcode_dependent_value (const aarch64_opcode *opcode)
 628 {
 629   return (opcode->flags >> 24) & 0x7;
 630 }
 631
 632 static inline bfd_boolean
 633 opcode_has_special_coder (const aarch64_opcode *opcode)
 634 {
 635   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 636           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 637     : FALSE;
 638 }
 639 \f
 640 struct aarch64_name_value_pair
 641 {
 642   const char *  name;
 643   aarch64_insn  value;
 644 };
 645
 646 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 647 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 648 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 649
 650 typedef struct
 651 {
 652   const char *  name;
 653   aarch64_insn  value;
 654   uint32_t      flags;
 655 } aarch64_sys_reg;
 656
 657 extern const aarch64_sys_reg aarch64_sys_regs [];
 658 extern const aarch64_sys_reg aarch64_pstatefields [];
 659 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 660 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 661                                                 const aarch64_sys_reg *);
 662 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 663                                                     const aarch64_sys_reg *);
 664
 665 typedef struct
 666 {
 667   const char *name;
 668   uint32_t value;
 669   int has_xt;
 670 } aarch64_sys_ins_reg;
 671
 672 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 673 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 674 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 675 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 676
 677 /* Shift/extending operator kinds.
 678    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 679 enum aarch64_modifier_kind
 680 {
 681   AARCH64_MOD_NONE,
 682   AARCH64_MOD_MSL,
 683   AARCH64_MOD_ROR,
 684   AARCH64_MOD_ASR,
 685   AARCH64_MOD_LSR,
 686   AARCH64_MOD_LSL,
 687   AARCH64_MOD_UXTB,
 688   AARCH64_MOD_UXTH,
 689   AARCH64_MOD_UXTW,
 690   AARCH64_MOD_UXTX,
 691   AARCH64_MOD_SXTB,
 692   AARCH64_MOD_SXTH,
 693   AARCH64_MOD_SXTW,
 694   AARCH64_MOD_SXTX,
 695 };
 696
 697 bfd_boolean
 698 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 699
 700 enum aarch64_modifier_kind
 701 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 702 /* Condition.  */
 703
 704 typedef struct
 705 {
 706   /* A list of names with the first one as the disassembly preference;
 707      terminated by NULL if fewer than 3.  */
 708   const char *names[3];
 709   aarch64_insn value;
 710 } aarch64_cond;
 711
 712 extern const aarch64_cond aarch64_conds[16];
 713
 714 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 715 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 716 \f
 717 /* Structure representing an operand.  */
 718
 719 struct aarch64_opnd_info
 720 {
 721   enum aarch64_opnd type;
 722   aarch64_opnd_qualifier_t qualifier;
 723   int idx;
 724
 725   union
 726     {
 727       struct
 728         {
 729           unsigned regno;
 730         } reg;
 731       struct
 732         {
 733           unsigned regno : 5;
 734           unsigned index : 4;
 735         } reglane;
 736       /* e.g. LVn.  */
 737       struct
 738         {
 739           unsigned first_regno : 5;
 740           unsigned num_regs : 3;
 741           /* 1 if it is a list of reg element.  */
 742           unsigned has_index : 1;
 743           /* Lane index; valid only when has_index is 1.  */
 744           unsigned index : 4;
 745         } reglist;
 746       /* e.g. immediate or pc relative address offset.  */
 747       struct
 748         {
 749           int64_t value;
 750           unsigned is_fp : 1;
 751         } imm;
 752       /* e.g. address in STR (register offset).  */
 753       struct
 754         {
 755           unsigned base_regno;
 756           struct
 757             {
 758               union
 759                 {
 760                   int imm;
 761                   unsigned regno;
 762                 };
 763               unsigned is_reg;
 764             } offset;
 765           unsigned pcrel : 1;           /* PC-relative.  */
 766           unsigned writeback : 1;
 767           unsigned preind : 1;          /* Pre-indexed.  */
 768           unsigned postind : 1;         /* Post-indexed.  */
 769         } addr;
 770       const aarch64_cond *cond;
 771       /* The encoding of the system register.  */
 772       aarch64_insn sysreg;
 773       /* The encoding of the PSTATE field.  */
 774       aarch64_insn pstatefield;
 775       const aarch64_sys_ins_reg *sysins_op;
 776       const struct aarch64_name_value_pair *barrier;
 777       const struct aarch64_name_value_pair *prfop;
 778     };
 779
 780   /* Operand shifter; in use when the operand is a register offset address,
 781      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 782   struct
 783     {
 784       enum aarch64_modifier_kind kind;
 785       int amount;
 786       unsigned operator_present: 1;     /* Only valid during encoding.  */
 787       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 788       unsigned amount_present: 1;
 789     } shifter;
 790
 791   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 792                            to be done on it.  In some (but not all) of these
 793                            cases, we need to tell libopcodes to skip the
 794                            constraint checking and the encoding for this
 795                            operand, so that the libopcodes can pick up the
 796                            right opcode before the operand is fixed-up.  This
 797                            flag should only be used during the
 798                            assembling/encoding.  */
 799   unsigned present:1;   /* Whether this operand is present in the assembly
 800                            line; not used during the disassembly.  */
 801 };
 802
 803 typedef struct aarch64_opnd_info aarch64_opnd_info;
 804
 805 /* Structure representing an instruction.
 806
 807    It is used during both the assembling and disassembling.  The assembler
 808    fills an aarch64_inst after a successful parsing and then passes it to the
 809    encoding routine to do the encoding.  During the disassembling, the
 810    disassembler calls the decoding routine to decode a binary instruction; on a
 811    successful return, such a structure will be filled with information of the
 812    instruction; then the disassembler uses the information to print out the
 813    instruction.  */
 814
 815 struct aarch64_inst
 816 {
 817   /* The value of the binary instruction.  */
 818   aarch64_insn value;
 819
 820   /* Corresponding opcode entry.  */
 821   const aarch64_opcode *opcode;
 822
 823   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 824   const aarch64_cond *cond;
 825
 826   /* Operands information.  */
 827   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 828 };
 829
 830 typedef struct aarch64_inst aarch64_inst;
 831 \f
 832 /* Diagnosis related declaration and interface.  */
 833
 834 /* Operand error kind enumerators.
 835
 836    AARCH64_OPDE_RECOVERABLE
 837      Less severe error found during the parsing, very possibly because that
 838      GAS has picked up a wrong instruction template for the parsing.
 839
 840    AARCH64_OPDE_SYNTAX_ERROR
 841      General syntax error; it can be either a user error, or simply because
 842      that GAS is trying a wrong instruction template.
 843
 844    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 845      Definitely a user syntax error.
 846
 847    AARCH64_OPDE_INVALID_VARIANT
 848      No syntax error, but the operands are not a valid combination, e.g.
 849      FMOV D0,S0
 850
 851    AARCH64_OPDE_OUT_OF_RANGE
 852      Error about some immediate value out of a valid range.
 853
 854    AARCH64_OPDE_UNALIGNED
 855      Error about some immediate value not properly aligned (i.e. not being a
 856      multiple times of a certain value).
 857
 858    AARCH64_OPDE_REG_LIST
 859      Error about the register list operand having unexpected number of
 860      registers.
 861
 862    AARCH64_OPDE_OTHER_ERROR
 863      Error of the highest severity and used for any severe issue that does not
 864      fall into any of the above categories.
 865
 866    The enumerators are only interesting to GAS.  They are declared here (in
 867    libopcodes) because that some errors are detected (and then notified to GAS)
 868    by libopcodes (rather than by GAS solely).
 869
 870    The first three errors are only deteced by GAS while the
 871    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 872    only libopcodes has the information about the valid variants of each
 873    instruction.
 874
 875    The enumerators have an increasing severity.  This is helpful when there are
 876    multiple instruction templates available for a given mnemonic name (e.g.
 877    FMOV); this mechanism will help choose the most suitable template from which
 878    the generated diagnostics can most closely describe the issues, if any.  */
 879
 880 enum aarch64_operand_error_kind
 881 {
 882   AARCH64_OPDE_NIL,
 883   AARCH64_OPDE_RECOVERABLE,
 884   AARCH64_OPDE_SYNTAX_ERROR,
 885   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 886   AARCH64_OPDE_INVALID_VARIANT,
 887   AARCH64_OPDE_OUT_OF_RANGE,
 888   AARCH64_OPDE_UNALIGNED,
 889   AARCH64_OPDE_REG_LIST,
 890   AARCH64_OPDE_OTHER_ERROR
 891 };
 892
 893 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 894 struct aarch64_operand_error
 895 {
 896   enum aarch64_operand_error_kind kind;
 897   int index;
 898   const char *error;
 899   int data[3];  /* Some data for extra information.  */
 900 };
 901
 902 typedef struct aarch64_operand_error aarch64_operand_error;
 903
 904 /* Encoding entrypoint.  */
 905
 906 extern int
 907 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 908                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 909                        aarch64_operand_error *);
 910
 911 extern const aarch64_opcode *
 912 aarch64_replace_opcode (struct aarch64_inst *,
 913                         const aarch64_opcode *);
 914
 915 /* Given the opcode enumerator OP, return the pointer to the corresponding
 916    opcode entry.  */
 917
 918 extern const aarch64_opcode *
 919 aarch64_get_opcode (enum aarch64_op);
 920
 921 /* Generate the string representation of an operand.  */
 922 extern void
 923 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 924                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 925
 926 /* Miscellaneous interface.  */
 927
 928 extern int
 929 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 930
 931 extern aarch64_opnd_qualifier_t
 932 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 933                                 const aarch64_opnd_qualifier_t, int);
 934
 935 extern int
 936 aarch64_num_of_operands (const aarch64_opcode *);
 937
 938 extern int
 939 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 940
 941 extern int
 942 aarch64_zero_register_p (const aarch64_opnd_info *);
 943
 944 extern int
 945 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
 946
 947 /* Given an operand qualifier, return the expected data element size
 948    of a qualified operand.  */
 949 extern unsigned char
 950 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 951
 952 extern enum aarch64_operand_class
 953 aarch64_get_operand_class (enum aarch64_opnd);
 954
 955 extern const char *
 956 aarch64_get_operand_name (enum aarch64_opnd);
 957
 958 extern const char *
 959 aarch64_get_operand_desc (enum aarch64_opnd);
 960
 961 #ifdef DEBUG_AARCH64
 962 extern int debug_dump;
 963
 964 extern void
 965 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 966
 967 #define DEBUG_TRACE(M, ...)                                     \
 968   {                                                             \
 969     if (debug_dump)                                             \
 970       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 971   }
 972
 973 #define DEBUG_TRACE_IF(C, M, ...)                               \
 974   {                                                             \
 975     if (debug_dump && (C))                                      \
 976       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 977   }
 978 #else  /* !DEBUG_AARCH64 */
 979 #define DEBUG_TRACE(M, ...) ;
 980 #define DEBUG_TRACE_IF(C, M, ...) ;
 981 #endif /* DEBUG_AARCH64 */
 982
 983 #ifdef __cplusplus
 984 }
 985 #endif
 986
 987 #endif /* OPCODE_AARCH64_H */