include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 /* The offset for pc-relative addressing is currently defined to be 0.  */
  31 #define AARCH64_PCREL_OFFSET            0
  32
  33 typedef uint32_t aarch64_insn;
  34
  35 /* The following bitmasks control CPU features.  */
  36 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  37 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  38 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  39 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  40 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  41 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  42 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  43 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  44 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  45
  46 /* Architectures are the sum of the base and extensions.  */
  47 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  48                                                  AARCH64_FEATURE_FP  \
  49                                                  | AARCH64_FEATURE_SIMD)
  50 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  51                                                  AARCH64_FEATURE_FP  \
  52                                                  | AARCH64_FEATURE_SIMD \
  53                                                  | AARCH64_FEATURE_LSE  \
  54                                                  | AARCH64_FEATURE_PAN  \
  55                                                  | AARCH64_FEATURE_LOR  \
  56                                                  | AARCH64_FEATURE_RDMA)
  57
  58
  59 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  60 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  61
  62 /* CPU-specific features.  */
  63 typedef unsigned long aarch64_feature_set;
  64
  65 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  66   (((CPU) & (FEAT)) != 0)
  67
  68 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  69   do                                            \
  70     {                                           \
  71       (TARG) = (F1) | (F2);                     \
  72     }                                           \
  73   while (0)
  74
  75 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  76   do                                            \
  77     {                                           \
  78       (TARG) = (F1) &~ (F2);                    \
  79     }                                           \
  80   while (0)
  81
  82 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
  83
  84 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
  85   (((OPC) & (FEAT)) != 0)
  86
  87 enum aarch64_operand_class
  88 {
  89   AARCH64_OPND_CLASS_NIL,
  90   AARCH64_OPND_CLASS_INT_REG,
  91   AARCH64_OPND_CLASS_MODIFIED_REG,
  92   AARCH64_OPND_CLASS_FP_REG,
  93   AARCH64_OPND_CLASS_SIMD_REG,
  94   AARCH64_OPND_CLASS_SIMD_ELEMENT,
  95   AARCH64_OPND_CLASS_SISD_REG,
  96   AARCH64_OPND_CLASS_SIMD_REGLIST,
  97   AARCH64_OPND_CLASS_CP_REG,
  98   AARCH64_OPND_CLASS_ADDRESS,
  99   AARCH64_OPND_CLASS_IMMEDIATE,
 100   AARCH64_OPND_CLASS_SYSTEM,
 101   AARCH64_OPND_CLASS_COND,
 102 };
 103
 104 /* Operand code that helps both parsing and coding.
 105    Keep AARCH64_OPERANDS synced.  */
 106
 107 enum aarch64_opnd
 108 {
 109   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 110
 111   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 112   AARCH64_OPND_Rn,      /* Integer register as source.  */
 113   AARCH64_OPND_Rm,      /* Integer register as source.  */
 114   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 115   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 116   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 117   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 118   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 119
 120   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 121   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 122   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 123   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 124   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 125
 126   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 127   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 128   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 129   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 130   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 131   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 132
 133   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 134   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 135   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 136
 137   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 138   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 139   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 140   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 141   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 142   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 143   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 144   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 145   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 146   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 147   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 148                            structure to all lanes.  */
 149   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 150
 151   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 152   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 153
 154   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 155   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 156   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 157   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 158   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 159   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 160   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 161                            (no encoding).  */
 162   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 163   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 164   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 165   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 166   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 167   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 168   AARCH64_OPND_IMM,     /* Immediate.  */
 169   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 170   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 171   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 172   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 173   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 174   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 175   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 176   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 177                            each condition flag.  */
 178
 179   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 180   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 181   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 182   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 183   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 184
 185   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 186   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 187
 188   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 189   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 190   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 191   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 192   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 193
 194   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 195   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 196   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 197   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 198   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 199                                    negative or unaligned and there is
 200                                    no writeback allowed.  This operand code
 201                                    is only used to support the programmer-
 202                                    friendly feature of using LDR/STR as the
 203                                    the mnemonic name for LDUR/STUR instructions
 204                                    wherever there is no ambiguity.  */
 205   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 206   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 207   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 208
 209   AARCH64_OPND_SYSREG,          /* System register operand.  */
 210   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 211   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 212   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 213   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 214   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 215   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 216   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 217   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 218 };
 219
 220 /* Qualifier constrains an operand.  It either specifies a variant of an
 221    operand type or limits values available to an operand type.
 222
 223    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 224
 225 enum aarch64_opnd_qualifier
 226 {
 227   /* Indicating no further qualification on an operand.  */
 228   AARCH64_OPND_QLF_NIL,
 229
 230   /* Qualifying an operand which is a general purpose (integer) register;
 231      indicating the operand data size or a specific register.  */
 232   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 233   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 234   AARCH64_OPND_QLF_WSP, /* WSP.  */
 235   AARCH64_OPND_QLF_SP,  /* SP.  */
 236
 237   /* Qualifying an operand which is a floating-point register, a SIMD
 238      vector element or a SIMD vector element list; indicating operand data
 239      size or the size of each SIMD vector element in the case of a SIMD
 240      vector element list.
 241      These qualifiers are also used to qualify an address operand to
 242      indicate the size of data element a load/store instruction is
 243      accessing.
 244      They are also used for the immediate shift operand in e.g. SSHR.  Such
 245      a use is only for the ease of operand encoding/decoding and qualifier
 246      sequence matching; such a use should not be applied widely; use the value
 247      constraint qualifiers for immediate operands wherever possible.  */
 248   AARCH64_OPND_QLF_S_B,
 249   AARCH64_OPND_QLF_S_H,
 250   AARCH64_OPND_QLF_S_S,
 251   AARCH64_OPND_QLF_S_D,
 252   AARCH64_OPND_QLF_S_Q,
 253
 254   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 255      register list; indicating register shape.
 256      They are also used for the immediate shift operand in e.g. SSHR.  Such
 257      a use is only for the ease of operand encoding/decoding and qualifier
 258      sequence matching; such a use should not be applied widely; use the value
 259      constraint qualifiers for immediate operands wherever possible.  */
 260   AARCH64_OPND_QLF_V_8B,
 261   AARCH64_OPND_QLF_V_16B,
 262   AARCH64_OPND_QLF_V_4H,
 263   AARCH64_OPND_QLF_V_8H,
 264   AARCH64_OPND_QLF_V_2S,
 265   AARCH64_OPND_QLF_V_4S,
 266   AARCH64_OPND_QLF_V_1D,
 267   AARCH64_OPND_QLF_V_2D,
 268   AARCH64_OPND_QLF_V_1Q,
 269
 270   /* Constraint on value.  */
 271   AARCH64_OPND_QLF_imm_0_7,
 272   AARCH64_OPND_QLF_imm_0_15,
 273   AARCH64_OPND_QLF_imm_0_31,
 274   AARCH64_OPND_QLF_imm_0_63,
 275   AARCH64_OPND_QLF_imm_1_32,
 276   AARCH64_OPND_QLF_imm_1_64,
 277
 278   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 279      or shift-ones.  */
 280   AARCH64_OPND_QLF_LSL,
 281   AARCH64_OPND_QLF_MSL,
 282
 283   /* Special qualifier helping retrieve qualifier information during the
 284      decoding time (currently not in use).  */
 285   AARCH64_OPND_QLF_RETRIEVE,
 286 };
 287 \f
 288 /* Instruction class.  */
 289
 290 enum aarch64_insn_class
 291 {
 292   addsub_carry,
 293   addsub_ext,
 294   addsub_imm,
 295   addsub_shift,
 296   asimdall,
 297   asimddiff,
 298   asimdelem,
 299   asimdext,
 300   asimdimm,
 301   asimdins,
 302   asimdmisc,
 303   asimdperm,
 304   asimdsame,
 305   asimdshf,
 306   asimdtbl,
 307   asisddiff,
 308   asisdelem,
 309   asisdlse,
 310   asisdlsep,
 311   asisdlso,
 312   asisdlsop,
 313   asisdmisc,
 314   asisdone,
 315   asisdpair,
 316   asisdsame,
 317   asisdshf,
 318   bitfield,
 319   branch_imm,
 320   branch_reg,
 321   compbranch,
 322   condbranch,
 323   condcmp_imm,
 324   condcmp_reg,
 325   condsel,
 326   cryptoaes,
 327   cryptosha2,
 328   cryptosha3,
 329   dp_1src,
 330   dp_2src,
 331   dp_3src,
 332   exception,
 333   extract,
 334   float2fix,
 335   float2int,
 336   floatccmp,
 337   floatcmp,
 338   floatdp1,
 339   floatdp2,
 340   floatdp3,
 341   floatimm,
 342   floatsel,
 343   ldst_immpost,
 344   ldst_immpre,
 345   ldst_imm9,    /* immpost or immpre */
 346   ldst_pos,
 347   ldst_regoff,
 348   ldst_unpriv,
 349   ldst_unscaled,
 350   ldstexcl,
 351   ldstnapair_offs,
 352   ldstpair_off,
 353   ldstpair_indexed,
 354   loadlit,
 355   log_imm,
 356   log_shift,
 357   lse_atomic,
 358   movewide,
 359   pcreladdr,
 360   ic_system,
 361   testbranch,
 362 };
 363
 364 /* Opcode enumerators.  */
 365
 366 enum aarch64_op
 367 {
 368   OP_NIL,
 369   OP_STRB_POS,
 370   OP_LDRB_POS,
 371   OP_LDRSB_POS,
 372   OP_STRH_POS,
 373   OP_LDRH_POS,
 374   OP_LDRSH_POS,
 375   OP_STR_POS,
 376   OP_LDR_POS,
 377   OP_STRF_POS,
 378   OP_LDRF_POS,
 379   OP_LDRSW_POS,
 380   OP_PRFM_POS,
 381
 382   OP_STURB,
 383   OP_LDURB,
 384   OP_LDURSB,
 385   OP_STURH,
 386   OP_LDURH,
 387   OP_LDURSH,
 388   OP_STUR,
 389   OP_LDUR,
 390   OP_STURV,
 391   OP_LDURV,
 392   OP_LDURSW,
 393   OP_PRFUM,
 394
 395   OP_LDR_LIT,
 396   OP_LDRV_LIT,
 397   OP_LDRSW_LIT,
 398   OP_PRFM_LIT,
 399
 400   OP_ADD,
 401   OP_B,
 402   OP_BL,
 403
 404   OP_MOVN,
 405   OP_MOVZ,
 406   OP_MOVK,
 407
 408   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 409   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 410   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 411
 412   OP_MOV_V,             /* MOV alias for moving vector register.  */
 413
 414   OP_ASR_IMM,
 415   OP_LSR_IMM,
 416   OP_LSL_IMM,
 417
 418   OP_BIC,
 419
 420   OP_UBFX,
 421   OP_BFXIL,
 422   OP_SBFX,
 423   OP_SBFIZ,
 424   OP_BFI,
 425   OP_UBFIZ,
 426   OP_UXTB,
 427   OP_UXTH,
 428   OP_UXTW,
 429
 430   OP_CINC,
 431   OP_CINV,
 432   OP_CNEG,
 433   OP_CSET,
 434   OP_CSETM,
 435
 436   OP_FCVT,
 437   OP_FCVTN,
 438   OP_FCVTN2,
 439   OP_FCVTL,
 440   OP_FCVTL2,
 441   OP_FCVTXN_S,          /* Scalar version.  */
 442
 443   OP_ROR_IMM,
 444
 445   OP_SXTL,
 446   OP_SXTL2,
 447   OP_UXTL,
 448   OP_UXTL2,
 449
 450   OP_TOTAL_NUM,         /* Pseudo.  */
 451 };
 452
 453 /* Maximum number of operands an instruction can have.  */
 454 #define AARCH64_MAX_OPND_NUM 6
 455 /* Maximum number of qualifier sequences an instruction can have.  */
 456 #define AARCH64_MAX_QLF_SEQ_NUM 10
 457 /* Operand qualifier typedef; optimized for the size.  */
 458 typedef unsigned char aarch64_opnd_qualifier_t;
 459 /* Operand qualifier sequence typedef.  */
 460 typedef aarch64_opnd_qualifier_t        \
 461           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 462
 463 /* FIXME: improve the efficiency.  */
 464 static inline bfd_boolean
 465 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 466 {
 467   int i;
 468   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 469     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 470       return FALSE;
 471   return TRUE;
 472 }
 473
 474 /* This structure holds information for a particular opcode.  */
 475
 476 struct aarch64_opcode
 477 {
 478   /* The name of the mnemonic.  */
 479   const char *name;
 480
 481   /* The opcode itself.  Those bits which will be filled in with
 482      operands are zeroes.  */
 483   aarch64_insn opcode;
 484
 485   /* The opcode mask.  This is used by the disassembler.  This is a
 486      mask containing ones indicating those bits which must match the
 487      opcode field, and zeroes indicating those bits which need not
 488      match (and are presumably filled in by operands).  */
 489   aarch64_insn mask;
 490
 491   /* Instruction class.  */
 492   enum aarch64_insn_class iclass;
 493
 494   /* Enumerator identifier.  */
 495   enum aarch64_op op;
 496
 497   /* Which architecture variant provides this instruction.  */
 498   const aarch64_feature_set *avariant;
 499
 500   /* An array of operand codes.  Each code is an index into the
 501      operand table.  They appear in the order which the operands must
 502      appear in assembly code, and are terminated by a zero.  */
 503   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 504
 505   /* A list of operand qualifier code sequence.  Each operand qualifier
 506      code qualifies the corresponding operand code.  Each operand
 507      qualifier sequence specifies a valid opcode variant and related
 508      constraint on operands.  */
 509   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 510
 511   /* Flags providing information about this instruction */
 512   uint32_t flags;
 513 };
 514
 515 typedef struct aarch64_opcode aarch64_opcode;
 516
 517 /* Table describing all the AArch64 opcodes.  */
 518 extern aarch64_opcode aarch64_opcode_table[];
 519
 520 /* Opcode flags.  */
 521 #define F_ALIAS (1 << 0)
 522 #define F_HAS_ALIAS (1 << 1)
 523 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 524    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 525 #define F_P1 (1 << 2)
 526 #define F_P2 (2 << 2)
 527 #define F_P3 (3 << 2)
 528 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 529 #define F_COND (1 << 4)
 530 /* Instruction has the field of 'sf'.  */
 531 #define F_SF (1 << 5)
 532 /* Instruction has the field of 'size:Q'.  */
 533 #define F_SIZEQ (1 << 6)
 534 /* Floating-point instruction has the field of 'type'.  */
 535 #define F_FPTYPE (1 << 7)
 536 /* AdvSIMD scalar instruction has the field of 'size'.  */
 537 #define F_SSIZE (1 << 8)
 538 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 539 #define F_T (1 << 9)
 540 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 541 #define F_GPRSIZE_IN_Q (1 << 10)
 542 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 543 #define F_LDS_SIZE (1 << 11)
 544 /* Optional operand; assume maximum of 1 operand can be optional.  */
 545 #define F_OPD0_OPT (1 << 12)
 546 #define F_OPD1_OPT (2 << 12)
 547 #define F_OPD2_OPT (3 << 12)
 548 #define F_OPD3_OPT (4 << 12)
 549 #define F_OPD4_OPT (5 << 12)
 550 /* Default value for the optional operand when omitted from the assembly.  */
 551 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 552 /* Instruction that is an alias of another instruction needs to be
 553    encoded/decoded by converting it to/from the real form, followed by
 554    the encoding/decoding according to the rules of the real opcode.
 555    This compares to the direct coding using the alias's information.
 556    N.B. this flag requires F_ALIAS to be used together.  */
 557 #define F_CONV (1 << 20)
 558 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 559    friendly pseudo instruction available only in the assembly code (thus will
 560    not show up in the disassembly).  */
 561 #define F_PSEUDO (1 << 21)
 562 /* Instruction has miscellaneous encoding/decoding rules.  */
 563 #define F_MISC (1 << 22)
 564 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 565 #define F_N (1 << 23)
 566 /* Opcode dependent field.  */
 567 #define F_OD(X) (((X) & 0x7) << 24)
 568 /* Instruction has the field of 'sz'.  */
 569 #define F_LSE_SZ (1 << 27)
 570 /* Next bit is 28.  */
 571
 572 static inline bfd_boolean
 573 alias_opcode_p (const aarch64_opcode *opcode)
 574 {
 575   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 576 }
 577
 578 static inline bfd_boolean
 579 opcode_has_alias (const aarch64_opcode *opcode)
 580 {
 581   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 582 }
 583
 584 /* Priority for disassembling preference.  */
 585 static inline int
 586 opcode_priority (const aarch64_opcode *opcode)
 587 {
 588   return (opcode->flags >> 2) & 0x3;
 589 }
 590
 591 static inline bfd_boolean
 592 pseudo_opcode_p (const aarch64_opcode *opcode)
 593 {
 594   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 595 }
 596
 597 static inline bfd_boolean
 598 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 599 {
 600   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 601     ? TRUE : FALSE;
 602 }
 603
 604 static inline aarch64_insn
 605 get_optional_operand_default_value (const aarch64_opcode *opcode)
 606 {
 607   return (opcode->flags >> 15) & 0x1f;
 608 }
 609
 610 static inline unsigned int
 611 get_opcode_dependent_value (const aarch64_opcode *opcode)
 612 {
 613   return (opcode->flags >> 24) & 0x7;
 614 }
 615
 616 static inline bfd_boolean
 617 opcode_has_special_coder (const aarch64_opcode *opcode)
 618 {
 619   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 620           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 621     : FALSE;
 622 }
 623 \f
 624 struct aarch64_name_value_pair
 625 {
 626   const char *  name;
 627   aarch64_insn  value;
 628 };
 629
 630 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 631 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 632 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 633
 634 typedef struct
 635 {
 636   const char *  name;
 637   aarch64_insn  value;
 638   uint32_t      flags;
 639 } aarch64_sys_reg;
 640
 641 extern const aarch64_sys_reg aarch64_sys_regs [];
 642 extern const aarch64_sys_reg aarch64_pstatefields [];
 643 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 644 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 645                                                 const aarch64_sys_reg *);
 646 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 647                                                     const aarch64_sys_reg *);
 648
 649 typedef struct
 650 {
 651   const char *template;
 652   uint32_t value;
 653   int has_xt;
 654 } aarch64_sys_ins_reg;
 655
 656 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 657 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 658 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 659 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 660
 661 /* Shift/extending operator kinds.
 662    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 663 enum aarch64_modifier_kind
 664 {
 665   AARCH64_MOD_NONE,
 666   AARCH64_MOD_MSL,
 667   AARCH64_MOD_ROR,
 668   AARCH64_MOD_ASR,
 669   AARCH64_MOD_LSR,
 670   AARCH64_MOD_LSL,
 671   AARCH64_MOD_UXTB,
 672   AARCH64_MOD_UXTH,
 673   AARCH64_MOD_UXTW,
 674   AARCH64_MOD_UXTX,
 675   AARCH64_MOD_SXTB,
 676   AARCH64_MOD_SXTH,
 677   AARCH64_MOD_SXTW,
 678   AARCH64_MOD_SXTX,
 679 };
 680
 681 bfd_boolean
 682 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 683
 684 enum aarch64_modifier_kind
 685 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 686 /* Condition.  */
 687
 688 typedef struct
 689 {
 690   /* A list of names with the first one as the disassembly preference;
 691      terminated by NULL if fewer than 3.  */
 692   const char *names[3];
 693   aarch64_insn value;
 694 } aarch64_cond;
 695
 696 extern const aarch64_cond aarch64_conds[16];
 697
 698 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 699 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 700 \f
 701 /* Structure representing an operand.  */
 702
 703 struct aarch64_opnd_info
 704 {
 705   enum aarch64_opnd type;
 706   aarch64_opnd_qualifier_t qualifier;
 707   int idx;
 708
 709   union
 710     {
 711       struct
 712         {
 713           unsigned regno;
 714         } reg;
 715       struct
 716         {
 717           unsigned regno : 5;
 718           unsigned index : 4;
 719         } reglane;
 720       /* e.g. LVn.  */
 721       struct
 722         {
 723           unsigned first_regno : 5;
 724           unsigned num_regs : 3;
 725           /* 1 if it is a list of reg element.  */
 726           unsigned has_index : 1;
 727           /* Lane index; valid only when has_index is 1.  */
 728           unsigned index : 4;
 729         } reglist;
 730       /* e.g. immediate or pc relative address offset.  */
 731       struct
 732         {
 733           int64_t value;
 734           unsigned is_fp : 1;
 735         } imm;
 736       /* e.g. address in STR (register offset).  */
 737       struct
 738         {
 739           unsigned base_regno;
 740           struct
 741             {
 742               union
 743                 {
 744                   int imm;
 745                   unsigned regno;
 746                 };
 747               unsigned is_reg;
 748             } offset;
 749           unsigned pcrel : 1;           /* PC-relative.  */
 750           unsigned writeback : 1;
 751           unsigned preind : 1;          /* Pre-indexed.  */
 752           unsigned postind : 1;         /* Post-indexed.  */
 753         } addr;
 754       const aarch64_cond *cond;
 755       /* The encoding of the system register.  */
 756       aarch64_insn sysreg;
 757       /* The encoding of the PSTATE field.  */
 758       aarch64_insn pstatefield;
 759       const aarch64_sys_ins_reg *sysins_op;
 760       const struct aarch64_name_value_pair *barrier;
 761       const struct aarch64_name_value_pair *prfop;
 762     };
 763
 764   /* Operand shifter; in use when the operand is a register offset address,
 765      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 766   struct
 767     {
 768       enum aarch64_modifier_kind kind;
 769       int amount;
 770       unsigned operator_present: 1;     /* Only valid during encoding.  */
 771       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 772       unsigned amount_present: 1;
 773     } shifter;
 774
 775   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 776                            to be done on it.  In some (but not all) of these
 777                            cases, we need to tell libopcodes to skip the
 778                            constraint checking and the encoding for this
 779                            operand, so that the libopcodes can pick up the
 780                            right opcode before the operand is fixed-up.  This
 781                            flag should only be used during the
 782                            assembling/encoding.  */
 783   unsigned present:1;   /* Whether this operand is present in the assembly
 784                            line; not used during the disassembly.  */
 785 };
 786
 787 typedef struct aarch64_opnd_info aarch64_opnd_info;
 788
 789 /* Structure representing an instruction.
 790
 791    It is used during both the assembling and disassembling.  The assembler
 792    fills an aarch64_inst after a successful parsing and then passes it to the
 793    encoding routine to do the encoding.  During the disassembling, the
 794    disassembler calls the decoding routine to decode a binary instruction; on a
 795    successful return, such a structure will be filled with information of the
 796    instruction; then the disassembler uses the information to print out the
 797    instruction.  */
 798
 799 struct aarch64_inst
 800 {
 801   /* The value of the binary instruction.  */
 802   aarch64_insn value;
 803
 804   /* Corresponding opcode entry.  */
 805   const aarch64_opcode *opcode;
 806
 807   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 808   const aarch64_cond *cond;
 809
 810   /* Operands information.  */
 811   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 812 };
 813
 814 typedef struct aarch64_inst aarch64_inst;
 815 \f
 816 /* Diagnosis related declaration and interface.  */
 817
 818 /* Operand error kind enumerators.
 819
 820    AARCH64_OPDE_RECOVERABLE
 821      Less severe error found during the parsing, very possibly because that
 822      GAS has picked up a wrong instruction template for the parsing.
 823
 824    AARCH64_OPDE_SYNTAX_ERROR
 825      General syntax error; it can be either a user error, or simply because
 826      that GAS is trying a wrong instruction template.
 827
 828    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 829      Definitely a user syntax error.
 830
 831    AARCH64_OPDE_INVALID_VARIANT
 832      No syntax error, but the operands are not a valid combination, e.g.
 833      FMOV D0,S0
 834
 835    AARCH64_OPDE_OUT_OF_RANGE
 836      Error about some immediate value out of a valid range.
 837
 838    AARCH64_OPDE_UNALIGNED
 839      Error about some immediate value not properly aligned (i.e. not being a
 840      multiple times of a certain value).
 841
 842    AARCH64_OPDE_REG_LIST
 843      Error about the register list operand having unexpected number of
 844      registers.
 845
 846    AARCH64_OPDE_OTHER_ERROR
 847      Error of the highest severity and used for any severe issue that does not
 848      fall into any of the above categories.
 849
 850    The enumerators are only interesting to GAS.  They are declared here (in
 851    libopcodes) because that some errors are detected (and then notified to GAS)
 852    by libopcodes (rather than by GAS solely).
 853
 854    The first three errors are only deteced by GAS while the
 855    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 856    only libopcodes has the information about the valid variants of each
 857    instruction.
 858
 859    The enumerators have an increasing severity.  This is helpful when there are
 860    multiple instruction templates available for a given mnemonic name (e.g.
 861    FMOV); this mechanism will help choose the most suitable template from which
 862    the generated diagnostics can most closely describe the issues, if any.  */
 863
 864 enum aarch64_operand_error_kind
 865 {
 866   AARCH64_OPDE_NIL,
 867   AARCH64_OPDE_RECOVERABLE,
 868   AARCH64_OPDE_SYNTAX_ERROR,
 869   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 870   AARCH64_OPDE_INVALID_VARIANT,
 871   AARCH64_OPDE_OUT_OF_RANGE,
 872   AARCH64_OPDE_UNALIGNED,
 873   AARCH64_OPDE_REG_LIST,
 874   AARCH64_OPDE_OTHER_ERROR
 875 };
 876
 877 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 878 struct aarch64_operand_error
 879 {
 880   enum aarch64_operand_error_kind kind;
 881   int index;
 882   const char *error;
 883   int data[3];  /* Some data for extra information.  */
 884 };
 885
 886 typedef struct aarch64_operand_error aarch64_operand_error;
 887
 888 /* Encoding entrypoint.  */
 889
 890 extern int
 891 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 892                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 893                        aarch64_operand_error *);
 894
 895 extern const aarch64_opcode *
 896 aarch64_replace_opcode (struct aarch64_inst *,
 897                         const aarch64_opcode *);
 898
 899 /* Given the opcode enumerator OP, return the pointer to the corresponding
 900    opcode entry.  */
 901
 902 extern const aarch64_opcode *
 903 aarch64_get_opcode (enum aarch64_op);
 904
 905 /* Generate the string representation of an operand.  */
 906 extern void
 907 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 908                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 909
 910 /* Miscellaneous interface.  */
 911
 912 extern int
 913 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 914
 915 extern aarch64_opnd_qualifier_t
 916 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 917                                 const aarch64_opnd_qualifier_t, int);
 918
 919 extern int
 920 aarch64_num_of_operands (const aarch64_opcode *);
 921
 922 extern int
 923 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 924
 925 extern
 926 int aarch64_zero_register_p (const aarch64_opnd_info *);
 927
 928 /* Given an operand qualifier, return the expected data element size
 929    of a qualified operand.  */
 930 extern unsigned char
 931 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 932
 933 extern enum aarch64_operand_class
 934 aarch64_get_operand_class (enum aarch64_opnd);
 935
 936 extern const char *
 937 aarch64_get_operand_name (enum aarch64_opnd);
 938
 939 extern const char *
 940 aarch64_get_operand_desc (enum aarch64_opnd);
 941
 942 #ifdef DEBUG_AARCH64
 943 extern int debug_dump;
 944
 945 extern void
 946 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 947
 948 #define DEBUG_TRACE(M, ...)                                     \
 949   {                                                             \
 950     if (debug_dump)                                             \
 951       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 952   }
 953
 954 #define DEBUG_TRACE_IF(C, M, ...)                               \
 955   {                                                             \
 956     if (debug_dump && (C))                                      \
 957       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 958   }
 959 #else  /* !DEBUG_AARCH64 */
 960 #define DEBUG_TRACE(M, ...) ;
 961 #define DEBUG_TRACE_IF(C, M, ...) ;
 962 #endif /* DEBUG_AARCH64 */
 963
 964 #endif /* OPCODE_AARCH64_H */