include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2017 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  43 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  44 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  45 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  46 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  47 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  48 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  49 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  50 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  51 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  52 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  53 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  54 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  55 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  56 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  57 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  58 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  59 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  60 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  61
  62 /* Architectures are the sum of the base and extensions.  */
  63 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  64                                                  AARCH64_FEATURE_FP  \
  65                                                  | AARCH64_FEATURE_SIMD)
  66 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  67                                                  AARCH64_FEATURE_CRC    \
  68                                                  | AARCH64_FEATURE_V8_1 \
  69                                                  | AARCH64_FEATURE_LSE  \
  70                                                  | AARCH64_FEATURE_PAN  \
  71                                                  | AARCH64_FEATURE_LOR  \
  72                                                  | AARCH64_FEATURE_RDMA)
  73 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  74                                                  AARCH64_FEATURE_V8_2   \
  75                                                  | AARCH64_FEATURE_RAS)
  76 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  77                                                  AARCH64_FEATURE_V8_3   \
  78                                                  | AARCH64_FEATURE_RCPC \
  79                                                  | AARCH64_FEATURE_COMPNUM)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  88   ((~(CPU) & (FEAT)) == 0)
  89
  90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  91   (((CPU) & (FEAT)) != 0)
  92
  93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  94   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  95
  96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) | (F2);                     \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 104   do                                            \
 105     {                                           \
 106       (TARG) = (F1) &~ (F2);                    \
 107     }                                           \
 108   while (0)
 109
 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 111
 112 enum aarch64_operand_class
 113 {
 114   AARCH64_OPND_CLASS_NIL,
 115   AARCH64_OPND_CLASS_INT_REG,
 116   AARCH64_OPND_CLASS_MODIFIED_REG,
 117   AARCH64_OPND_CLASS_FP_REG,
 118   AARCH64_OPND_CLASS_SIMD_REG,
 119   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 120   AARCH64_OPND_CLASS_SISD_REG,
 121   AARCH64_OPND_CLASS_SIMD_REGLIST,
 122   AARCH64_OPND_CLASS_SVE_REG,
 123   AARCH64_OPND_CLASS_PRED_REG,
 124   AARCH64_OPND_CLASS_ADDRESS,
 125   AARCH64_OPND_CLASS_IMMEDIATE,
 126   AARCH64_OPND_CLASS_SYSTEM,
 127   AARCH64_OPND_CLASS_COND,
 128 };
 129
 130 /* Operand code that helps both parsing and coding.
 131    Keep AARCH64_OPERANDS synced.  */
 132
 133 enum aarch64_opnd
 134 {
 135   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 136
 137   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 138   AARCH64_OPND_Rn,      /* Integer register as source.  */
 139   AARCH64_OPND_Rm,      /* Integer register as source.  */
 140   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 141   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 142   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 143   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 144   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 145
 146   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 147   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 148   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 149   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 150   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 151   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 152
 153   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 154   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 155   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 156   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 157   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 158   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 159
 160   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 161   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 162   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 163
 164   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 165   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 166   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 167   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 169   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 170   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 171   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 172   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 173   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 174   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 175                            structure to all lanes.  */
 176   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 177
 178   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 179   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 180
 181   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 182   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 183   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 184   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 185   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 186   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 187   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 188                            (no encoding).  */
 189   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 190   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 191   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 192   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 193   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 194   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 195   AARCH64_OPND_IMM,     /* Immediate.  */
 196   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 197   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 198   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 199   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 200   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 201   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 202   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 203   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 204   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 205                            each condition flag.  */
 206
 207   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 208   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 209   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 210   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 211   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 212   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 213   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 214   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 215
 216   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 217   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 218
 219   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 220   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 221   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 222   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 223   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 224
 225   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 226   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 227   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 228   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 229   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 230                                    negative or unaligned and there is
 231                                    no writeback allowed.  This operand code
 232                                    is only used to support the programmer-
 233                                    friendly feature of using LDR/STR as the
 234                                    the mnemonic name for LDUR/STUR instructions
 235                                    wherever there is no ambiguity.  */
 236   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 237   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 238   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 239   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 240
 241   AARCH64_OPND_SYSREG,          /* System register operand.  */
 242   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 243   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 244   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 245   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 246   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 247   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 248   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 249   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 250   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 251
 252   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 253   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 254   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 255   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 256   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 257   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 258   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 259   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 260   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 261   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 262   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 263   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 264   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 265   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 266   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 267   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 268   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 269   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 270   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 271   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 272   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 273   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 274   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 275   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 276                                        Bit 14 controls S/U choice.  */
 277   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 278                                        Bit 22 controls S/U choice.  */
 279   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 280                                        Bit 14 controls S/U choice.  */
 281   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 282                                        Bit 22 controls S/U choice.  */
 283   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 284                                        Bit 14 controls S/U choice.  */
 285   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 286                                        Bit 22 controls S/U choice.  */
 287   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 288                                        Bit 14 controls S/U choice.  */
 289   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 290                                        Bit 22 controls S/U choice.  */
 291   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 292   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 293   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 294   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 295   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 296   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 297   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 298   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 299   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 300   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 301   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 302   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 303   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 304   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 305   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 306   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 307   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 308   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 309   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 310   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 311   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 312   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 313   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 314   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 315   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 316   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 317   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 318   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 319   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 320   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 321   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 322   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 323   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 324   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 325   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 326   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 327   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 328   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 329   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 330   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 331   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 332   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 333   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 334   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 335   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 336   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 337   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 338   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 339   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 340   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 341   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 342   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 343   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 344   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 345   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 346   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 347   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 348   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 349   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 350   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 351 };
 352
 353 /* Qualifier constrains an operand.  It either specifies a variant of an
 354    operand type or limits values available to an operand type.
 355
 356    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 357
 358 enum aarch64_opnd_qualifier
 359 {
 360   /* Indicating no further qualification on an operand.  */
 361   AARCH64_OPND_QLF_NIL,
 362
 363   /* Qualifying an operand which is a general purpose (integer) register;
 364      indicating the operand data size or a specific register.  */
 365   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 366   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 367   AARCH64_OPND_QLF_WSP, /* WSP.  */
 368   AARCH64_OPND_QLF_SP,  /* SP.  */
 369
 370   /* Qualifying an operand which is a floating-point register, a SIMD
 371      vector element or a SIMD vector element list; indicating operand data
 372      size or the size of each SIMD vector element in the case of a SIMD
 373      vector element list.
 374      These qualifiers are also used to qualify an address operand to
 375      indicate the size of data element a load/store instruction is
 376      accessing.
 377      They are also used for the immediate shift operand in e.g. SSHR.  Such
 378      a use is only for the ease of operand encoding/decoding and qualifier
 379      sequence matching; such a use should not be applied widely; use the value
 380      constraint qualifiers for immediate operands wherever possible.  */
 381   AARCH64_OPND_QLF_S_B,
 382   AARCH64_OPND_QLF_S_H,
 383   AARCH64_OPND_QLF_S_S,
 384   AARCH64_OPND_QLF_S_D,
 385   AARCH64_OPND_QLF_S_Q,
 386
 387   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 388      register list; indicating register shape.
 389      They are also used for the immediate shift operand in e.g. SSHR.  Such
 390      a use is only for the ease of operand encoding/decoding and qualifier
 391      sequence matching; such a use should not be applied widely; use the value
 392      constraint qualifiers for immediate operands wherever possible.  */
 393   AARCH64_OPND_QLF_V_8B,
 394   AARCH64_OPND_QLF_V_16B,
 395   AARCH64_OPND_QLF_V_2H,
 396   AARCH64_OPND_QLF_V_4H,
 397   AARCH64_OPND_QLF_V_8H,
 398   AARCH64_OPND_QLF_V_2S,
 399   AARCH64_OPND_QLF_V_4S,
 400   AARCH64_OPND_QLF_V_1D,
 401   AARCH64_OPND_QLF_V_2D,
 402   AARCH64_OPND_QLF_V_1Q,
 403
 404   AARCH64_OPND_QLF_P_Z,
 405   AARCH64_OPND_QLF_P_M,
 406
 407   /* Constraint on value.  */
 408   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 409   AARCH64_OPND_QLF_imm_0_7,
 410   AARCH64_OPND_QLF_imm_0_15,
 411   AARCH64_OPND_QLF_imm_0_31,
 412   AARCH64_OPND_QLF_imm_0_63,
 413   AARCH64_OPND_QLF_imm_1_32,
 414   AARCH64_OPND_QLF_imm_1_64,
 415
 416   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 417      or shift-ones.  */
 418   AARCH64_OPND_QLF_LSL,
 419   AARCH64_OPND_QLF_MSL,
 420
 421   /* Special qualifier helping retrieve qualifier information during the
 422      decoding time (currently not in use).  */
 423   AARCH64_OPND_QLF_RETRIEVE,
 424 };
 425 \f
 426 /* Instruction class.  */
 427
 428 enum aarch64_insn_class
 429 {
 430   addsub_carry,
 431   addsub_ext,
 432   addsub_imm,
 433   addsub_shift,
 434   asimdall,
 435   asimddiff,
 436   asimdelem,
 437   asimdext,
 438   asimdimm,
 439   asimdins,
 440   asimdmisc,
 441   asimdperm,
 442   asimdsame,
 443   asimdshf,
 444   asimdtbl,
 445   asisddiff,
 446   asisdelem,
 447   asisdlse,
 448   asisdlsep,
 449   asisdlso,
 450   asisdlsop,
 451   asisdmisc,
 452   asisdone,
 453   asisdpair,
 454   asisdsame,
 455   asisdshf,
 456   bitfield,
 457   branch_imm,
 458   branch_reg,
 459   compbranch,
 460   condbranch,
 461   condcmp_imm,
 462   condcmp_reg,
 463   condsel,
 464   cryptoaes,
 465   cryptosha2,
 466   cryptosha3,
 467   dp_1src,
 468   dp_2src,
 469   dp_3src,
 470   exception,
 471   extract,
 472   float2fix,
 473   float2int,
 474   floatccmp,
 475   floatcmp,
 476   floatdp1,
 477   floatdp2,
 478   floatdp3,
 479   floatimm,
 480   floatsel,
 481   ldst_immpost,
 482   ldst_immpre,
 483   ldst_imm9,    /* immpost or immpre */
 484   ldst_imm10,   /* LDRAA/LDRAB */
 485   ldst_pos,
 486   ldst_regoff,
 487   ldst_unpriv,
 488   ldst_unscaled,
 489   ldstexcl,
 490   ldstnapair_offs,
 491   ldstpair_off,
 492   ldstpair_indexed,
 493   loadlit,
 494   log_imm,
 495   log_shift,
 496   lse_atomic,
 497   movewide,
 498   pcreladdr,
 499   ic_system,
 500   sve_cpy,
 501   sve_index,
 502   sve_limm,
 503   sve_misc,
 504   sve_movprfx,
 505   sve_pred_zm,
 506   sve_shift_pred,
 507   sve_shift_unpred,
 508   sve_size_bhs,
 509   sve_size_bhsd,
 510   sve_size_hsd,
 511   sve_size_sd,
 512   testbranch,
 513   dotproduct,
 514 };
 515
 516 /* Opcode enumerators.  */
 517
 518 enum aarch64_op
 519 {
 520   OP_NIL,
 521   OP_STRB_POS,
 522   OP_LDRB_POS,
 523   OP_LDRSB_POS,
 524   OP_STRH_POS,
 525   OP_LDRH_POS,
 526   OP_LDRSH_POS,
 527   OP_STR_POS,
 528   OP_LDR_POS,
 529   OP_STRF_POS,
 530   OP_LDRF_POS,
 531   OP_LDRSW_POS,
 532   OP_PRFM_POS,
 533
 534   OP_STURB,
 535   OP_LDURB,
 536   OP_LDURSB,
 537   OP_STURH,
 538   OP_LDURH,
 539   OP_LDURSH,
 540   OP_STUR,
 541   OP_LDUR,
 542   OP_STURV,
 543   OP_LDURV,
 544   OP_LDURSW,
 545   OP_PRFUM,
 546
 547   OP_LDR_LIT,
 548   OP_LDRV_LIT,
 549   OP_LDRSW_LIT,
 550   OP_PRFM_LIT,
 551
 552   OP_ADD,
 553   OP_B,
 554   OP_BL,
 555
 556   OP_MOVN,
 557   OP_MOVZ,
 558   OP_MOVK,
 559
 560   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 561   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 562   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 563
 564   OP_MOV_V,             /* MOV alias for moving vector register.  */
 565
 566   OP_ASR_IMM,
 567   OP_LSR_IMM,
 568   OP_LSL_IMM,
 569
 570   OP_BIC,
 571
 572   OP_UBFX,
 573   OP_BFXIL,
 574   OP_SBFX,
 575   OP_SBFIZ,
 576   OP_BFI,
 577   OP_BFC,               /* ARMv8.2.  */
 578   OP_UBFIZ,
 579   OP_UXTB,
 580   OP_UXTH,
 581   OP_UXTW,
 582
 583   OP_CINC,
 584   OP_CINV,
 585   OP_CNEG,
 586   OP_CSET,
 587   OP_CSETM,
 588
 589   OP_FCVT,
 590   OP_FCVTN,
 591   OP_FCVTN2,
 592   OP_FCVTL,
 593   OP_FCVTL2,
 594   OP_FCVTXN_S,          /* Scalar version.  */
 595
 596   OP_ROR_IMM,
 597
 598   OP_SXTL,
 599   OP_SXTL2,
 600   OP_UXTL,
 601   OP_UXTL2,
 602
 603   OP_MOV_P_P,
 604   OP_MOV_Z_P_Z,
 605   OP_MOV_Z_V,
 606   OP_MOV_Z_Z,
 607   OP_MOV_Z_Zi,
 608   OP_MOVM_P_P_P,
 609   OP_MOVS_P_P,
 610   OP_MOVZS_P_P_P,
 611   OP_MOVZ_P_P_P,
 612   OP_NOTS_P_P_P_Z,
 613   OP_NOT_P_P_P_Z,
 614
 615   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 616
 617   OP_TOTAL_NUM,         /* Pseudo.  */
 618 };
 619
 620 /* Maximum number of operands an instruction can have.  */
 621 #define AARCH64_MAX_OPND_NUM 6
 622 /* Maximum number of qualifier sequences an instruction can have.  */
 623 #define AARCH64_MAX_QLF_SEQ_NUM 10
 624 /* Operand qualifier typedef; optimized for the size.  */
 625 typedef unsigned char aarch64_opnd_qualifier_t;
 626 /* Operand qualifier sequence typedef.  */
 627 typedef aarch64_opnd_qualifier_t        \
 628           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 629
 630 /* FIXME: improve the efficiency.  */
 631 static inline bfd_boolean
 632 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 633 {
 634   int i;
 635   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 636     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 637       return FALSE;
 638   return TRUE;
 639 }
 640
 641 /* This structure holds information for a particular opcode.  */
 642
 643 struct aarch64_opcode
 644 {
 645   /* The name of the mnemonic.  */
 646   const char *name;
 647
 648   /* The opcode itself.  Those bits which will be filled in with
 649      operands are zeroes.  */
 650   aarch64_insn opcode;
 651
 652   /* The opcode mask.  This is used by the disassembler.  This is a
 653      mask containing ones indicating those bits which must match the
 654      opcode field, and zeroes indicating those bits which need not
 655      match (and are presumably filled in by operands).  */
 656   aarch64_insn mask;
 657
 658   /* Instruction class.  */
 659   enum aarch64_insn_class iclass;
 660
 661   /* Enumerator identifier.  */
 662   enum aarch64_op op;
 663
 664   /* Which architecture variant provides this instruction.  */
 665   const aarch64_feature_set *avariant;
 666
 667   /* An array of operand codes.  Each code is an index into the
 668      operand table.  They appear in the order which the operands must
 669      appear in assembly code, and are terminated by a zero.  */
 670   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 671
 672   /* A list of operand qualifier code sequence.  Each operand qualifier
 673      code qualifies the corresponding operand code.  Each operand
 674      qualifier sequence specifies a valid opcode variant and related
 675      constraint on operands.  */
 676   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 677
 678   /* Flags providing information about this instruction */
 679   uint32_t flags;
 680
 681   /* If nonzero, this operand and operand 0 are both registers and
 682      are required to have the same register number.  */
 683   unsigned char tied_operand;
 684
 685   /* If non-NULL, a function to verify that a given instruction is valid.  */
 686   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 687 };
 688
 689 typedef struct aarch64_opcode aarch64_opcode;
 690
 691 /* Table describing all the AArch64 opcodes.  */
 692 extern aarch64_opcode aarch64_opcode_table[];
 693
 694 /* Opcode flags.  */
 695 #define F_ALIAS (1 << 0)
 696 #define F_HAS_ALIAS (1 << 1)
 697 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 698    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 699 #define F_P1 (1 << 2)
 700 #define F_P2 (2 << 2)
 701 #define F_P3 (3 << 2)
 702 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 703 #define F_COND (1 << 4)
 704 /* Instruction has the field of 'sf'.  */
 705 #define F_SF (1 << 5)
 706 /* Instruction has the field of 'size:Q'.  */
 707 #define F_SIZEQ (1 << 6)
 708 /* Floating-point instruction has the field of 'type'.  */
 709 #define F_FPTYPE (1 << 7)
 710 /* AdvSIMD scalar instruction has the field of 'size'.  */
 711 #define F_SSIZE (1 << 8)
 712 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 713 #define F_T (1 << 9)
 714 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 715 #define F_GPRSIZE_IN_Q (1 << 10)
 716 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 717 #define F_LDS_SIZE (1 << 11)
 718 /* Optional operand; assume maximum of 1 operand can be optional.  */
 719 #define F_OPD0_OPT (1 << 12)
 720 #define F_OPD1_OPT (2 << 12)
 721 #define F_OPD2_OPT (3 << 12)
 722 #define F_OPD3_OPT (4 << 12)
 723 #define F_OPD4_OPT (5 << 12)
 724 /* Default value for the optional operand when omitted from the assembly.  */
 725 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 726 /* Instruction that is an alias of another instruction needs to be
 727    encoded/decoded by converting it to/from the real form, followed by
 728    the encoding/decoding according to the rules of the real opcode.
 729    This compares to the direct coding using the alias's information.
 730    N.B. this flag requires F_ALIAS to be used together.  */
 731 #define F_CONV (1 << 20)
 732 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 733    friendly pseudo instruction available only in the assembly code (thus will
 734    not show up in the disassembly).  */
 735 #define F_PSEUDO (1 << 21)
 736 /* Instruction has miscellaneous encoding/decoding rules.  */
 737 #define F_MISC (1 << 22)
 738 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 739 #define F_N (1 << 23)
 740 /* Opcode dependent field.  */
 741 #define F_OD(X) (((X) & 0x7) << 24)
 742 /* Instruction has the field of 'sz'.  */
 743 #define F_LSE_SZ (1 << 27)
 744 /* Require an exact qualifier match, even for NIL qualifiers.  */
 745 #define F_STRICT (1ULL << 28)
 746 /* Next bit is 29.  */
 747
 748 static inline bfd_boolean
 749 alias_opcode_p (const aarch64_opcode *opcode)
 750 {
 751   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 752 }
 753
 754 static inline bfd_boolean
 755 opcode_has_alias (const aarch64_opcode *opcode)
 756 {
 757   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 758 }
 759
 760 /* Priority for disassembling preference.  */
 761 static inline int
 762 opcode_priority (const aarch64_opcode *opcode)
 763 {
 764   return (opcode->flags >> 2) & 0x3;
 765 }
 766
 767 static inline bfd_boolean
 768 pseudo_opcode_p (const aarch64_opcode *opcode)
 769 {
 770   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 771 }
 772
 773 static inline bfd_boolean
 774 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 775 {
 776   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 777     ? TRUE : FALSE;
 778 }
 779
 780 static inline aarch64_insn
 781 get_optional_operand_default_value (const aarch64_opcode *opcode)
 782 {
 783   return (opcode->flags >> 15) & 0x1f;
 784 }
 785
 786 static inline unsigned int
 787 get_opcode_dependent_value (const aarch64_opcode *opcode)
 788 {
 789   return (opcode->flags >> 24) & 0x7;
 790 }
 791
 792 static inline bfd_boolean
 793 opcode_has_special_coder (const aarch64_opcode *opcode)
 794 {
 795   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 796           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 797     : FALSE;
 798 }
 799 \f
 800 struct aarch64_name_value_pair
 801 {
 802   const char *  name;
 803   aarch64_insn  value;
 804 };
 805
 806 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 807 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 808 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 809 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 810
 811 typedef struct
 812 {
 813   const char *  name;
 814   aarch64_insn  value;
 815   uint32_t      flags;
 816 } aarch64_sys_reg;
 817
 818 extern const aarch64_sys_reg aarch64_sys_regs [];
 819 extern const aarch64_sys_reg aarch64_pstatefields [];
 820 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 821 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 822                                                 const aarch64_sys_reg *);
 823 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 824                                                     const aarch64_sys_reg *);
 825
 826 typedef struct
 827 {
 828   const char *name;
 829   uint32_t value;
 830   uint32_t flags ;
 831 } aarch64_sys_ins_reg;
 832
 833 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 834 extern bfd_boolean
 835 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 836                                  const aarch64_sys_ins_reg *);
 837
 838 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 839 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 840 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 841 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 842
 843 /* Shift/extending operator kinds.
 844    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 845 enum aarch64_modifier_kind
 846 {
 847   AARCH64_MOD_NONE,
 848   AARCH64_MOD_MSL,
 849   AARCH64_MOD_ROR,
 850   AARCH64_MOD_ASR,
 851   AARCH64_MOD_LSR,
 852   AARCH64_MOD_LSL,
 853   AARCH64_MOD_UXTB,
 854   AARCH64_MOD_UXTH,
 855   AARCH64_MOD_UXTW,
 856   AARCH64_MOD_UXTX,
 857   AARCH64_MOD_SXTB,
 858   AARCH64_MOD_SXTH,
 859   AARCH64_MOD_SXTW,
 860   AARCH64_MOD_SXTX,
 861   AARCH64_MOD_MUL,
 862   AARCH64_MOD_MUL_VL,
 863 };
 864
 865 bfd_boolean
 866 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 867
 868 enum aarch64_modifier_kind
 869 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 870 /* Condition.  */
 871
 872 typedef struct
 873 {
 874   /* A list of names with the first one as the disassembly preference;
 875      terminated by NULL if fewer than 3.  */
 876   const char *names[4];
 877   aarch64_insn value;
 878 } aarch64_cond;
 879
 880 extern const aarch64_cond aarch64_conds[16];
 881
 882 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 883 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 884 \f
 885 /* Structure representing an operand.  */
 886
 887 struct aarch64_opnd_info
 888 {
 889   enum aarch64_opnd type;
 890   aarch64_opnd_qualifier_t qualifier;
 891   int idx;
 892
 893   union
 894     {
 895       struct
 896         {
 897           unsigned regno;
 898         } reg;
 899       struct
 900         {
 901           unsigned int regno;
 902           int64_t index;
 903         } reglane;
 904       /* e.g. LVn.  */
 905       struct
 906         {
 907           unsigned first_regno : 5;
 908           unsigned num_regs : 3;
 909           /* 1 if it is a list of reg element.  */
 910           unsigned has_index : 1;
 911           /* Lane index; valid only when has_index is 1.  */
 912           int64_t index;
 913         } reglist;
 914       /* e.g. immediate or pc relative address offset.  */
 915       struct
 916         {
 917           int64_t value;
 918           unsigned is_fp : 1;
 919         } imm;
 920       /* e.g. address in STR (register offset).  */
 921       struct
 922         {
 923           unsigned base_regno;
 924           struct
 925             {
 926               union
 927                 {
 928                   int imm;
 929                   unsigned regno;
 930                 };
 931               unsigned is_reg;
 932             } offset;
 933           unsigned pcrel : 1;           /* PC-relative.  */
 934           unsigned writeback : 1;
 935           unsigned preind : 1;          /* Pre-indexed.  */
 936           unsigned postind : 1;         /* Post-indexed.  */
 937         } addr;
 938       const aarch64_cond *cond;
 939       /* The encoding of the system register.  */
 940       aarch64_insn sysreg;
 941       /* The encoding of the PSTATE field.  */
 942       aarch64_insn pstatefield;
 943       const aarch64_sys_ins_reg *sysins_op;
 944       const struct aarch64_name_value_pair *barrier;
 945       const struct aarch64_name_value_pair *hint_option;
 946       const struct aarch64_name_value_pair *prfop;
 947     };
 948
 949   /* Operand shifter; in use when the operand is a register offset address,
 950      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 951   struct
 952     {
 953       enum aarch64_modifier_kind kind;
 954       unsigned operator_present: 1;     /* Only valid during encoding.  */
 955       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 956       unsigned amount_present: 1;
 957       int64_t amount;
 958     } shifter;
 959
 960   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 961                            to be done on it.  In some (but not all) of these
 962                            cases, we need to tell libopcodes to skip the
 963                            constraint checking and the encoding for this
 964                            operand, so that the libopcodes can pick up the
 965                            right opcode before the operand is fixed-up.  This
 966                            flag should only be used during the
 967                            assembling/encoding.  */
 968   unsigned present:1;   /* Whether this operand is present in the assembly
 969                            line; not used during the disassembly.  */
 970 };
 971
 972 typedef struct aarch64_opnd_info aarch64_opnd_info;
 973
 974 /* Structure representing an instruction.
 975
 976    It is used during both the assembling and disassembling.  The assembler
 977    fills an aarch64_inst after a successful parsing and then passes it to the
 978    encoding routine to do the encoding.  During the disassembling, the
 979    disassembler calls the decoding routine to decode a binary instruction; on a
 980    successful return, such a structure will be filled with information of the
 981    instruction; then the disassembler uses the information to print out the
 982    instruction.  */
 983
 984 struct aarch64_inst
 985 {
 986   /* The value of the binary instruction.  */
 987   aarch64_insn value;
 988
 989   /* Corresponding opcode entry.  */
 990   const aarch64_opcode *opcode;
 991
 992   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 993   const aarch64_cond *cond;
 994
 995   /* Operands information.  */
 996   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 997 };
 998
 999 typedef struct aarch64_inst aarch64_inst;
1000 \f
1001 /* Diagnosis related declaration and interface.  */
1002
1003 /* Operand error kind enumerators.
1004
1005    AARCH64_OPDE_RECOVERABLE
1006      Less severe error found during the parsing, very possibly because that
1007      GAS has picked up a wrong instruction template for the parsing.
1008
1009    AARCH64_OPDE_SYNTAX_ERROR
1010      General syntax error; it can be either a user error, or simply because
1011      that GAS is trying a wrong instruction template.
1012
1013    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1014      Definitely a user syntax error.
1015
1016    AARCH64_OPDE_INVALID_VARIANT
1017      No syntax error, but the operands are not a valid combination, e.g.
1018      FMOV D0,S0
1019
1020    AARCH64_OPDE_UNTIED_OPERAND
1021      The asm failed to use the same register for a destination operand
1022      and a tied source operand.
1023
1024    AARCH64_OPDE_OUT_OF_RANGE
1025      Error about some immediate value out of a valid range.
1026
1027    AARCH64_OPDE_UNALIGNED
1028      Error about some immediate value not properly aligned (i.e. not being a
1029      multiple times of a certain value).
1030
1031    AARCH64_OPDE_REG_LIST
1032      Error about the register list operand having unexpected number of
1033      registers.
1034
1035    AARCH64_OPDE_OTHER_ERROR
1036      Error of the highest severity and used for any severe issue that does not
1037      fall into any of the above categories.
1038
1039    The enumerators are only interesting to GAS.  They are declared here (in
1040    libopcodes) because that some errors are detected (and then notified to GAS)
1041    by libopcodes (rather than by GAS solely).
1042
1043    The first three errors are only deteced by GAS while the
1044    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1045    only libopcodes has the information about the valid variants of each
1046    instruction.
1047
1048    The enumerators have an increasing severity.  This is helpful when there are
1049    multiple instruction templates available for a given mnemonic name (e.g.
1050    FMOV); this mechanism will help choose the most suitable template from which
1051    the generated diagnostics can most closely describe the issues, if any.  */
1052
1053 enum aarch64_operand_error_kind
1054 {
1055   AARCH64_OPDE_NIL,
1056   AARCH64_OPDE_RECOVERABLE,
1057   AARCH64_OPDE_SYNTAX_ERROR,
1058   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1059   AARCH64_OPDE_INVALID_VARIANT,
1060   AARCH64_OPDE_UNTIED_OPERAND,
1061   AARCH64_OPDE_OUT_OF_RANGE,
1062   AARCH64_OPDE_UNALIGNED,
1063   AARCH64_OPDE_REG_LIST,
1064   AARCH64_OPDE_OTHER_ERROR
1065 };
1066
1067 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1068 struct aarch64_operand_error
1069 {
1070   enum aarch64_operand_error_kind kind;
1071   int index;
1072   const char *error;
1073   int data[3];  /* Some data for extra information.  */
1074 };
1075
1076 typedef struct aarch64_operand_error aarch64_operand_error;
1077
1078 /* Encoding entrypoint.  */
1079
1080 extern int
1081 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1082                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1083                        aarch64_operand_error *);
1084
1085 extern const aarch64_opcode *
1086 aarch64_replace_opcode (struct aarch64_inst *,
1087                         const aarch64_opcode *);
1088
1089 /* Given the opcode enumerator OP, return the pointer to the corresponding
1090    opcode entry.  */
1091
1092 extern const aarch64_opcode *
1093 aarch64_get_opcode (enum aarch64_op);
1094
1095 /* Generate the string representation of an operand.  */
1096 extern void
1097 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1098                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1099
1100 /* Miscellaneous interface.  */
1101
1102 extern int
1103 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1104
1105 extern aarch64_opnd_qualifier_t
1106 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1107                                 const aarch64_opnd_qualifier_t, int);
1108
1109 extern int
1110 aarch64_num_of_operands (const aarch64_opcode *);
1111
1112 extern int
1113 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1114
1115 extern int
1116 aarch64_zero_register_p (const aarch64_opnd_info *);
1117
1118 extern int
1119 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1120
1121 /* Given an operand qualifier, return the expected data element size
1122    of a qualified operand.  */
1123 extern unsigned char
1124 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1125
1126 extern enum aarch64_operand_class
1127 aarch64_get_operand_class (enum aarch64_opnd);
1128
1129 extern const char *
1130 aarch64_get_operand_name (enum aarch64_opnd);
1131
1132 extern const char *
1133 aarch64_get_operand_desc (enum aarch64_opnd);
1134
1135 extern bfd_boolean
1136 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1137
1138 #ifdef DEBUG_AARCH64
1139 extern int debug_dump;
1140
1141 extern void
1142 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1143
1144 #define DEBUG_TRACE(M, ...)                                     \
1145   {                                                             \
1146     if (debug_dump)                                             \
1147       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1148   }
1149
1150 #define DEBUG_TRACE_IF(C, M, ...)                               \
1151   {                                                             \
1152     if (debug_dump && (C))                                      \
1153       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1154   }
1155 #else  /* !DEBUG_AARCH64 */
1156 #define DEBUG_TRACE(M, ...) ;
1157 #define DEBUG_TRACE_IF(C, M, ...) ;
1158 #endif /* DEBUG_AARCH64 */
1159
1160 extern const char *const aarch64_sve_pattern_array[32];
1161 extern const char *const aarch64_sve_prfop_array[16];
1162
1163 #ifdef __cplusplus
1164 }
1165 #endif
1166
1167 #endif /* OPCODE_AARCH64_H */