include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2017 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  43 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  44 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  45 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  46 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  47 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  48 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  49 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  50 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  51 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  52 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  53 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  54 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  55 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  56 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  57 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  58
  59 /* Architectures are the sum of the base and extensions.  */
  60 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  61                                                  AARCH64_FEATURE_FP  \
  62                                                  | AARCH64_FEATURE_SIMD)
  63 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  64                                                  AARCH64_FEATURE_CRC    \
  65                                                  | AARCH64_FEATURE_V8_1 \
  66                                                  | AARCH64_FEATURE_LSE  \
  67                                                  | AARCH64_FEATURE_PAN  \
  68                                                  | AARCH64_FEATURE_LOR  \
  69                                                  | AARCH64_FEATURE_RDMA)
  70 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  71                                                  AARCH64_FEATURE_V8_2   \
  72                                                  | AARCH64_FEATURE_F16  \
  73                                                  | AARCH64_FEATURE_RAS)
  74 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  75                                                  AARCH64_FEATURE_V8_3   \
  76                                                  | AARCH64_FEATURE_RCPC \
  77                                                  | AARCH64_FEATURE_COMPNUM)
  78
  79 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  80 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  81
  82 /* CPU-specific features.  */
  83 typedef unsigned long aarch64_feature_set;
  84
  85 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  86   ((~(CPU) & (FEAT)) == 0)
  87
  88 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  89   (((CPU) & (FEAT)) != 0)
  90
  91 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  92   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  93
  94 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  95   do                                            \
  96     {                                           \
  97       (TARG) = (F1) | (F2);                     \
  98     }                                           \
  99   while (0)
 100
 101 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 102   do                                            \
 103     {                                           \
 104       (TARG) = (F1) &~ (F2);                    \
 105     }                                           \
 106   while (0)
 107
 108 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 109
 110 enum aarch64_operand_class
 111 {
 112   AARCH64_OPND_CLASS_NIL,
 113   AARCH64_OPND_CLASS_INT_REG,
 114   AARCH64_OPND_CLASS_MODIFIED_REG,
 115   AARCH64_OPND_CLASS_FP_REG,
 116   AARCH64_OPND_CLASS_SIMD_REG,
 117   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 118   AARCH64_OPND_CLASS_SISD_REG,
 119   AARCH64_OPND_CLASS_SIMD_REGLIST,
 120   AARCH64_OPND_CLASS_SVE_REG,
 121   AARCH64_OPND_CLASS_PRED_REG,
 122   AARCH64_OPND_CLASS_ADDRESS,
 123   AARCH64_OPND_CLASS_IMMEDIATE,
 124   AARCH64_OPND_CLASS_SYSTEM,
 125   AARCH64_OPND_CLASS_COND,
 126 };
 127
 128 /* Operand code that helps both parsing and coding.
 129    Keep AARCH64_OPERANDS synced.  */
 130
 131 enum aarch64_opnd
 132 {
 133   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 134
 135   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 136   AARCH64_OPND_Rn,      /* Integer register as source.  */
 137   AARCH64_OPND_Rm,      /* Integer register as source.  */
 138   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 139   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 140   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 141   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 142   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 143
 144   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 145   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 146   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 147   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 148   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 149   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 150
 151   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 152   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 153   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 154   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 155   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 156   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 157
 158   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 159   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 160   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 161
 162   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 163   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 164   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 165   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 166   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 167   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 168   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 169   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 170   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 171   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 172   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 173                            structure to all lanes.  */
 174   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 175
 176   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 177   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 178
 179   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 180   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 181   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 182   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 183   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 184   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 185   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 186                            (no encoding).  */
 187   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 188   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 189   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 190   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 191   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 192   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 193   AARCH64_OPND_IMM,     /* Immediate.  */
 194   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 195   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 196   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 197   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 198   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 199   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 200   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 201   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 202   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 203                            each condition flag.  */
 204
 205   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 206   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 207   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 208   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 209   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 210   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 211   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 212   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 213
 214   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 215   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 216
 217   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 218   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 219   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 220   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 221   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 222
 223   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 224   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 225   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 226   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 227   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 228                                    negative or unaligned and there is
 229                                    no writeback allowed.  This operand code
 230                                    is only used to support the programmer-
 231                                    friendly feature of using LDR/STR as the
 232                                    the mnemonic name for LDUR/STUR instructions
 233                                    wherever there is no ambiguity.  */
 234   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 235   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 236   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 237   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 238
 239   AARCH64_OPND_SYSREG,          /* System register operand.  */
 240   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 241   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 242   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 243   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 244   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 245   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 246   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 247   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 248   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 249
 250   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 251   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 252   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 253   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 254   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 255   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 256   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 257   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 258   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 259   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 260   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 261   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 262   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 263   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 264   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 265   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 266   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 267   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 268   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 269   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 270   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 271   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 272   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 273                                        Bit 14 controls S/U choice.  */
 274   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 275                                        Bit 22 controls S/U choice.  */
 276   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 277                                        Bit 14 controls S/U choice.  */
 278   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 279                                        Bit 22 controls S/U choice.  */
 280   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 281                                        Bit 14 controls S/U choice.  */
 282   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 283                                        Bit 22 controls S/U choice.  */
 284   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 285                                        Bit 14 controls S/U choice.  */
 286   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 287                                        Bit 22 controls S/U choice.  */
 288   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 289   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 290   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 291   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 292   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 293   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 294   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 295   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 296   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 297   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 298   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 299   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 300   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 301   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 302   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 303   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 304   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 305   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 306   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 307   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 308   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 309   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 310   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 311   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 312   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 313   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 314   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 315   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 316   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 317   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 318   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 319   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 320   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 321   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 322   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 323   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 324   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 325   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 326   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 327   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 328   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 329   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 330   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 331   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 332   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 333   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 334   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 335   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 336   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 337   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 338   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 339   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 340   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 341   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 342   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 343 };
 344
 345 /* Qualifier constrains an operand.  It either specifies a variant of an
 346    operand type or limits values available to an operand type.
 347
 348    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 349
 350 enum aarch64_opnd_qualifier
 351 {
 352   /* Indicating no further qualification on an operand.  */
 353   AARCH64_OPND_QLF_NIL,
 354
 355   /* Qualifying an operand which is a general purpose (integer) register;
 356      indicating the operand data size or a specific register.  */
 357   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 358   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 359   AARCH64_OPND_QLF_WSP, /* WSP.  */
 360   AARCH64_OPND_QLF_SP,  /* SP.  */
 361
 362   /* Qualifying an operand which is a floating-point register, a SIMD
 363      vector element or a SIMD vector element list; indicating operand data
 364      size or the size of each SIMD vector element in the case of a SIMD
 365      vector element list.
 366      These qualifiers are also used to qualify an address operand to
 367      indicate the size of data element a load/store instruction is
 368      accessing.
 369      They are also used for the immediate shift operand in e.g. SSHR.  Such
 370      a use is only for the ease of operand encoding/decoding and qualifier
 371      sequence matching; such a use should not be applied widely; use the value
 372      constraint qualifiers for immediate operands wherever possible.  */
 373   AARCH64_OPND_QLF_S_B,
 374   AARCH64_OPND_QLF_S_H,
 375   AARCH64_OPND_QLF_S_S,
 376   AARCH64_OPND_QLF_S_D,
 377   AARCH64_OPND_QLF_S_Q,
 378
 379   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 380      register list; indicating register shape.
 381      They are also used for the immediate shift operand in e.g. SSHR.  Such
 382      a use is only for the ease of operand encoding/decoding and qualifier
 383      sequence matching; such a use should not be applied widely; use the value
 384      constraint qualifiers for immediate operands wherever possible.  */
 385   AARCH64_OPND_QLF_V_8B,
 386   AARCH64_OPND_QLF_V_16B,
 387   AARCH64_OPND_QLF_V_2H,
 388   AARCH64_OPND_QLF_V_4H,
 389   AARCH64_OPND_QLF_V_8H,
 390   AARCH64_OPND_QLF_V_2S,
 391   AARCH64_OPND_QLF_V_4S,
 392   AARCH64_OPND_QLF_V_1D,
 393   AARCH64_OPND_QLF_V_2D,
 394   AARCH64_OPND_QLF_V_1Q,
 395
 396   AARCH64_OPND_QLF_P_Z,
 397   AARCH64_OPND_QLF_P_M,
 398
 399   /* Constraint on value.  */
 400   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 401   AARCH64_OPND_QLF_imm_0_7,
 402   AARCH64_OPND_QLF_imm_0_15,
 403   AARCH64_OPND_QLF_imm_0_31,
 404   AARCH64_OPND_QLF_imm_0_63,
 405   AARCH64_OPND_QLF_imm_1_32,
 406   AARCH64_OPND_QLF_imm_1_64,
 407
 408   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 409      or shift-ones.  */
 410   AARCH64_OPND_QLF_LSL,
 411   AARCH64_OPND_QLF_MSL,
 412
 413   /* Special qualifier helping retrieve qualifier information during the
 414      decoding time (currently not in use).  */
 415   AARCH64_OPND_QLF_RETRIEVE,
 416 };
 417 \f
 418 /* Instruction class.  */
 419
 420 enum aarch64_insn_class
 421 {
 422   addsub_carry,
 423   addsub_ext,
 424   addsub_imm,
 425   addsub_shift,
 426   asimdall,
 427   asimddiff,
 428   asimdelem,
 429   asimdext,
 430   asimdimm,
 431   asimdins,
 432   asimdmisc,
 433   asimdperm,
 434   asimdsame,
 435   asimdshf,
 436   asimdtbl,
 437   asisddiff,
 438   asisdelem,
 439   asisdlse,
 440   asisdlsep,
 441   asisdlso,
 442   asisdlsop,
 443   asisdmisc,
 444   asisdone,
 445   asisdpair,
 446   asisdsame,
 447   asisdshf,
 448   bitfield,
 449   branch_imm,
 450   branch_reg,
 451   compbranch,
 452   condbranch,
 453   condcmp_imm,
 454   condcmp_reg,
 455   condsel,
 456   cryptoaes,
 457   cryptosha2,
 458   cryptosha3,
 459   dp_1src,
 460   dp_2src,
 461   dp_3src,
 462   exception,
 463   extract,
 464   float2fix,
 465   float2int,
 466   floatccmp,
 467   floatcmp,
 468   floatdp1,
 469   floatdp2,
 470   floatdp3,
 471   floatimm,
 472   floatsel,
 473   ldst_immpost,
 474   ldst_immpre,
 475   ldst_imm9,    /* immpost or immpre */
 476   ldst_imm10,   /* LDRAA/LDRAB */
 477   ldst_pos,
 478   ldst_regoff,
 479   ldst_unpriv,
 480   ldst_unscaled,
 481   ldstexcl,
 482   ldstnapair_offs,
 483   ldstpair_off,
 484   ldstpair_indexed,
 485   loadlit,
 486   log_imm,
 487   log_shift,
 488   lse_atomic,
 489   movewide,
 490   pcreladdr,
 491   ic_system,
 492   sve_cpy,
 493   sve_index,
 494   sve_limm,
 495   sve_misc,
 496   sve_movprfx,
 497   sve_pred_zm,
 498   sve_shift_pred,
 499   sve_shift_unpred,
 500   sve_size_bhs,
 501   sve_size_bhsd,
 502   sve_size_hsd,
 503   sve_size_sd,
 504   testbranch,
 505 };
 506
 507 /* Opcode enumerators.  */
 508
 509 enum aarch64_op
 510 {
 511   OP_NIL,
 512   OP_STRB_POS,
 513   OP_LDRB_POS,
 514   OP_LDRSB_POS,
 515   OP_STRH_POS,
 516   OP_LDRH_POS,
 517   OP_LDRSH_POS,
 518   OP_STR_POS,
 519   OP_LDR_POS,
 520   OP_STRF_POS,
 521   OP_LDRF_POS,
 522   OP_LDRSW_POS,
 523   OP_PRFM_POS,
 524
 525   OP_STURB,
 526   OP_LDURB,
 527   OP_LDURSB,
 528   OP_STURH,
 529   OP_LDURH,
 530   OP_LDURSH,
 531   OP_STUR,
 532   OP_LDUR,
 533   OP_STURV,
 534   OP_LDURV,
 535   OP_LDURSW,
 536   OP_PRFUM,
 537
 538   OP_LDR_LIT,
 539   OP_LDRV_LIT,
 540   OP_LDRSW_LIT,
 541   OP_PRFM_LIT,
 542
 543   OP_ADD,
 544   OP_B,
 545   OP_BL,
 546
 547   OP_MOVN,
 548   OP_MOVZ,
 549   OP_MOVK,
 550
 551   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 552   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 553   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 554
 555   OP_MOV_V,             /* MOV alias for moving vector register.  */
 556
 557   OP_ASR_IMM,
 558   OP_LSR_IMM,
 559   OP_LSL_IMM,
 560
 561   OP_BIC,
 562
 563   OP_UBFX,
 564   OP_BFXIL,
 565   OP_SBFX,
 566   OP_SBFIZ,
 567   OP_BFI,
 568   OP_BFC,               /* ARMv8.2.  */
 569   OP_UBFIZ,
 570   OP_UXTB,
 571   OP_UXTH,
 572   OP_UXTW,
 573
 574   OP_CINC,
 575   OP_CINV,
 576   OP_CNEG,
 577   OP_CSET,
 578   OP_CSETM,
 579
 580   OP_FCVT,
 581   OP_FCVTN,
 582   OP_FCVTN2,
 583   OP_FCVTL,
 584   OP_FCVTL2,
 585   OP_FCVTXN_S,          /* Scalar version.  */
 586
 587   OP_ROR_IMM,
 588
 589   OP_SXTL,
 590   OP_SXTL2,
 591   OP_UXTL,
 592   OP_UXTL2,
 593
 594   OP_MOV_P_P,
 595   OP_MOV_Z_P_Z,
 596   OP_MOV_Z_V,
 597   OP_MOV_Z_Z,
 598   OP_MOV_Z_Zi,
 599   OP_MOVM_P_P_P,
 600   OP_MOVS_P_P,
 601   OP_MOVZS_P_P_P,
 602   OP_MOVZ_P_P_P,
 603   OP_NOTS_P_P_P_Z,
 604   OP_NOT_P_P_P_Z,
 605
 606   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 607
 608   OP_TOTAL_NUM,         /* Pseudo.  */
 609 };
 610
 611 /* Maximum number of operands an instruction can have.  */
 612 #define AARCH64_MAX_OPND_NUM 6
 613 /* Maximum number of qualifier sequences an instruction can have.  */
 614 #define AARCH64_MAX_QLF_SEQ_NUM 10
 615 /* Operand qualifier typedef; optimized for the size.  */
 616 typedef unsigned char aarch64_opnd_qualifier_t;
 617 /* Operand qualifier sequence typedef.  */
 618 typedef aarch64_opnd_qualifier_t        \
 619           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 620
 621 /* FIXME: improve the efficiency.  */
 622 static inline bfd_boolean
 623 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 624 {
 625   int i;
 626   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 627     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 628       return FALSE;
 629   return TRUE;
 630 }
 631
 632 /* This structure holds information for a particular opcode.  */
 633
 634 struct aarch64_opcode
 635 {
 636   /* The name of the mnemonic.  */
 637   const char *name;
 638
 639   /* The opcode itself.  Those bits which will be filled in with
 640      operands are zeroes.  */
 641   aarch64_insn opcode;
 642
 643   /* The opcode mask.  This is used by the disassembler.  This is a
 644      mask containing ones indicating those bits which must match the
 645      opcode field, and zeroes indicating those bits which need not
 646      match (and are presumably filled in by operands).  */
 647   aarch64_insn mask;
 648
 649   /* Instruction class.  */
 650   enum aarch64_insn_class iclass;
 651
 652   /* Enumerator identifier.  */
 653   enum aarch64_op op;
 654
 655   /* Which architecture variant provides this instruction.  */
 656   const aarch64_feature_set *avariant;
 657
 658   /* An array of operand codes.  Each code is an index into the
 659      operand table.  They appear in the order which the operands must
 660      appear in assembly code, and are terminated by a zero.  */
 661   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 662
 663   /* A list of operand qualifier code sequence.  Each operand qualifier
 664      code qualifies the corresponding operand code.  Each operand
 665      qualifier sequence specifies a valid opcode variant and related
 666      constraint on operands.  */
 667   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 668
 669   /* Flags providing information about this instruction */
 670   uint32_t flags;
 671
 672   /* If nonzero, this operand and operand 0 are both registers and
 673      are required to have the same register number.  */
 674   unsigned char tied_operand;
 675
 676   /* If non-NULL, a function to verify that a given instruction is valid.  */
 677   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 678 };
 679
 680 typedef struct aarch64_opcode aarch64_opcode;
 681
 682 /* Table describing all the AArch64 opcodes.  */
 683 extern aarch64_opcode aarch64_opcode_table[];
 684
 685 /* Opcode flags.  */
 686 #define F_ALIAS (1 << 0)
 687 #define F_HAS_ALIAS (1 << 1)
 688 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 689    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 690 #define F_P1 (1 << 2)
 691 #define F_P2 (2 << 2)
 692 #define F_P3 (3 << 2)
 693 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 694 #define F_COND (1 << 4)
 695 /* Instruction has the field of 'sf'.  */
 696 #define F_SF (1 << 5)
 697 /* Instruction has the field of 'size:Q'.  */
 698 #define F_SIZEQ (1 << 6)
 699 /* Floating-point instruction has the field of 'type'.  */
 700 #define F_FPTYPE (1 << 7)
 701 /* AdvSIMD scalar instruction has the field of 'size'.  */
 702 #define F_SSIZE (1 << 8)
 703 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 704 #define F_T (1 << 9)
 705 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 706 #define F_GPRSIZE_IN_Q (1 << 10)
 707 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 708 #define F_LDS_SIZE (1 << 11)
 709 /* Optional operand; assume maximum of 1 operand can be optional.  */
 710 #define F_OPD0_OPT (1 << 12)
 711 #define F_OPD1_OPT (2 << 12)
 712 #define F_OPD2_OPT (3 << 12)
 713 #define F_OPD3_OPT (4 << 12)
 714 #define F_OPD4_OPT (5 << 12)
 715 /* Default value for the optional operand when omitted from the assembly.  */
 716 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 717 /* Instruction that is an alias of another instruction needs to be
 718    encoded/decoded by converting it to/from the real form, followed by
 719    the encoding/decoding according to the rules of the real opcode.
 720    This compares to the direct coding using the alias's information.
 721    N.B. this flag requires F_ALIAS to be used together.  */
 722 #define F_CONV (1 << 20)
 723 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 724    friendly pseudo instruction available only in the assembly code (thus will
 725    not show up in the disassembly).  */
 726 #define F_PSEUDO (1 << 21)
 727 /* Instruction has miscellaneous encoding/decoding rules.  */
 728 #define F_MISC (1 << 22)
 729 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 730 #define F_N (1 << 23)
 731 /* Opcode dependent field.  */
 732 #define F_OD(X) (((X) & 0x7) << 24)
 733 /* Instruction has the field of 'sz'.  */
 734 #define F_LSE_SZ (1 << 27)
 735 /* Require an exact qualifier match, even for NIL qualifiers.  */
 736 #define F_STRICT (1ULL << 28)
 737 /* Next bit is 29.  */
 738
 739 static inline bfd_boolean
 740 alias_opcode_p (const aarch64_opcode *opcode)
 741 {
 742   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 743 }
 744
 745 static inline bfd_boolean
 746 opcode_has_alias (const aarch64_opcode *opcode)
 747 {
 748   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 749 }
 750
 751 /* Priority for disassembling preference.  */
 752 static inline int
 753 opcode_priority (const aarch64_opcode *opcode)
 754 {
 755   return (opcode->flags >> 2) & 0x3;
 756 }
 757
 758 static inline bfd_boolean
 759 pseudo_opcode_p (const aarch64_opcode *opcode)
 760 {
 761   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 762 }
 763
 764 static inline bfd_boolean
 765 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 766 {
 767   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 768     ? TRUE : FALSE;
 769 }
 770
 771 static inline aarch64_insn
 772 get_optional_operand_default_value (const aarch64_opcode *opcode)
 773 {
 774   return (opcode->flags >> 15) & 0x1f;
 775 }
 776
 777 static inline unsigned int
 778 get_opcode_dependent_value (const aarch64_opcode *opcode)
 779 {
 780   return (opcode->flags >> 24) & 0x7;
 781 }
 782
 783 static inline bfd_boolean
 784 opcode_has_special_coder (const aarch64_opcode *opcode)
 785 {
 786   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 787           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 788     : FALSE;
 789 }
 790 \f
 791 struct aarch64_name_value_pair
 792 {
 793   const char *  name;
 794   aarch64_insn  value;
 795 };
 796
 797 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 798 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 799 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 800 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 801
 802 typedef struct
 803 {
 804   const char *  name;
 805   aarch64_insn  value;
 806   uint32_t      flags;
 807 } aarch64_sys_reg;
 808
 809 extern const aarch64_sys_reg aarch64_sys_regs [];
 810 extern const aarch64_sys_reg aarch64_pstatefields [];
 811 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 812 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 813                                                 const aarch64_sys_reg *);
 814 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 815                                                     const aarch64_sys_reg *);
 816
 817 typedef struct
 818 {
 819   const char *name;
 820   uint32_t value;
 821   uint32_t flags ;
 822 } aarch64_sys_ins_reg;
 823
 824 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 825 extern bfd_boolean
 826 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 827                                  const aarch64_sys_ins_reg *);
 828
 829 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 830 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 831 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 832 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 833
 834 /* Shift/extending operator kinds.
 835    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 836 enum aarch64_modifier_kind
 837 {
 838   AARCH64_MOD_NONE,
 839   AARCH64_MOD_MSL,
 840   AARCH64_MOD_ROR,
 841   AARCH64_MOD_ASR,
 842   AARCH64_MOD_LSR,
 843   AARCH64_MOD_LSL,
 844   AARCH64_MOD_UXTB,
 845   AARCH64_MOD_UXTH,
 846   AARCH64_MOD_UXTW,
 847   AARCH64_MOD_UXTX,
 848   AARCH64_MOD_SXTB,
 849   AARCH64_MOD_SXTH,
 850   AARCH64_MOD_SXTW,
 851   AARCH64_MOD_SXTX,
 852   AARCH64_MOD_MUL,
 853   AARCH64_MOD_MUL_VL,
 854 };
 855
 856 bfd_boolean
 857 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 858
 859 enum aarch64_modifier_kind
 860 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 861 /* Condition.  */
 862
 863 typedef struct
 864 {
 865   /* A list of names with the first one as the disassembly preference;
 866      terminated by NULL if fewer than 3.  */
 867   const char *names[4];
 868   aarch64_insn value;
 869 } aarch64_cond;
 870
 871 extern const aarch64_cond aarch64_conds[16];
 872
 873 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 874 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 875 \f
 876 /* Structure representing an operand.  */
 877
 878 struct aarch64_opnd_info
 879 {
 880   enum aarch64_opnd type;
 881   aarch64_opnd_qualifier_t qualifier;
 882   int idx;
 883
 884   union
 885     {
 886       struct
 887         {
 888           unsigned regno;
 889         } reg;
 890       struct
 891         {
 892           unsigned int regno;
 893           int64_t index;
 894         } reglane;
 895       /* e.g. LVn.  */
 896       struct
 897         {
 898           unsigned first_regno : 5;
 899           unsigned num_regs : 3;
 900           /* 1 if it is a list of reg element.  */
 901           unsigned has_index : 1;
 902           /* Lane index; valid only when has_index is 1.  */
 903           int64_t index;
 904         } reglist;
 905       /* e.g. immediate or pc relative address offset.  */
 906       struct
 907         {
 908           int64_t value;
 909           unsigned is_fp : 1;
 910         } imm;
 911       /* e.g. address in STR (register offset).  */
 912       struct
 913         {
 914           unsigned base_regno;
 915           struct
 916             {
 917               union
 918                 {
 919                   int imm;
 920                   unsigned regno;
 921                 };
 922               unsigned is_reg;
 923             } offset;
 924           unsigned pcrel : 1;           /* PC-relative.  */
 925           unsigned writeback : 1;
 926           unsigned preind : 1;          /* Pre-indexed.  */
 927           unsigned postind : 1;         /* Post-indexed.  */
 928         } addr;
 929       const aarch64_cond *cond;
 930       /* The encoding of the system register.  */
 931       aarch64_insn sysreg;
 932       /* The encoding of the PSTATE field.  */
 933       aarch64_insn pstatefield;
 934       const aarch64_sys_ins_reg *sysins_op;
 935       const struct aarch64_name_value_pair *barrier;
 936       const struct aarch64_name_value_pair *hint_option;
 937       const struct aarch64_name_value_pair *prfop;
 938     };
 939
 940   /* Operand shifter; in use when the operand is a register offset address,
 941      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 942   struct
 943     {
 944       enum aarch64_modifier_kind kind;
 945       unsigned operator_present: 1;     /* Only valid during encoding.  */
 946       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 947       unsigned amount_present: 1;
 948       int64_t amount;
 949     } shifter;
 950
 951   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 952                            to be done on it.  In some (but not all) of these
 953                            cases, we need to tell libopcodes to skip the
 954                            constraint checking and the encoding for this
 955                            operand, so that the libopcodes can pick up the
 956                            right opcode before the operand is fixed-up.  This
 957                            flag should only be used during the
 958                            assembling/encoding.  */
 959   unsigned present:1;   /* Whether this operand is present in the assembly
 960                            line; not used during the disassembly.  */
 961 };
 962
 963 typedef struct aarch64_opnd_info aarch64_opnd_info;
 964
 965 /* Structure representing an instruction.
 966
 967    It is used during both the assembling and disassembling.  The assembler
 968    fills an aarch64_inst after a successful parsing and then passes it to the
 969    encoding routine to do the encoding.  During the disassembling, the
 970    disassembler calls the decoding routine to decode a binary instruction; on a
 971    successful return, such a structure will be filled with information of the
 972    instruction; then the disassembler uses the information to print out the
 973    instruction.  */
 974
 975 struct aarch64_inst
 976 {
 977   /* The value of the binary instruction.  */
 978   aarch64_insn value;
 979
 980   /* Corresponding opcode entry.  */
 981   const aarch64_opcode *opcode;
 982
 983   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 984   const aarch64_cond *cond;
 985
 986   /* Operands information.  */
 987   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 988 };
 989
 990 typedef struct aarch64_inst aarch64_inst;
 991 \f
 992 /* Diagnosis related declaration and interface.  */
 993
 994 /* Operand error kind enumerators.
 995
 996    AARCH64_OPDE_RECOVERABLE
 997      Less severe error found during the parsing, very possibly because that
 998      GAS has picked up a wrong instruction template for the parsing.
 999
1000    AARCH64_OPDE_SYNTAX_ERROR
1001      General syntax error; it can be either a user error, or simply because
1002      that GAS is trying a wrong instruction template.
1003
1004    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1005      Definitely a user syntax error.
1006
1007    AARCH64_OPDE_INVALID_VARIANT
1008      No syntax error, but the operands are not a valid combination, e.g.
1009      FMOV D0,S0
1010
1011    AARCH64_OPDE_UNTIED_OPERAND
1012      The asm failed to use the same register for a destination operand
1013      and a tied source operand.
1014
1015    AARCH64_OPDE_OUT_OF_RANGE
1016      Error about some immediate value out of a valid range.
1017
1018    AARCH64_OPDE_UNALIGNED
1019      Error about some immediate value not properly aligned (i.e. not being a
1020      multiple times of a certain value).
1021
1022    AARCH64_OPDE_REG_LIST
1023      Error about the register list operand having unexpected number of
1024      registers.
1025
1026    AARCH64_OPDE_OTHER_ERROR
1027      Error of the highest severity and used for any severe issue that does not
1028      fall into any of the above categories.
1029
1030    The enumerators are only interesting to GAS.  They are declared here (in
1031    libopcodes) because that some errors are detected (and then notified to GAS)
1032    by libopcodes (rather than by GAS solely).
1033
1034    The first three errors are only deteced by GAS while the
1035    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1036    only libopcodes has the information about the valid variants of each
1037    instruction.
1038
1039    The enumerators have an increasing severity.  This is helpful when there are
1040    multiple instruction templates available for a given mnemonic name (e.g.
1041    FMOV); this mechanism will help choose the most suitable template from which
1042    the generated diagnostics can most closely describe the issues, if any.  */
1043
1044 enum aarch64_operand_error_kind
1045 {
1046   AARCH64_OPDE_NIL,
1047   AARCH64_OPDE_RECOVERABLE,
1048   AARCH64_OPDE_SYNTAX_ERROR,
1049   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1050   AARCH64_OPDE_INVALID_VARIANT,
1051   AARCH64_OPDE_UNTIED_OPERAND,
1052   AARCH64_OPDE_OUT_OF_RANGE,
1053   AARCH64_OPDE_UNALIGNED,
1054   AARCH64_OPDE_REG_LIST,
1055   AARCH64_OPDE_OTHER_ERROR
1056 };
1057
1058 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1059 struct aarch64_operand_error
1060 {
1061   enum aarch64_operand_error_kind kind;
1062   int index;
1063   const char *error;
1064   int data[3];  /* Some data for extra information.  */
1065 };
1066
1067 typedef struct aarch64_operand_error aarch64_operand_error;
1068
1069 /* Encoding entrypoint.  */
1070
1071 extern int
1072 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1073                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1074                        aarch64_operand_error *);
1075
1076 extern const aarch64_opcode *
1077 aarch64_replace_opcode (struct aarch64_inst *,
1078                         const aarch64_opcode *);
1079
1080 /* Given the opcode enumerator OP, return the pointer to the corresponding
1081    opcode entry.  */
1082
1083 extern const aarch64_opcode *
1084 aarch64_get_opcode (enum aarch64_op);
1085
1086 /* Generate the string representation of an operand.  */
1087 extern void
1088 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1089                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1090
1091 /* Miscellaneous interface.  */
1092
1093 extern int
1094 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1095
1096 extern aarch64_opnd_qualifier_t
1097 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1098                                 const aarch64_opnd_qualifier_t, int);
1099
1100 extern int
1101 aarch64_num_of_operands (const aarch64_opcode *);
1102
1103 extern int
1104 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1105
1106 extern int
1107 aarch64_zero_register_p (const aarch64_opnd_info *);
1108
1109 extern int
1110 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1111
1112 /* Given an operand qualifier, return the expected data element size
1113    of a qualified operand.  */
1114 extern unsigned char
1115 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1116
1117 extern enum aarch64_operand_class
1118 aarch64_get_operand_class (enum aarch64_opnd);
1119
1120 extern const char *
1121 aarch64_get_operand_name (enum aarch64_opnd);
1122
1123 extern const char *
1124 aarch64_get_operand_desc (enum aarch64_opnd);
1125
1126 extern bfd_boolean
1127 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1128
1129 #ifdef DEBUG_AARCH64
1130 extern int debug_dump;
1131
1132 extern void
1133 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1134
1135 #define DEBUG_TRACE(M, ...)                                     \
1136   {                                                             \
1137     if (debug_dump)                                             \
1138       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1139   }
1140
1141 #define DEBUG_TRACE_IF(C, M, ...)                               \
1142   {                                                             \
1143     if (debug_dump && (C))                                      \
1144       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1145   }
1146 #else  /* !DEBUG_AARCH64 */
1147 #define DEBUG_TRACE(M, ...) ;
1148 #define DEBUG_TRACE_IF(C, M, ...) ;
1149 #endif /* DEBUG_AARCH64 */
1150
1151 extern const char *const aarch64_sve_pattern_array[32];
1152 extern const char *const aarch64_sve_prfop_array[16];
1153
1154 #ifdef __cplusplus
1155 }
1156 #endif
1157
1158 #endif /* OPCODE_AARCH64_H */