include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifndef MAX_INSN_ARGS
  28 #define MAX_INSN_ARGS        6
  29 #endif
  30
  31 #ifndef MAX_INSN_FLGS
  32 #define MAX_INSN_FLGS        3
  33 #endif
  34
  35 /* Instruction Class.  */
  36 typedef enum
  37   {
  38     ARITH,
  39     AUXREG,
  40     BRANCH,
  41     CONTROL,
  42     DSP,
  43     FLOAT,
  44     INVALID,
  45     JUMP,
  46     KERNEL,
  47     LOGICAL,
  48     MEMORY,
  49   } insn_class_t;
  50
  51 /* Instruction Subclass.  */
  52 typedef enum
  53   {
  54     NONE,
  55     CVT,
  56     BTSCN,
  57     CD1,
  58     CD2,
  59     DIV,
  60     DP,
  61     MPY1E,
  62     MPY6E,
  63     MPY7E,
  64     MPY8E,
  65     MPY9E,
  66     SHFT1,
  67     SHFT2,
  68     SWAP,
  69     SP
  70   } insn_subclass_t;
  71
  72 /* Flags class.  */
  73 typedef enum
  74   {
  75     FNONE,
  76     CND,  /* Conditional flags.  */
  77     WBM,  /* Write-back modes.  */
  78     FLG,  /* F Flag.  */
  79     SBP,  /* Static branch prediction.  */
  80     DLY,  /* Delay slot.  */
  81     DIF,  /* Bypass caches.  */
  82     SGX,  /* Sign extend modes.  */
  83     SZM   /* Data size modes.  */
  84   } flag_class_t;
  85
  86 /* The opcode table is an array of struct arc_opcode.  */
  87 struct arc_opcode
  88 {
  89   /* The opcode name.  */
  90   const char *name;
  91
  92   /* The opcode itself.  Those bits which will be filled in with
  93      operands are zeroes.  */
  94   unsigned opcode;
  95
  96   /* The opcode mask.  This is used by the disassembler.  This is a
  97      mask containing ones indicating those bits which must match the
  98      opcode field, and zeroes indicating those bits which need not
  99      match (and are presumably filled in by operands).  */
 100   unsigned mask;
 101
 102   /* One bit flags for the opcode.  These are primarily used to
 103      indicate specific processors and environments support the
 104      instructions.  The defined values are listed below.  */
 105   unsigned cpu;
 106
 107   /* The instruction class.  This is used by gdb.  */
 108   insn_class_t class;
 109
 110   /* The instruction subclass.  */
 111   insn_subclass_t subclass;
 112
 113   /* An array of operand codes.  Each code is an index into the
 114      operand table.  They appear in the order which the operands must
 115      appear in assembly code, and are terminated by a zero.  */
 116   unsigned char operands[MAX_INSN_ARGS + 1];
 117
 118   /* An array of flag codes.  Each code is an index into the flag
 119      table.  They appear in the order which the flags must appear in
 120      assembly code, and are terminated by a zero.  */
 121   unsigned char flags[MAX_INSN_FLGS + 1];
 122 };
 123
 124 /* The table itself is sorted by major opcode number, and is otherwise
 125    in the order in which the disassembler should consider
 126    instructions.  */
 127 extern const struct arc_opcode arc_opcodes[];
 128 extern const unsigned arc_num_opcodes;
 129
 130 /* CPU Availability.  */
 131 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 132 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 133 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 134 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 135
 136 /* CPU extensions.  */
 137 #define ARC_EA       0x0001
 138 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 139 #define ARC_LLOCK    0x0002
 140 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 141 #define ARC_MPY      0x0004
 142 #define ARC_MULT     0x0004
 143
 144 /* Floating point support.  */
 145 #define ARC_DPFP     0x0010
 146 #define ARC_SPFP     0x0020
 147 #define ARC_FPU      0x0030
 148
 149 /* NORM & SWAP.  */
 150 #define ARC_SWAP     0x0100
 151 #define ARC_NORM     0x0200
 152 #define ARC_BSCAN    0x0200
 153
 154 /* A7 specific.  */
 155 #define ARC_UIX      0x1000
 156 #define ARC_TSTAMP   0x1000
 157
 158 /* A6 specific.  */
 159 #define ARC_VBFDW    0x1000
 160 #define ARC_BARREL   0x1000
 161 #define ARC_DSPA     0x1000
 162
 163 /* EM specific.  */
 164 #define ARC_SHIFT    0x1000
 165
 166 /* V2 specific.  */
 167 #define ARC_INTR     0x1000
 168 #define ARC_DIV      0x1000
 169
 170 /* V1 specific.  */
 171 #define ARC_XMAC     0x1000
 172 #define ARC_CRC      0x1000
 173
 174 /* Base architecture -- all cpus.  */
 175 #define ARC_OPCODE_BASE                         \
 176   (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700        \
 177    | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 178
 179 /* A macro to check for short instructions.  */
 180 #define ARC_SHORT(mask)                         \
 181   (((mask) & 0xFFFF0000) ? 0 : 1)
 182
 183 /* The operands table is an array of struct arc_operand.  */
 184 struct arc_operand
 185 {
 186   /* The number of bits in the operand.  */
 187   unsigned int bits;
 188
 189   /* How far the operand is left shifted in the instruction.  */
 190   unsigned int shift;
 191
 192   /* The default relocation type for this operand.  */
 193   signed int default_reloc;
 194
 195   /* One bit syntax flags.  */
 196   unsigned int flags;
 197
 198   /* Insertion function.  This is used by the assembler.  To insert an
 199      operand value into an instruction, check this field.
 200
 201      If it is NULL, execute
 202          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 203      (i is the instruction which we are filling in, o is a pointer to
 204      this structure, and op is the opcode value; this assumes twos
 205      complement arithmetic).
 206
 207      If this field is not NULL, then simply call it with the
 208      instruction and the operand value.  It will return the new value
 209      of the instruction.  If the ERRMSG argument is not NULL, then if
 210      the operand value is illegal, *ERRMSG will be set to a warning
 211      string (the operand will be inserted in any case).  If the
 212      operand value is legal, *ERRMSG will be unchanged (most operands
 213      can accept any value).  */
 214   unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
 215
 216   /* Extraction function.  This is used by the disassembler.  To
 217      extract this operand type from an instruction, check this field.
 218
 219      If it is NULL, compute
 220          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 221          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 222              && (op & (1 << (o->bits - 1))) != 0)
 223            op -= 1 << o->bits;
 224      (i is the instruction, o is a pointer to this structure, and op
 225      is the result; this assumes twos complement arithmetic).
 226
 227      If this field is not NULL, then simply call it with the
 228      instruction value.  It will return the value of the operand.  If
 229      the INVALID argument is not NULL, *INVALID will be set to
 230      TRUE if this operand type can not actually be extracted from
 231      this operand (i.e., the instruction does not match).  If the
 232      operand is valid, *INVALID will not be changed.  */
 233   int (*extract) (unsigned instruction, bfd_boolean *invalid);
 234 };
 235
 236 /* Elements in the table are retrieved by indexing with values from
 237    the operands field of the arc_opcodes table.  */
 238 extern const struct arc_operand arc_operands[];
 239 extern const unsigned arc_num_operands;
 240 extern const unsigned arc_Toperand;
 241 extern const unsigned arc_NToperand;
 242
 243 /* Values defined for the flags field of a struct arc_operand.  */
 244
 245 /* This operand does not actually exist in the assembler input.  This
 246    is used to support extended mnemonics, for which two operands fields
 247    are identical.  The assembler should call the insert function with
 248    any op value.  The disassembler should call the extract function,
 249    ignore the return value, and check the value placed in the invalid
 250    argument.  */
 251 #define ARC_OPERAND_FAKE        0x0001
 252
 253 /* This operand names an integer register.  */
 254 #define ARC_OPERAND_IR          0x0002
 255
 256 /* This operand takes signed values.  */
 257 #define ARC_OPERAND_SIGNED      0x0004
 258
 259 /* This operand takes unsigned values.  This exists primarily so that
 260    a flags value of 0 can be treated as end-of-arguments.  */
 261 #define ARC_OPERAND_UNSIGNED    0x0008
 262
 263 /* This operand takes long immediate values.  */
 264 #define ARC_OPERAND_LIMM        0x0010
 265
 266 /* This operand is identical like the previous one.  */
 267 #define ARC_OPERAND_DUPLICATE   0x0020
 268
 269 /* This operand is PC relative.  Used for internal relocs.  */
 270 #define ARC_OPERAND_PCREL       0x0040
 271
 272 /* This operand is truncated.  The truncation is done accordingly to
 273    operand alignment attribute.  */
 274 #define ARC_OPERAND_TRUNCATE    0x0080
 275
 276 /* This operand is 16bit aligned.  */
 277 #define ARC_OPERAND_ALIGNED16   0x0100
 278
 279 /* This operand is 32bit aligned.  */
 280 #define ARC_OPERAND_ALIGNED32   0x0200
 281
 282 /* This operand can be ignored by matching process if it is not
 283    present.  */
 284 #define ARC_OPERAND_IGNORE      0x0400
 285
 286 /* Don't check the range when matching.  */
 287 #define ARC_OPERAND_NCHK        0x0800
 288
 289 /* Mark the braket possition.  */
 290 #define ARC_OPERAND_BRAKET      0x1000
 291
 292 /* Mask for selecting the type for typecheck purposes.  */
 293 #define ARC_OPERAND_TYPECHECK_MASK              \
 294   (ARC_OPERAND_IR |                             \
 295    ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED |      \
 296    ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
 297
 298 /* The flags structure.  */
 299 struct arc_flag_operand
 300 {
 301   /* The flag name.  */
 302   const char *name;
 303
 304   /* The flag code.  */
 305   unsigned code;
 306
 307   /* The number of bits in the operand.  */
 308   unsigned int bits;
 309
 310   /* How far the operand is left shifted in the instruction.  */
 311   unsigned int shift;
 312
 313   /* Available for disassembler.  */
 314   unsigned char favail;
 315 };
 316
 317 /* The flag operands table.  */
 318 extern const struct arc_flag_operand arc_flag_operands[];
 319 extern const unsigned arc_num_flag_operands;
 320
 321 /* The flag's class structure.  */
 322 struct arc_flag_class
 323 {
 324   /* Flag class.  */
 325   flag_class_t class;
 326
 327   /* List of valid flags (codes).  */
 328   unsigned flags[256];
 329 };
 330
 331 extern const struct arc_flag_class arc_flag_classes[];
 332
 333 /* Structure for special cases.  */
 334 struct arc_flag_special
 335 {
 336   /* Name of special case instruction.  */
 337   const char *name;
 338
 339   /* List of flags applicable for special case instruction.  */
 340   unsigned flags[32];
 341 };
 342
 343 extern const struct arc_flag_special arc_flag_special_cases[];
 344 extern const unsigned arc_num_flag_special;
 345
 346 /* Relocation equivalence structure.  */
 347 struct arc_reloc_equiv_tab
 348 {
 349   const char * name;       /* String to lookup.  */
 350   const char * mnemonic;   /* Extra matching condition.  */
 351   unsigned     flags[32];  /* Extra matching condition.  */
 352   signed int   oldreloc;   /* Old relocation.  */
 353   signed int   newreloc;   /* New relocation.  */
 354 };
 355
 356 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 357 extern const unsigned arc_num_equiv_tab;
 358
 359 /* Structure for operand operations for pseudo/alias instructions.  */
 360 struct arc_operand_operation
 361 {
 362   /* The index for operand from operand array.  */
 363   unsigned operand_idx;
 364
 365   /* Defines if it needs the operand inserted by the assembler or
 366      whether this operand comes from the pseudo instruction's
 367      operands.  */
 368   unsigned char needs_insert;
 369
 370   /* Count we have to add to the operand.  Use negative number to
 371      subtract from the operand.  Also use this number to add to 0 if
 372      the operand needs to be inserted (i.e. needs_insert == 1).  */
 373   int count;
 374
 375   /* Index of the operand to swap with.  To be done AFTER applying
 376      inc_count.  */
 377   unsigned swap_operand_idx;
 378 };
 379
 380 /* Structure for pseudo/alias instructions.  */
 381 struct arc_pseudo_insn
 382 {
 383   /* Mnemonic for pseudo/alias insn.  */
 384   const char *mnemonic_p;
 385
 386   /* Mnemonic for real instruction.  */
 387   const char *mnemonic_r;
 388
 389   /* Flag that will have to be added (if any).  */
 390   const char *flag_r;
 391
 392   /* Amount of operands.  */
 393   unsigned operand_cnt;
 394
 395   /* Array of operand operations.  */
 396   struct arc_operand_operation operand[6];
 397 };
 398
 399 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 400 extern const unsigned arc_num_pseudo_insn;
 401
 402 /* Structure for AUXILIARY registers.  */
 403 struct arc_aux_reg
 404 {
 405   /* Register address.  */
 406   int address;
 407
 408  /* Register name.  */
 409   const char *name;
 410
 411   /* Size of the string.  */
 412   size_t length;
 413 };
 414
 415 extern const struct arc_aux_reg arc_aux_regs[];
 416 extern const unsigned arc_num_aux_regs;
 417
 418 extern const struct arc_opcode arc_relax_opcodes[];
 419 extern const unsigned arc_num_relax_opcodes;
 420
 421 #endif /* OPCODE_ARC_H */