include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #ifndef MAX_INSN_ARGS
  32 #define MAX_INSN_ARGS        16
  33 #endif
  34
  35 #ifndef MAX_INSN_FLGS
  36 #define MAX_INSN_FLGS        4
  37 #endif
  38
  39 /* Instruction Class.  */
  40 typedef enum
  41 {
  42   ACL,
  43   ARITH,
  44   AUXREG,
  45   BBIT0,
  46   BBIT1,
  47   BI,
  48   BIH,
  49   BITOP,
  50   BITSTREAM,
  51   BMU,
  52   BRANCH,
  53   BRCC,
  54   CONTROL,
  55   DIVREM,
  56   DMA,
  57   DPI,
  58   DSP,
  59   EI,
  60   ENTER,
  61   FLOAT,
  62   INVALID,
  63   JLI,
  64   JUMP,
  65   KERNEL,
  66   LEAVE,
  67   LOAD,
  68   LOGICAL,
  69   LOOP,
  70   MEMORY,
  71   MISC,
  72   MOVE,
  73   MPY,
  74   NET,
  75   PROTOCOL_DECODE,
  76   PMU,
  77   POP,
  78   PUSH,
  79   SJLI,
  80   STORE,
  81   SUB,
  82   ULTRAIP,
  83   XY
  84 } insn_class_t;
  85
  86 /* Instruction Subclass.  */
  87 typedef enum
  88 {
  89   NONE     = 0,
  90   CVT      = (1U << 1),
  91   BTSCN    = (1U << 2),
  92   CD       = (1U << 3),
  93   CD1      = CD,
  94   CD2      = CD,
  95   COND     = (1U << 4),
  96   DIV      = (1U << 5),
  97   DP       = (1U << 6),
  98   DPA      = (1U << 7),
  99   DPX      = (1U << 8),
 100   LL64     = (1U << 9),
 101   MPY1E    = (1U << 10),
 102   MPY6E    = (1U << 11),
 103   MPY7E    = (1U << 12),
 104   MPY8E    = (1U << 13),
 105   MPY9E    = (1U << 14),
 106   NPS400   = (1U << 15),
 107   QUARKSE1 = (1U << 16),
 108   QUARKSE2 = (1U << 17),
 109   SHFT1    = (1U << 18),
 110   SHFT2    = (1U << 19),
 111   SWAP     = (1U << 20),
 112   SP       = (1U << 21),
 113   SPX      = (1U << 22)
 114 } insn_subclass_t;
 115
 116 /* Flags class.  */
 117 typedef enum
 118 {
 119   F_CLASS_NONE = 0,
 120
 121   /* At most one flag from the set of flags can appear in the
 122      instruction.  */
 123   F_CLASS_OPTIONAL = (1 << 0),
 124
 125   /* Exactly one from from the set of flags must appear in the
 126      instruction.  */
 127   F_CLASS_REQUIRED = (1 << 1),
 128
 129   /* The conditional code can be extended over the standard variants
 130      via .extCondCode pseudo-op.  */
 131   F_CLASS_EXTEND = (1 << 2),
 132
 133   /* Condition code flag.  */
 134   F_CLASS_COND = (1 << 3),
 135
 136   /* Write back mode.  */
 137   F_CLASS_WB = (1 << 4),
 138
 139   /* Data size.  */
 140   F_CLASS_ZZ = (1 << 5),
 141
 142   /* Implicit flag.  */
 143   F_CLASS_IMPLICIT = (1 << 6)
 144 } flag_class_t;
 145
 146 /* The opcode table is an array of struct arc_opcode.  */
 147 struct arc_opcode
 148 {
 149   /* The opcode name.  */
 150   const char * name;
 151
 152   /* The opcode itself.  Those bits which will be filled in with
 153      operands are zeroes.  */
 154   unsigned long long opcode;
 155
 156   /* The opcode mask.  This is used by the disassembler.  This is a
 157      mask containing ones indicating those bits which must match the
 158      opcode field, and zeroes indicating those bits which need not
 159      match (and are presumably filled in by operands).  */
 160   unsigned long long mask;
 161
 162   /* One bit flags for the opcode.  These are primarily used to
 163      indicate specific processors and environments support the
 164      instructions.  The defined values are listed below.  */
 165   unsigned cpu;
 166
 167   /* The instruction class.  This is used by gdb.  */
 168   insn_class_t insn_class;
 169
 170   /* The instruction subclass.  */
 171   insn_subclass_t subclass;
 172
 173   /* An array of operand codes.  Each code is an index into the
 174      operand table.  They appear in the order which the operands must
 175      appear in assembly code, and are terminated by a zero.  */
 176   unsigned char operands[MAX_INSN_ARGS + 1];
 177
 178   /* An array of flag codes.  Each code is an index into the flag
 179      table.  They appear in the order which the flags must appear in
 180      assembly code, and are terminated by a zero.  */
 181   unsigned char flags[MAX_INSN_FLGS + 1];
 182 };
 183
 184 /* The table itself is sorted by major opcode number, and is otherwise
 185    in the order in which the disassembler should consider
 186    instructions.  */
 187 extern const struct arc_opcode arc_opcodes[];
 188
 189 /* Return length of an instruction represented by OPCODE, in bytes.  */
 190 extern int arc_opcode_len (const struct arc_opcode *opcode);
 191
 192 /* CPU Availability.  */
 193 #define ARC_OPCODE_NONE     0x0000
 194 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 195 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 196 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 197 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 198
 199 /* CPU combi.  */
 200 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 201                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 202 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 203 #define ARC_OPCODE_ARCV1   (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700)
 204 #define ARC_OPCODE_ARCV2   (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 205 #define ARC_OPCODE_ARCMPY6E  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
 206
 207 /* The operands table is an array of struct arc_operand.  */
 208 struct arc_operand
 209 {
 210   /* The number of bits in the operand.  */
 211   unsigned int bits;
 212
 213   /* How far the operand is left shifted in the instruction.  */
 214   unsigned int shift;
 215
 216   /* The default relocation type for this operand.  */
 217   signed int default_reloc;
 218
 219   /* One bit syntax flags.  */
 220   unsigned int flags;
 221
 222   /* Insertion function.  This is used by the assembler.  To insert an
 223      operand value into an instruction, check this field.
 224
 225      If it is NULL, execute
 226          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 227      (i is the instruction which we are filling in, o is a pointer to
 228      this structure, and op is the opcode value; this assumes twos
 229      complement arithmetic).
 230
 231      If this field is not NULL, then simply call it with the
 232      instruction and the operand value.  It will return the new value
 233      of the instruction.  If the ERRMSG argument is not NULL, then if
 234      the operand value is illegal, *ERRMSG will be set to a warning
 235      string (the operand will be inserted in any case).  If the
 236      operand value is legal, *ERRMSG will be unchanged (most operands
 237      can accept any value).  */
 238   unsigned long long (*insert) (unsigned long long instruction,
 239                                 long long int op,
 240                                 const char **errmsg);
 241
 242   /* Extraction function.  This is used by the disassembler.  To
 243      extract this operand type from an instruction, check this field.
 244
 245      If it is NULL, compute
 246          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 247          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 248              && (op & (1 << (o->bits - 1))) != 0)
 249            op -= 1 << o->bits;
 250      (i is the instruction, o is a pointer to this structure, and op
 251      is the result; this assumes twos complement arithmetic).
 252
 253      If this field is not NULL, then simply call it with the
 254      instruction value.  It will return the value of the operand.  If
 255      the INVALID argument is not NULL, *INVALID will be set to
 256      TRUE if this operand type can not actually be extracted from
 257      this operand (i.e., the instruction does not match).  If the
 258      operand is valid, *INVALID will not be changed.  */
 259   long long int (*extract) (unsigned long long instruction,
 260                             bfd_boolean *invalid);
 261 };
 262
 263 /* Elements in the table are retrieved by indexing with values from
 264    the operands field of the arc_opcodes table.  */
 265 extern const struct arc_operand arc_operands[];
 266 extern const unsigned arc_num_operands;
 267 extern const unsigned arc_Toperand;
 268 extern const unsigned arc_NToperand;
 269
 270 /* Values defined for the flags field of a struct arc_operand.  */
 271
 272 /* This operand does not actually exist in the assembler input.  This
 273    is used to support extended mnemonics, for which two operands fields
 274    are identical.  The assembler should call the insert function with
 275    any op value.  The disassembler should call the extract function,
 276    ignore the return value, and check the value placed in the invalid
 277    argument.  */
 278 #define ARC_OPERAND_FAKE        0x0001
 279
 280 /* This operand names an integer register.  */
 281 #define ARC_OPERAND_IR          0x0002
 282
 283 /* This operand takes signed values.  */
 284 #define ARC_OPERAND_SIGNED      0x0004
 285
 286 /* This operand takes unsigned values.  This exists primarily so that
 287    a flags value of 0 can be treated as end-of-arguments.  */
 288 #define ARC_OPERAND_UNSIGNED    0x0008
 289
 290 /* This operand takes long immediate values.  */
 291 #define ARC_OPERAND_LIMM        0x0010
 292
 293 /* This operand is identical like the previous one.  */
 294 #define ARC_OPERAND_DUPLICATE   0x0020
 295
 296 /* This operand is PC relative.  Used for internal relocs.  */
 297 #define ARC_OPERAND_PCREL       0x0040
 298
 299 /* This operand is truncated.  The truncation is done accordingly to
 300    operand alignment attribute.  */
 301 #define ARC_OPERAND_TRUNCATE    0x0080
 302
 303 /* This operand is 16bit aligned.  */
 304 #define ARC_OPERAND_ALIGNED16   0x0100
 305
 306 /* This operand is 32bit aligned.  */
 307 #define ARC_OPERAND_ALIGNED32   0x0200
 308
 309 /* This operand can be ignored by matching process if it is not
 310    present.  */
 311 #define ARC_OPERAND_IGNORE      0x0400
 312
 313 /* Don't check the range when matching.  */
 314 #define ARC_OPERAND_NCHK        0x0800
 315
 316 /* Mark the braket possition.  */
 317 #define ARC_OPERAND_BRAKET      0x1000
 318
 319 /* Address type operand for NPS400.  */
 320 #define ARC_OPERAND_ADDRTYPE    0x2000
 321
 322 /* Mark the colon position.  */
 323 #define ARC_OPERAND_COLON       0x4000
 324
 325 /* Mask for selecting the type for typecheck purposes.  */
 326 #define ARC_OPERAND_TYPECHECK_MASK               \
 327   (ARC_OPERAND_IR                                \
 328    | ARC_OPERAND_LIMM     | ARC_OPERAND_SIGNED   \
 329    | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET   \
 330    | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
 331
 332 /* Macro to determine if an operand is a fake operand.  */
 333 #define ARC_OPERAND_IS_FAKE(op)                     \
 334   ((operand->flags & ARC_OPERAND_FAKE)              \
 335    && !((operand->flags & ARC_OPERAND_BRAKET)       \
 336         || (operand->flags & ARC_OPERAND_COLON)))
 337
 338 /* The flags structure.  */
 339 struct arc_flag_operand
 340 {
 341   /* The flag name.  */
 342   const char * name;
 343
 344   /* The flag code.  */
 345   unsigned code;
 346
 347   /* The number of bits in the operand.  */
 348   unsigned int bits;
 349
 350   /* How far the operand is left shifted in the instruction.  */
 351   unsigned int shift;
 352
 353   /* Available for disassembler.  */
 354   unsigned char favail;
 355 };
 356
 357 /* The flag operands table.  */
 358 extern const struct arc_flag_operand arc_flag_operands[];
 359 extern const unsigned arc_num_flag_operands;
 360
 361 /* The flag's class structure.  */
 362 struct arc_flag_class
 363 {
 364   /* Flag class.  */
 365   flag_class_t flag_class;
 366
 367   /* List of valid flags (codes).  */
 368   unsigned flags[256];
 369 };
 370
 371 extern const struct arc_flag_class arc_flag_classes[];
 372
 373 /* Structure for special cases.  */
 374 struct arc_flag_special
 375 {
 376   /* Name of special case instruction.  */
 377   const char *name;
 378
 379   /* List of flags applicable for special case instruction.  */
 380   unsigned flags[32];
 381 };
 382
 383 extern const struct arc_flag_special arc_flag_special_cases[];
 384 extern const unsigned arc_num_flag_special;
 385
 386 /* Relocation equivalence structure.  */
 387 struct arc_reloc_equiv_tab
 388 {
 389   const char * name;       /* String to lookup.  */
 390   const char * mnemonic;   /* Extra matching condition.  */
 391   unsigned     flags[32];  /* Extra matching condition.  */
 392   signed int   oldreloc;   /* Old relocation.  */
 393   signed int   newreloc;   /* New relocation.  */
 394 };
 395
 396 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 397 extern const unsigned arc_num_equiv_tab;
 398
 399 /* Structure for operand operations for pseudo/alias instructions.  */
 400 struct arc_operand_operation
 401 {
 402   /* The index for operand from operand array.  */
 403   unsigned operand_idx;
 404
 405   /* Defines if it needs the operand inserted by the assembler or
 406      whether this operand comes from the pseudo instruction's
 407      operands.  */
 408   unsigned char needs_insert;
 409
 410   /* Count we have to add to the operand.  Use negative number to
 411      subtract from the operand.  Also use this number to add to 0 if
 412      the operand needs to be inserted (i.e. needs_insert == 1).  */
 413   int count;
 414
 415   /* Index of the operand to swap with.  To be done AFTER applying
 416      inc_count.  */
 417   unsigned swap_operand_idx;
 418 };
 419
 420 /* Structure for pseudo/alias instructions.  */
 421 struct arc_pseudo_insn
 422 {
 423   /* Mnemonic for pseudo/alias insn.  */
 424   const char * mnemonic_p;
 425
 426   /* Mnemonic for real instruction.  */
 427   const char * mnemonic_r;
 428
 429   /* Flag that will have to be added (if any).  */
 430   const char * flag_r;
 431
 432   /* Amount of operands.  */
 433   unsigned operand_cnt;
 434
 435   /* Array of operand operations.  */
 436   struct arc_operand_operation operand[6];
 437 };
 438
 439 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 440 extern const unsigned arc_num_pseudo_insn;
 441
 442 /* Structure for AUXILIARY registers.  */
 443 struct arc_aux_reg
 444 {
 445   /* Register address.  */
 446   int address;
 447
 448   /* One bit flags for the opcode.  These are primarily used to
 449      indicate specific processors and environments support the
 450      instructions.  */
 451   unsigned cpu;
 452
 453   /* AUX register subclass.  */
 454   insn_subclass_t subclass;
 455
 456   /* Register name.  */
 457   const char * name;
 458
 459   /* Size of the string.  */
 460   size_t length;
 461 };
 462
 463 extern const struct arc_aux_reg arc_aux_regs[];
 464 extern const unsigned arc_num_aux_regs;
 465
 466 extern const struct arc_opcode arc_relax_opcodes[];
 467 extern const unsigned arc_num_relax_opcodes;
 468
 469 /* Macro used for generating one class of NPS instructions.  */
 470 #define NPS_CMEM_HIGH_VALUE 0x57f0
 471
 472 /* Macros to help generating regular pattern instructions.  */
 473 #define FIELDA(word) (word & 0x3F)
 474 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 475 #define FIELDC(word) ((word & 0x3F) << 6)
 476 #define FIELDF       (0x01 << 15)
 477 #define FIELDQ       (0x1F)
 478
 479 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 480 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 481 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 482
 483 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 484 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 485 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 486 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 487 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 488 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 489 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 490 #define INSN3OP_0LL(MOP,SOP)                                    \
 491   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 492 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 493 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 494 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 495 #define INSN3OP_0LU(MOP,SOP)                                    \
 496   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 497 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 498 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 499 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 500 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 501 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 502 #define INSN3OP_C0LL(MOP,SOP)                                   \
 503   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 504 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 505 #define INSN3OP_C0LU(MOP,SOP)                                   \
 506   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 507
 508 #define MASK_32BIT(VAL) (0xffffffff & (VAL))
 509
 510 #define MINSN3OP_ABC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 511 #define MINSN3OP_ALC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 512 #define MINSN3OP_ABL  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
 513 #define MINSN3OP_ALL  (MASK_32BIT (~(FIELDF | FIELDA (63))))
 514 #define MINSN3OP_0BC  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 515 #define MINSN3OP_0LC  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 516 #define MINSN3OP_0BL  (MASK_32BIT (~(FIELDF | FIELDB (63))))
 517 #define MINSN3OP_0LL  (MASK_32BIT (~(FIELDF)))
 518 #define MINSN3OP_ABU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 519 #define MINSN3OP_ALU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 520 #define MINSN3OP_0BU  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 521 #define MINSN3OP_0LU  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 522 #define MINSN3OP_BBS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 523 #define MINSN3OP_0LS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 524 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 525 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
 526 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 527 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
 528 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 529 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 530
 531 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 532 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 533 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 534 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 535 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 536 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 537
 538 #define MINSN2OP_BC  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 539 #define MINSN2OP_BL  (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
 540 #define MINSN2OP_0C  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 541 #define MINSN2OP_0L  (MASK_32BIT ((~(FIELDF))))
 542 #define MINSN2OP_BU  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 543 #define MINSN2OP_0U  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 544
 545 /* Various constants used when defining an extension instruction.  */
 546 #define ARC_SYNTAX_3OP          (1 << 0)
 547 #define ARC_SYNTAX_2OP          (1 << 1)
 548 #define ARC_SYNTAX_1OP          (1 << 2)
 549 #define ARC_SYNTAX_NOP          (1 << 3)
 550 #define ARC_SYNTAX_MASK         (0x0F)
 551
 552 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 553 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 554
 555 #define ARC_SUFFIX_NONE         (1 << 0)
 556 #define ARC_SUFFIX_COND         (1 << 1)
 557 #define ARC_SUFFIX_FLAG         (1 << 2)
 558
 559 #define ARC_REGISTER_READONLY    (1 << 0)
 560 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 561 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 562
 563 /* Constants needed to initialize extension instructions.  */
 564 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 565 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 566 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 567 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 568
 569 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 570 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 571 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 572 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 573 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 574 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 575 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 576 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 577 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 578 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 579 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 580 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 581
 582 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 583 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 584 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 585
 586 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 587 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 588 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 589
 590 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 591 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 592 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 593 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 594 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 595 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 596
 597 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 598 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 599 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 600 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 601
 602 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 604 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 605
 606 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
 607    Instruction Set Reference Manual v2.4 for a description of address types.  */
 608
 609 typedef enum
 610 {
 611   /* Addresses in memory.  */
 612
 613   /* Buffer descriptor.  */
 614   ARC_NPS400_ADDRTYPE_BD,
 615
 616   /* Job identifier.  */
 617   ARC_NPS400_ADDRTYPE_JID,
 618
 619   /* Linked Buffer Descriptor.  */
 620   ARC_NPS400_ADDRTYPE_LBD,
 621
 622   /* Multicast Buffer Descriptor.  */
 623   ARC_NPS400_ADDRTYPE_MBD,
 624
 625   /* Summarized Address.  */
 626   ARC_NPS400_ADDRTYPE_SD,
 627
 628   /* SMEM Security Context Local Memory.  */
 629   ARC_NPS400_ADDRTYPE_SM,
 630
 631   /* Extended Address.  */
 632   ARC_NPS400_ADDRTYPE_XA,
 633
 634   /* Extended Summarized Address.  */
 635   ARC_NPS400_ADDRTYPE_XD,
 636
 637   /* CMEM offset addresses.  */
 638
 639   /* On-demand Counter Descriptor.  */
 640   ARC_NPS400_ADDRTYPE_CD,
 641
 642   /* CMEM Buffer Descriptor.  */
 643   ARC_NPS400_ADDRTYPE_CBD,
 644
 645   /* CMEM Job Identifier.  */
 646   ARC_NPS400_ADDRTYPE_CJID,
 647
 648   /* CMEM Linked Buffer Descriptor.  */
 649   ARC_NPS400_ADDRTYPE_CLBD,
 650
 651   /* CMEM Offset.  */
 652   ARC_NPS400_ADDRTYPE_CM,
 653
 654   /* CMEM Summarized Address.  */
 655   ARC_NPS400_ADDRTYPE_CSD,
 656
 657   /* CMEM Extended Address.  */
 658   ARC_NPS400_ADDRTYPE_CXA,
 659
 660   /* CMEM Extended Summarized Address.  */
 661   ARC_NPS400_ADDRTYPE_CXD
 662
 663 } arc_nps_address_type;
 664
 665 #define ARC_NUM_ADDRTYPES 16
 666
 667 #ifdef __cplusplus
 668 }
 669 #endif
 670
 671 #endif /* OPCODE_ARC_H */