include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #ifndef MAX_INSN_ARGS
  32 #define MAX_INSN_ARGS        16
  33 #endif
  34
  35 #ifndef MAX_INSN_FLGS
  36 #define MAX_INSN_FLGS        3
  37 #endif
  38
  39 /* Instruction Class.  */
  40 typedef enum
  41 {
  42   ACL,
  43   ARITH,
  44   AUXREG,
  45   BBIT0,
  46   BBIT1,
  47   BI,
  48   BIH,
  49   BITOP,
  50   BITSTREAM,
  51   BMU,
  52   BRANCH,
  53   BRCC,
  54   CONTROL,
  55   DIVREM,
  56   DMA,
  57   DPI,
  58   DSP,
  59   EI,
  60   ENTER,
  61   FLOAT,
  62   INVALID,
  63   JLI,
  64   JUMP,
  65   KERNEL,
  66   LEAVE,
  67   LOAD,
  68   LOGICAL,
  69   LOOP,
  70   MEMORY,
  71   MOVE,
  72   MPY,
  73   NET,
  74   PROTOCOL_DECODE,
  75   PMU,
  76   POP,
  77   PUSH,
  78   STORE,
  79   SUB,
  80   XY
  81 } insn_class_t;
  82
  83 /* Instruction Subclass.  */
  84 typedef enum
  85 {
  86   NONE,
  87   CVT,
  88   BTSCN,
  89   CD1,
  90   CD2,
  91   COND,
  92   DIV,
  93   DP,
  94   DPA,
  95   DPX,
  96   MPY1E,
  97   MPY6E,
  98   MPY7E,
  99   MPY8E,
 100   MPY9E,
 101   NPS400,
 102   QUARKSE,
 103   SHFT1,
 104   SHFT2,
 105   SWAP,
 106   SP,
 107   SPX
 108 } insn_subclass_t;
 109
 110 /* Flags class.  */
 111 typedef enum
 112 {
 113   F_CLASS_NONE = 0,
 114
 115   /* At most one flag from the set of flags can appear in the
 116      instruction.  */
 117   F_CLASS_OPTIONAL = (1 << 0),
 118
 119   /* Exactly one from from the set of flags must appear in the
 120      instruction.  */
 121   F_CLASS_REQUIRED = (1 << 1),
 122
 123   /* The conditional code can be extended over the standard variants
 124      via .extCondCode pseudo-op.  */
 125   F_CLASS_EXTEND = (1 << 2),
 126
 127   /* Condition code flag.  */
 128   F_CLASS_COND = (1 << 3),
 129
 130   /* Write back mode.  */
 131   F_CLASS_WB = (1 << 4),
 132
 133   /* Data size.  */
 134   F_CLASS_ZZ = (1 << 5),
 135
 136   /* Implicit flag.  */
 137   F_CLASS_IMPLICIT = (1 << 6)
 138 } flag_class_t;
 139
 140 /* The opcode table is an array of struct arc_opcode.  */
 141 struct arc_opcode
 142 {
 143   /* The opcode name.  */
 144   const char *name;
 145
 146   /* The opcode itself.  Those bits which will be filled in with
 147      operands are zeroes.  */
 148   unsigned long long opcode;
 149
 150   /* The opcode mask.  This is used by the disassembler.  This is a
 151      mask containing ones indicating those bits which must match the
 152      opcode field, and zeroes indicating those bits which need not
 153      match (and are presumably filled in by operands).  */
 154   unsigned long long mask;
 155
 156   /* One bit flags for the opcode.  These are primarily used to
 157      indicate specific processors and environments support the
 158      instructions.  The defined values are listed below.  */
 159   unsigned cpu;
 160
 161   /* The instruction class.  This is used by gdb.  */
 162   insn_class_t insn_class;
 163
 164   /* The instruction subclass.  */
 165   insn_subclass_t subclass;
 166
 167   /* An array of operand codes.  Each code is an index into the
 168      operand table.  They appear in the order which the operands must
 169      appear in assembly code, and are terminated by a zero.  */
 170   unsigned char operands[MAX_INSN_ARGS + 1];
 171
 172   /* An array of flag codes.  Each code is an index into the flag
 173      table.  They appear in the order which the flags must appear in
 174      assembly code, and are terminated by a zero.  */
 175   unsigned char flags[MAX_INSN_FLGS + 1];
 176 };
 177
 178 /* The table itself is sorted by major opcode number, and is otherwise
 179    in the order in which the disassembler should consider
 180    instructions.  */
 181 extern const struct arc_opcode arc_opcodes[];
 182
 183 /* Return length of an instruction represented by OPCODE, in bytes.  */
 184 extern int arc_opcode_len (const struct arc_opcode *opcode);
 185
 186 /* CPU Availability.  */
 187 #define ARC_OPCODE_NONE     0x0000
 188 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 189 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 190 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 191 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 192
 193 /* CPU combi.  */
 194 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 195                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 196 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 197 #define ARC_OPCODE_ARCV2   (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 198
 199 /* CPU extensions.  */
 200 #define ARC_EA       0x0001
 201 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 202 #define ARC_LLOCK    0x0002
 203 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 204 #define ARC_MPY      0x0004
 205 #define ARC_MULT     0x0004
 206 #define ARC_NPS400   0x0008
 207
 208 /* Floating point support.  */
 209 #define ARC_DPFP     0x0010
 210 #define ARC_SPFP     0x0020
 211 #define ARC_FPU      0x0030
 212 #define ARC_FPUDA    0x0040
 213
 214 /* NORM & SWAP.  */
 215 #define ARC_SWAP     0x0100
 216 #define ARC_NORM     0x0200
 217 #define ARC_BSCAN    0x0200
 218
 219 /* A7 specific.  */
 220 #define ARC_UIX      0x1000
 221 #define ARC_TSTAMP   0x1000
 222
 223 /* A6 specific.  */
 224 #define ARC_VBFDW    0x1000
 225 #define ARC_BARREL   0x1000
 226 #define ARC_DSPA     0x1000
 227
 228 /* EM specific.  */
 229 #define ARC_SHIFT    0x1000
 230
 231 /* V2 specific.  */
 232 #define ARC_INTR     0x1000
 233 #define ARC_DIV      0x1000
 234
 235 /* V1 specific.  */
 236 #define ARC_XMAC     0x1000
 237 #define ARC_CRC      0x1000
 238
 239 /* The operands table is an array of struct arc_operand.  */
 240 struct arc_operand
 241 {
 242   /* The number of bits in the operand.  */
 243   unsigned int bits;
 244
 245   /* How far the operand is left shifted in the instruction.  */
 246   unsigned int shift;
 247
 248   /* The default relocation type for this operand.  */
 249   signed int default_reloc;
 250
 251   /* One bit syntax flags.  */
 252   unsigned int flags;
 253
 254   /* Insertion function.  This is used by the assembler.  To insert an
 255      operand value into an instruction, check this field.
 256
 257      If it is NULL, execute
 258          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 259      (i is the instruction which we are filling in, o is a pointer to
 260      this structure, and op is the opcode value; this assumes twos
 261      complement arithmetic).
 262
 263      If this field is not NULL, then simply call it with the
 264      instruction and the operand value.  It will return the new value
 265      of the instruction.  If the ERRMSG argument is not NULL, then if
 266      the operand value is illegal, *ERRMSG will be set to a warning
 267      string (the operand will be inserted in any case).  If the
 268      operand value is legal, *ERRMSG will be unchanged (most operands
 269      can accept any value).  */
 270   unsigned long long (*insert) (unsigned long long instruction,
 271                                 long long int op,
 272                                 const char **errmsg);
 273
 274   /* Extraction function.  This is used by the disassembler.  To
 275      extract this operand type from an instruction, check this field.
 276
 277      If it is NULL, compute
 278          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 279          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 280              && (op & (1 << (o->bits - 1))) != 0)
 281            op -= 1 << o->bits;
 282      (i is the instruction, o is a pointer to this structure, and op
 283      is the result; this assumes twos complement arithmetic).
 284
 285      If this field is not NULL, then simply call it with the
 286      instruction value.  It will return the value of the operand.  If
 287      the INVALID argument is not NULL, *INVALID will be set to
 288      TRUE if this operand type can not actually be extracted from
 289      this operand (i.e., the instruction does not match).  If the
 290      operand is valid, *INVALID will not be changed.  */
 291   long long int (*extract) (unsigned long long instruction,
 292                             bfd_boolean *invalid);
 293 };
 294
 295 /* Elements in the table are retrieved by indexing with values from
 296    the operands field of the arc_opcodes table.  */
 297 extern const struct arc_operand arc_operands[];
 298 extern const unsigned arc_num_operands;
 299 extern const unsigned arc_Toperand;
 300 extern const unsigned arc_NToperand;
 301
 302 /* Values defined for the flags field of a struct arc_operand.  */
 303
 304 /* This operand does not actually exist in the assembler input.  This
 305    is used to support extended mnemonics, for which two operands fields
 306    are identical.  The assembler should call the insert function with
 307    any op value.  The disassembler should call the extract function,
 308    ignore the return value, and check the value placed in the invalid
 309    argument.  */
 310 #define ARC_OPERAND_FAKE        0x0001
 311
 312 /* This operand names an integer register.  */
 313 #define ARC_OPERAND_IR          0x0002
 314
 315 /* This operand takes signed values.  */
 316 #define ARC_OPERAND_SIGNED      0x0004
 317
 318 /* This operand takes unsigned values.  This exists primarily so that
 319    a flags value of 0 can be treated as end-of-arguments.  */
 320 #define ARC_OPERAND_UNSIGNED    0x0008
 321
 322 /* This operand takes long immediate values.  */
 323 #define ARC_OPERAND_LIMM        0x0010
 324
 325 /* This operand is identical like the previous one.  */
 326 #define ARC_OPERAND_DUPLICATE   0x0020
 327
 328 /* This operand is PC relative.  Used for internal relocs.  */
 329 #define ARC_OPERAND_PCREL       0x0040
 330
 331 /* This operand is truncated.  The truncation is done accordingly to
 332    operand alignment attribute.  */
 333 #define ARC_OPERAND_TRUNCATE    0x0080
 334
 335 /* This operand is 16bit aligned.  */
 336 #define ARC_OPERAND_ALIGNED16   0x0100
 337
 338 /* This operand is 32bit aligned.  */
 339 #define ARC_OPERAND_ALIGNED32   0x0200
 340
 341 /* This operand can be ignored by matching process if it is not
 342    present.  */
 343 #define ARC_OPERAND_IGNORE      0x0400
 344
 345 /* Don't check the range when matching.  */
 346 #define ARC_OPERAND_NCHK        0x0800
 347
 348 /* Mark the braket possition.  */
 349 #define ARC_OPERAND_BRAKET      0x1000
 350
 351 /* Address type operand for NPS400.  */
 352 #define ARC_OPERAND_ADDRTYPE    0x2000
 353
 354 /* Mark the colon position.  */
 355 #define ARC_OPERAND_COLON       0x4000
 356
 357 /* Mask for selecting the type for typecheck purposes.  */
 358 #define ARC_OPERAND_TYPECHECK_MASK               \
 359   (ARC_OPERAND_IR                                \
 360    | ARC_OPERAND_LIMM     | ARC_OPERAND_SIGNED   \
 361    | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET   \
 362    | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
 363
 364 /* Macro to determine if an operand is a fake operand.  */
 365 #define ARC_OPERAND_IS_FAKE(op)                     \
 366   ((operand->flags & ARC_OPERAND_FAKE)              \
 367    && !((operand->flags & ARC_OPERAND_BRAKET)       \
 368         || (operand->flags & ARC_OPERAND_COLON)))
 369
 370 /* The flags structure.  */
 371 struct arc_flag_operand
 372 {
 373   /* The flag name.  */
 374   const char *name;
 375
 376   /* The flag code.  */
 377   unsigned code;
 378
 379   /* The number of bits in the operand.  */
 380   unsigned int bits;
 381
 382   /* How far the operand is left shifted in the instruction.  */
 383   unsigned int shift;
 384
 385   /* Available for disassembler.  */
 386   unsigned char favail;
 387 };
 388
 389 /* The flag operands table.  */
 390 extern const struct arc_flag_operand arc_flag_operands[];
 391 extern const unsigned arc_num_flag_operands;
 392
 393 /* The flag's class structure.  */
 394 struct arc_flag_class
 395 {
 396   /* Flag class.  */
 397   flag_class_t flag_class;
 398
 399   /* List of valid flags (codes).  */
 400   unsigned flags[256];
 401 };
 402
 403 extern const struct arc_flag_class arc_flag_classes[];
 404
 405 /* Structure for special cases.  */
 406 struct arc_flag_special
 407 {
 408   /* Name of special case instruction.  */
 409   const char *name;
 410
 411   /* List of flags applicable for special case instruction.  */
 412   unsigned flags[32];
 413 };
 414
 415 extern const struct arc_flag_special arc_flag_special_cases[];
 416 extern const unsigned arc_num_flag_special;
 417
 418 /* Relocation equivalence structure.  */
 419 struct arc_reloc_equiv_tab
 420 {
 421   const char * name;       /* String to lookup.  */
 422   const char * mnemonic;   /* Extra matching condition.  */
 423   unsigned     flags[32];  /* Extra matching condition.  */
 424   signed int   oldreloc;   /* Old relocation.  */
 425   signed int   newreloc;   /* New relocation.  */
 426 };
 427
 428 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 429 extern const unsigned arc_num_equiv_tab;
 430
 431 /* Structure for operand operations for pseudo/alias instructions.  */
 432 struct arc_operand_operation
 433 {
 434   /* The index for operand from operand array.  */
 435   unsigned operand_idx;
 436
 437   /* Defines if it needs the operand inserted by the assembler or
 438      whether this operand comes from the pseudo instruction's
 439      operands.  */
 440   unsigned char needs_insert;
 441
 442   /* Count we have to add to the operand.  Use negative number to
 443      subtract from the operand.  Also use this number to add to 0 if
 444      the operand needs to be inserted (i.e. needs_insert == 1).  */
 445   int count;
 446
 447   /* Index of the operand to swap with.  To be done AFTER applying
 448      inc_count.  */
 449   unsigned swap_operand_idx;
 450 };
 451
 452 /* Structure for pseudo/alias instructions.  */
 453 struct arc_pseudo_insn
 454 {
 455   /* Mnemonic for pseudo/alias insn.  */
 456   const char *mnemonic_p;
 457
 458   /* Mnemonic for real instruction.  */
 459   const char *mnemonic_r;
 460
 461   /* Flag that will have to be added (if any).  */
 462   const char *flag_r;
 463
 464   /* Amount of operands.  */
 465   unsigned operand_cnt;
 466
 467   /* Array of operand operations.  */
 468   struct arc_operand_operation operand[6];
 469 };
 470
 471 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 472 extern const unsigned arc_num_pseudo_insn;
 473
 474 /* Structure for AUXILIARY registers.  */
 475 struct arc_aux_reg
 476 {
 477   /* Register address.  */
 478   int address;
 479
 480   /* One bit flags for the opcode.  These are primarily used to
 481      indicate specific processors and environments support the
 482      instructions.  */
 483   unsigned cpu;
 484
 485   /* AUX register subclass.  */
 486   insn_subclass_t subclass;
 487
 488   /* Register name.  */
 489   const char *name;
 490
 491   /* Size of the string.  */
 492   size_t length;
 493 };
 494
 495 extern const struct arc_aux_reg arc_aux_regs[];
 496 extern const unsigned arc_num_aux_regs;
 497
 498 extern const struct arc_opcode arc_relax_opcodes[];
 499 extern const unsigned arc_num_relax_opcodes;
 500
 501 /* Macro used for generating one class of NPS instructions.  */
 502 #define NPS_CMEM_HIGH_VALUE 0x57f0
 503
 504 /* Macros to help generating regular pattern instructions.  */
 505 #define FIELDA(word) (word & 0x3F)
 506 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 507 #define FIELDC(word) ((word & 0x3F) << 6)
 508 #define FIELDF       (0x01 << 15)
 509 #define FIELDQ       (0x1F)
 510
 511 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 512 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 513 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 514
 515 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 516 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 517 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 518 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 519 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 520 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 521 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 522 #define INSN3OP_0LL(MOP,SOP)                                    \
 523   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 524 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 525 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 526 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 527 #define INSN3OP_0LU(MOP,SOP)                                    \
 528   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 529 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 530 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 531 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 532 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 533 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 534 #define INSN3OP_C0LL(MOP,SOP)                                   \
 535   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 536 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 537 #define INSN3OP_C0LU(MOP,SOP)                                   \
 538   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 539
 540 #define MASK_32BIT(VAL) (0xffffffff & (VAL))
 541
 542 #define MINSN3OP_ABC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 543 #define MINSN3OP_ALC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 544 #define MINSN3OP_ABL  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
 545 #define MINSN3OP_ALL  (MASK_32BIT (~(FIELDF | FIELDA (63))))
 546 #define MINSN3OP_0BC  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 547 #define MINSN3OP_0LC  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 548 #define MINSN3OP_0BL  (MASK_32BIT (~(FIELDF | FIELDB (63))))
 549 #define MINSN3OP_0LL  (MASK_32BIT (~(FIELDF)))
 550 #define MINSN3OP_ABU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 551 #define MINSN3OP_ALU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 552 #define MINSN3OP_0BU  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 553 #define MINSN3OP_0LU  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 554 #define MINSN3OP_BBS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 555 #define MINSN3OP_0LS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 556 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 557 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
 558 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 559 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
 560 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 561 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 562
 563 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 564 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 565 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 566 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 567 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 568 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 569
 570 #define MINSN2OP_BC  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 571 #define MINSN2OP_BL  (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
 572 #define MINSN2OP_0C  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 573 #define MINSN2OP_0L  (MASK_32BIT ((~(FIELDF))))
 574 #define MINSN2OP_BU  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 575 #define MINSN2OP_0U  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 576
 577 /* Various constants used when defining an extension instruction.  */
 578 #define ARC_SYNTAX_3OP          (1 << 0)
 579 #define ARC_SYNTAX_2OP          (1 << 1)
 580 #define ARC_SYNTAX_1OP          (1 << 2)
 581 #define ARC_SYNTAX_NOP          (1 << 3)
 582 #define ARC_SYNTAX_MASK         (0x0F)
 583
 584 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 585 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 586
 587 #define ARC_SUFFIX_NONE         (1 << 0)
 588 #define ARC_SUFFIX_COND         (1 << 1)
 589 #define ARC_SUFFIX_FLAG         (1 << 2)
 590
 591 #define ARC_REGISTER_READONLY    (1 << 0)
 592 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 593 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 594
 595 /* Constants needed to initialize extension instructions.  */
 596 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 597 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 598 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 599 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 600
 601 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 602 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 604 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 605 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 606 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 607 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 608 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 609 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 610 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 611 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 612 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 613
 614 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 615 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 616 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 617
 618 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 619 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 620 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 621
 622 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 623 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 624 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 625 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 626 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 627 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 628
 629 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 630 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 631 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 632 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 633
 634 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 635 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 636 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 637
 638 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
 639    Instruction Set Reference Manual v2.4 for a description of address types.  */
 640
 641 typedef enum
 642 {
 643   /* Addresses in memory.  */
 644
 645   /* Buffer descriptor.  */
 646   ARC_NPS400_ADDRTYPE_BD,
 647
 648   /* Job identifier.  */
 649   ARC_NPS400_ADDRTYPE_JID,
 650
 651   /* Linked Buffer Descriptor.  */
 652   ARC_NPS400_ADDRTYPE_LBD,
 653
 654   /* Multicast Buffer Descriptor.  */
 655   ARC_NPS400_ADDRTYPE_MBD,
 656
 657   /* Summarized Address.  */
 658   ARC_NPS400_ADDRTYPE_SD,
 659
 660   /* SMEM Security Context Local Memory.  */
 661   ARC_NPS400_ADDRTYPE_SM,
 662
 663   /* Extended Address.  */
 664   ARC_NPS400_ADDRTYPE_XA,
 665
 666   /* Extended Summarized Address.  */
 667   ARC_NPS400_ADDRTYPE_XD,
 668
 669   /* CMEM offset addresses.  */
 670
 671   /* On-demand Counter Descriptor.  */
 672   ARC_NPS400_ADDRTYPE_CD,
 673
 674   /* CMEM Buffer Descriptor.  */
 675   ARC_NPS400_ADDRTYPE_CBD,
 676
 677   /* CMEM Job Identifier.  */
 678   ARC_NPS400_ADDRTYPE_CJID,
 679
 680   /* CMEM Linked Buffer Descriptor.  */
 681   ARC_NPS400_ADDRTYPE_CLBD,
 682
 683   /* CMEM Offset.  */
 684   ARC_NPS400_ADDRTYPE_CM,
 685
 686   /* CMEM Summarized Address.  */
 687   ARC_NPS400_ADDRTYPE_CSD,
 688
 689   /* CMEM Extended Address.  */
 690   ARC_NPS400_ADDRTYPE_CXA,
 691
 692   /* CMEM Extended Summarized Address.  */
 693   ARC_NPS400_ADDRTYPE_CXD
 694
 695 } arc_nps_address_type;
 696
 697 #define ARC_NUM_ADDRTYPES 16
 698
 699 #ifdef __cplusplus
 700 }
 701 #endif
 702
 703 #endif /* OPCODE_ARC_H */