include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifndef MAX_INSN_ARGS
  28 #define MAX_INSN_ARGS        6
  29 #endif
  30
  31 #ifndef MAX_INSN_FLGS
  32 #define MAX_INSN_FLGS        3
  33 #endif
  34
  35 /* Instruction Class.  */
  36 typedef enum
  37   {
  38     ARITH,
  39     AUXREG,
  40     BRANCH,
  41     CONTROL,
  42     DSP,
  43     FLOAT,
  44     INVALID,
  45     JUMP,
  46     KERNEL,
  47     LOGICAL,
  48     MEMORY,
  49   } insn_class_t;
  50
  51 /* Instruction Subclass.  */
  52 typedef enum
  53   {
  54     NONE,
  55     CVT,
  56     BTSCN,
  57     CD1,
  58     CD2,
  59     DIV,
  60     DP,
  61     MPY1E,
  62     MPY6E,
  63     MPY7E,
  64     MPY8E,
  65     MPY9E,
  66     SHFT1,
  67     SHFT2,
  68     SWAP,
  69     SP
  70   } insn_subclass_t;
  71
  72 /* Flags class.  */
  73 typedef enum
  74   {
  75     FNONE,
  76     CND,  /* Conditional flags.  */
  77     WBM,  /* Write-back modes.  */
  78     FLG,  /* F Flag.  */
  79     SBP,  /* Static branch prediction.  */
  80     DLY,  /* Delay slot.  */
  81     DIF,  /* Bypass caches.  */
  82     SGX,  /* Sign extend modes.  */
  83     SZM   /* Data size modes.  */
  84   } flag_class_t;
  85
  86 /* The opcode table is an array of struct arc_opcode.  */
  87 struct arc_opcode
  88 {
  89   /* The opcode name.  */
  90   const char *name;
  91
  92   /* The opcode itself.  Those bits which will be filled in with
  93      operands are zeroes.  */
  94   unsigned opcode;
  95
  96   /* The opcode mask.  This is used by the disassembler.  This is a
  97      mask containing ones indicating those bits which must match the
  98      opcode field, and zeroes indicating those bits which need not
  99      match (and are presumably filled in by operands).  */
 100   unsigned mask;
 101
 102   /* One bit flags for the opcode.  These are primarily used to
 103      indicate specific processors and environments support the
 104      instructions.  The defined values are listed below.  */
 105   unsigned cpu;
 106
 107   /* The instruction class.  This is used by gdb.  */
 108   insn_class_t class;
 109
 110   /* The instruction subclass.  */
 111   insn_subclass_t subclass;
 112
 113   /* An array of operand codes.  Each code is an index into the
 114      operand table.  They appear in the order which the operands must
 115      appear in assembly code, and are terminated by a zero.  */
 116   unsigned char operands[MAX_INSN_ARGS + 1];
 117
 118   /* An array of flag codes.  Each code is an index into the flag
 119      table.  They appear in the order which the flags must appear in
 120      assembly code, and are terminated by a zero.  */
 121   unsigned char flags[MAX_INSN_FLGS + 1];
 122 };
 123
 124 /* The table itself is sorted by major opcode number, and is otherwise
 125    in the order in which the disassembler should consider
 126    instructions.  */
 127 extern const struct arc_opcode arc_opcodes[];
 128 extern const unsigned arc_num_opcodes;
 129
 130 /* CPU Availability.  */
 131 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 132 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 133 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 134 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 135 #define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */
 136
 137 /* CPU extensions.  */
 138 #define ARC_EA       0x0001
 139 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 140 #define ARC_LLOCK    0x0002
 141 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 142 #define ARC_MPY      0x0004
 143 #define ARC_MULT     0x0004
 144
 145 /* Floating point support.  */
 146 #define ARC_DPFP     0x0010
 147 #define ARC_SPFP     0x0020
 148 #define ARC_FPU      0x0030
 149
 150 /* NORM & SWAP.  */
 151 #define ARC_SWAP     0x0100
 152 #define ARC_NORM     0x0200
 153 #define ARC_BSCAN    0x0200
 154
 155 /* A7 specific.  */
 156 #define ARC_UIX      0x1000
 157 #define ARC_TSTAMP   0x1000
 158
 159 /* A6 specific.  */
 160 #define ARC_VBFDW    0x1000
 161 #define ARC_BARREL   0x1000
 162 #define ARC_DSPA     0x1000
 163
 164 /* EM specific.  */
 165 #define ARC_SHIFT    0x1000
 166
 167 /* V2 specific.  */
 168 #define ARC_INTR     0x1000
 169 #define ARC_DIV      0x1000
 170
 171 /* V1 specific.  */
 172 #define ARC_XMAC     0x1000
 173 #define ARC_CRC      0x1000
 174
 175 /* A macro to check for short instructions.  */
 176 #define ARC_SHORT(mask)                         \
 177   (((mask) & 0xFFFF0000) ? 0 : 1)
 178
 179 /* The operands table is an array of struct arc_operand.  */
 180 struct arc_operand
 181 {
 182   /* The number of bits in the operand.  */
 183   unsigned int bits;
 184
 185   /* How far the operand is left shifted in the instruction.  */
 186   unsigned int shift;
 187
 188   /* The default relocation type for this operand.  */
 189   signed int default_reloc;
 190
 191   /* One bit syntax flags.  */
 192   unsigned int flags;
 193
 194   /* Insertion function.  This is used by the assembler.  To insert an
 195      operand value into an instruction, check this field.
 196
 197      If it is NULL, execute
 198          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 199      (i is the instruction which we are filling in, o is a pointer to
 200      this structure, and op is the opcode value; this assumes twos
 201      complement arithmetic).
 202
 203      If this field is not NULL, then simply call it with the
 204      instruction and the operand value.  It will return the new value
 205      of the instruction.  If the ERRMSG argument is not NULL, then if
 206      the operand value is illegal, *ERRMSG will be set to a warning
 207      string (the operand will be inserted in any case).  If the
 208      operand value is legal, *ERRMSG will be unchanged (most operands
 209      can accept any value).  */
 210   unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
 211
 212   /* Extraction function.  This is used by the disassembler.  To
 213      extract this operand type from an instruction, check this field.
 214
 215      If it is NULL, compute
 216          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 217          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 218              && (op & (1 << (o->bits - 1))) != 0)
 219            op -= 1 << o->bits;
 220      (i is the instruction, o is a pointer to this structure, and op
 221      is the result; this assumes twos complement arithmetic).
 222
 223      If this field is not NULL, then simply call it with the
 224      instruction value.  It will return the value of the operand.  If
 225      the INVALID argument is not NULL, *INVALID will be set to
 226      TRUE if this operand type can not actually be extracted from
 227      this operand (i.e., the instruction does not match).  If the
 228      operand is valid, *INVALID will not be changed.  */
 229   int (*extract) (unsigned instruction, bfd_boolean *invalid);
 230 };
 231
 232 /* Elements in the table are retrieved by indexing with values from
 233    the operands field of the arc_opcodes table.  */
 234 extern const struct arc_operand arc_operands[];
 235 extern const unsigned arc_num_operands;
 236 extern const unsigned arc_Toperand;
 237 extern const unsigned arc_NToperand;
 238
 239 /* Values defined for the flags field of a struct arc_operand.  */
 240
 241 /* This operand does not actually exist in the assembler input.  This
 242    is used to support extended mnemonics, for which two operands fields
 243    are identical.  The assembler should call the insert function with
 244    any op value.  The disassembler should call the extract function,
 245    ignore the return value, and check the value placed in the invalid
 246    argument.  */
 247 #define ARC_OPERAND_FAKE        0x0001
 248
 249 /* This operand names an integer register.  */
 250 #define ARC_OPERAND_IR          0x0002
 251
 252 /* This operand takes signed values.  */
 253 #define ARC_OPERAND_SIGNED      0x0004
 254
 255 /* This operand takes unsigned values.  This exists primarily so that
 256    a flags value of 0 can be treated as end-of-arguments.  */
 257 #define ARC_OPERAND_UNSIGNED    0x0008
 258
 259 /* This operand takes long immediate values.  */
 260 #define ARC_OPERAND_LIMM        0x0010
 261
 262 /* This operand is identical like the previous one.  */
 263 #define ARC_OPERAND_DUPLICATE   0x0020
 264
 265 /* This operand is PC relative.  Used for internal relocs.  */
 266 #define ARC_OPERAND_PCREL       0x0040
 267
 268 /* This operand is truncated.  The truncation is done accordingly to
 269    operand alignment attribute.  */
 270 #define ARC_OPERAND_TRUNCATE    0x0080
 271
 272 /* This operand is 16bit aligned.  */
 273 #define ARC_OPERAND_ALIGNED16   0x0100
 274
 275 /* This operand is 32bit aligned.  */
 276 #define ARC_OPERAND_ALIGNED32   0x0200
 277
 278 /* This operand can be ignored by matching process if it is not
 279    present.  */
 280 #define ARC_OPERAND_IGNORE      0x0400
 281
 282 /* Don't check the range when matching.  */
 283 #define ARC_OPERAND_NCHK        0x0800
 284
 285 /* Mark the braket possition.  */
 286 #define ARC_OPERAND_BRAKET      0x1000
 287
 288 /* Mask for selecting the type for typecheck purposes.  */
 289 #define ARC_OPERAND_TYPECHECK_MASK              \
 290   (ARC_OPERAND_IR |                             \
 291    ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED |      \
 292    ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
 293
 294 /* The flags structure.  */
 295 struct arc_flag_operand
 296 {
 297   /* The flag name.  */
 298   const char *name;
 299
 300   /* The flag code.  */
 301   unsigned code;
 302
 303   /* The number of bits in the operand.  */
 304   unsigned int bits;
 305
 306   /* How far the operand is left shifted in the instruction.  */
 307   unsigned int shift;
 308
 309   /* Available for disassembler.  */
 310   unsigned char favail;
 311 };
 312
 313 /* The flag operands table.  */
 314 extern const struct arc_flag_operand arc_flag_operands[];
 315 extern const unsigned arc_num_flag_operands;
 316
 317 /* The flag's class structure.  */
 318 struct arc_flag_class
 319 {
 320   /* Flag class.  */
 321   flag_class_t class;
 322
 323   /* List of valid flags (codes).  */
 324   unsigned flags[256];
 325 };
 326
 327 extern const struct arc_flag_class arc_flag_classes[];
 328
 329 /* Structure for special cases.  */
 330 struct arc_flag_special
 331 {
 332   /* Name of special case instruction.  */
 333   const char *name;
 334
 335   /* List of flags applicable for special case instruction.  */
 336   unsigned flags[32];
 337 };
 338
 339 extern const struct arc_flag_special arc_flag_special_cases[];
 340 extern const unsigned arc_num_flag_special;
 341
 342 /* Relocation equivalence structure.  */
 343 struct arc_reloc_equiv_tab
 344 {
 345   const char * name;       /* String to lookup.  */
 346   const char * mnemonic;   /* Extra matching condition.  */
 347   unsigned     flags[32];  /* Extra matching condition.  */
 348   signed int   oldreloc;   /* Old relocation.  */
 349   signed int   newreloc;   /* New relocation.  */
 350 };
 351
 352 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 353 extern const unsigned arc_num_equiv_tab;
 354
 355 /* Structure for operand operations for pseudo/alias instructions.  */
 356 struct arc_operand_operation
 357 {
 358   /* The index for operand from operand array.  */
 359   unsigned operand_idx;
 360
 361   /* Defines if it needs the operand inserted by the assembler or
 362      whether this operand comes from the pseudo instruction's
 363      operands.  */
 364   unsigned char needs_insert;
 365
 366   /* Count we have to add to the operand.  Use negative number to
 367      subtract from the operand.  Also use this number to add to 0 if
 368      the operand needs to be inserted (i.e. needs_insert == 1).  */
 369   int count;
 370
 371   /* Index of the operand to swap with.  To be done AFTER applying
 372      inc_count.  */
 373   unsigned swap_operand_idx;
 374 };
 375
 376 /* Structure for pseudo/alias instructions.  */
 377 struct arc_pseudo_insn
 378 {
 379   /* Mnemonic for pseudo/alias insn.  */
 380   const char *mnemonic_p;
 381
 382   /* Mnemonic for real instruction.  */
 383   const char *mnemonic_r;
 384
 385   /* Flag that will have to be added (if any).  */
 386   const char *flag_r;
 387
 388   /* Amount of operands.  */
 389   unsigned operand_cnt;
 390
 391   /* Array of operand operations.  */
 392   struct arc_operand_operation operand[6];
 393 };
 394
 395 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 396 extern const unsigned arc_num_pseudo_insn;
 397
 398 /* Structure for AUXILIARY registers.  */
 399 struct arc_aux_reg
 400 {
 401   /* Register address.  */
 402   int address;
 403
 404  /* Register name.  */
 405   const char *name;
 406
 407   /* Size of the string.  */
 408   size_t length;
 409 };
 410
 411 extern const struct arc_aux_reg arc_aux_regs[];
 412 extern const unsigned arc_num_aux_regs;
 413
 414 extern const struct arc_opcode arc_relax_opcodes[];
 415 extern const unsigned arc_num_relax_opcodes;
 416
 417 #endif /* OPCODE_ARC_H */