include/opcode/hppa.h

   1 /* Table of opcodes for the PA-RISC.
   2    Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc.
   3
   4    Contributed by the Center for Software Science at the
   5    University of Utah (pa-gdb-bugs@cs.utah.edu).
   6
   7 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
   8
   9 GAS/GDB is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 1, or (at your option)
  12 any later version.
  13
  14 GAS/GDB is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with GAS or GDB; see the file COPYING.  If not, write to
  21 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #if !defined(__STDC__) && !defined(const)
  24 #define const
  25 #endif
  26
  27 /*
  28  * Structure of an opcode table entry.
  29  */
  30
  31 /* There are two kinds of delay slot nullification: normal which is
  32  * controled by the nullification bit, and conditional, which depends
  33  * on the direction of the branch and its success or failure.
  34  *
  35  * NONE is unfortunately #defined in the hiux system include files.
  36  * #undef it away.
  37  */
  38 #undef NONE
  39 struct pa_opcode
  40 {
  41     const char *name;
  42     unsigned long int match;    /* Bits that must be set...  */
  43     unsigned long int mask;     /* ... in these bits. */
  44     char *args;
  45     enum pa_arch arch;
  46     char flags;
  47 };
  48
  49 /* Enable/disable strict syntax checking.  Not currently used, but will
  50    be necessary for PA2.0 support in the future.  */
  51 #define FLAG_STRICT 0x1
  52
  53 /*
  54    All hppa opcodes are 32 bits.
  55
  56    The match component is a mask saying which bits must match a
  57    particular opcode in order for an instruction to be an instance
  58    of that opcode.
  59
  60    The args component is a string containing one character for each operand of
  61    the instruction.  Characters used as a prefix allow any second character to
  62    be used without conflicting with the main operand characters.
  63
  64    Bit positions in this description follow HP usage of lsb = 31,
  65    "at" is lsb of field.
  66
  67    In the args field, the following characters must match exactly:
  68
  69         '+,() '
  70
  71    In the args field, the following characters are unused:
  72
  73         '  "# %&   *+-  /          :;< > @'
  74         '  C        LM       U   YZ[\]  '
  75         'a  d       l              {|} '
  76
  77    Here are all the characters:
  78
  79         ' !"#$%&'()*+-,./0123456789:;<=>?@'
  80         'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
  81         'abcdefghijklmnopqrstuvwxyz{|}~'
  82
  83 Kinds of operands:
  84    x    integer register field at 15.
  85    b    integer register field at 10.
  86    t    integer register field at 31.
  87    y    floating point register field at 31
  88    5    5 bit immediate at 15.
  89    s    2 bit space specifier at 17.
  90    S    3 bit space specifier at 18.
  91    V    5 bit immediate value at 31
  92    i    11 bit immediate value at 31
  93    j    14 bit immediate value at 31
  94    k    21 bit immediate value at 31
  95    n    nullification for branch instructions
  96    N    nullification for spop and copr instructions
  97    w    12 bit branch displacement
  98    W    17 bit branch displacement (PC relative)
  99    z    17 bit branch displacement (just a number, not an address)
 100
 101 Completer operands all have 'c' as the prefix:
 102
 103    cx   indexed load completer.
 104    cm   short load and store completer.
 105    cs   store bytes short completer.
 106    cZ   System Control Completer (to support LPA, LHA, etc.)
 107
 108 Condition operands all have '?' as the prefix:
 109
 110    ?f   Floating point compare conditions (encoded as 5 bits at 31)
 111
 112    ?a   add conditions
 113    ?A   64 bit add conditions
 114    ?@   add branch conditions followed by nullify
 115    ?d   non-negated add branch conditions
 116    ?D   negated add branch conditions
 117    ?w   wide mode non-negated add branch conditions
 118    ?W   wide mode negated add branch conditions
 119
 120    ?s   compare/subtract conditions
 121    ?S   64 bit compare/subtract conditions
 122    ?t   non-negated compare conditions
 123    ?T   negated compare conditions
 124    ?r   64 bit non-negated compare conditions
 125    ?R   64 bit negated compare conditions
 126    ?Q   64 bit compare conditions for CMPIB instruction
 127    ?n   compare conditions followed by nullify
 128
 129    ?l   logical conditions
 130    ?L   64 bit logical conditions
 131
 132    ?b   branch on bit conditions
 133    ?B   64 bit branch on bit conditions
 134
 135    ?x   shift/extract/deposit conditions
 136    ?X   64 bit shift/extract/deposit conditions
 137    ?y   shift/extract/deposit conditions followed by nullify for conditional
 138         branches
 139
 140    ?u   unit conditions
 141    ?U   64 bit unit conditions
 142
 143 Also these:
 144
 145    .    2 bit shift amount at 25
 146    p    5 bit shift count at 26 (to support the SHD instruction) encoded as
 147         31-p
 148    ~    6 bit shift count at 20,22:26 encoded as 63-~.
 149    P    5 bit bit position at 26
 150    T    5 bit field length at 31 (encoded as 32-T)
 151    A    13 bit immediate at 18 (to support the BREAK instruction)
 152    ^    like b, but describes a control register
 153    !    sar (cr11) register
 154    D    26 bit immediate at 31 (to support the DIAG instruction)
 155    $    9 bit immediate at 28 (to support POPBTS)
 156
 157    f    3 bit Special Function Unit identifier at 25
 158    O    20 bit Special Function Unit operation split between 15 bits at 20
 159         and 5 bits at 31
 160    o    15 bit Special Function Unit operation at 20
 161    2    22 bit Special Function Unit operation split between 17 bits at 20
 162         and 5 bits at 31
 163    1    15 bit Special Function Unit operation split between 10 bits at 20
 164         and 5 bits at 31
 165    0    10 bit Special Function Unit operation split between 5 bits at 20
 166         and 5 bits at 31
 167    u    3 bit coprocessor unit identifier at 25
 168    F    Source Floating Point Operand Format Completer encoded 2 bits at 20
 169    I    Source Floating Point Operand Format Completer encoded 1 bits at 20
 170         (for 0xe format FP instructions)
 171    G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
 172
 173    r    5 bit immediate value at 31 (for the break instruction)
 174         (very similar to V above, except the value is unsigned instead of
 175         low_sign_ext)
 176    R    5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
 177         (same as r above, except the value is in a different location)
 178    Q    5 bit immediate value at 10 (a bit position specified in
 179         the bb instruction. It's the same as r above, except the
 180         value is in a different location)
 181
 182 And these (PJH) for PA-89 F.P. registers and instructions:
 183
 184    v    a 't' operand type extended to handle L/R register halves.
 185    E    a 'b' operand type extended to handle L/R register halves.
 186    X    an 'x' operand type extended to handle L/R register halves.
 187    J    a 'b' operand type further extended to handle extra 1.1 registers
 188    K    a 'x' operand type further extended to handle extra 1.1 registers
 189    4    a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
 190    6    a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
 191    7    a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
 192    8    5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
 193    9    5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
 194    H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
 195         (very similar to 'F')
 196 */
 197
 198
 199 /* List of characters not to put a space after.  Note that
 200    "," is included, as the "spopN" operations use literal
 201    commas in their completer sections. */
 202 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
 203
 204 /* The order of the opcodes in this table is significant:
 205
 206    * The assembler requires that all instances of the same mnemonic must be
 207    consecutive.  If they aren't, the assembler will bomb at runtime.
 208
 209    * The disassembler should not care about the order of the opcodes.  */
 210
 211 static const struct pa_opcode pa_opcodes[] =
 212 {
 213
 214
 215 /* pseudo-instructions */
 216
 217 { "b",          0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */
 218 { "ldi",        0x34000000, 0xffe0c000, "j,x", pa10},   /* ldo val(r0),r */
 219 { "comib",      0x84000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/
 220 /* This entry is for the disassembler only.  It will never be used by
 221    assembler.  */
 222 { "comib",      0x8c000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/
 223 { "comb",       0x80000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */
 224 /* This entry is for the disassembler only.  It will never be used by
 225    assembler.  */
 226 { "comb",       0x88000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */
 227 { "addb",       0xa0000000, 0xfc000000, "?@nx,b,w", pa10}, /* addb{tf} */
 228 /* This entry is for the disassembler only.  It will never be used by
 229    assembler.  */
 230 { "addb",       0xa8000000, 0xfc000000, "?@nx,b,w", pa10},
 231 { "addib",      0xa4000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/
 232 /* This entry is for the disassembler only.  It will never be used by
 233    assembler.  */
 234 { "addib",      0xac000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/
 235 { "nop",        0x08000240, 0xffffffff, "", pa10},      /* or 0,0,0 */
 236 { "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10},   /* or r,0,t */
 237 { "mtsar",      0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */
 238
 239 /* Loads and Stores for integer registers.  */
 240 { "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10},
 241 { "ldw",        0x48000000, 0xfc000000, "j(b),x", pa10},
 242 { "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10},
 243 { "ldh",        0x44000000, 0xfc000000, "j(b),x", pa10},
 244 { "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10},
 245 { "ldb",        0x40000000, 0xfc000000, "j(b),x", pa10},
 246 { "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10},
 247 { "stw",        0x68000000, 0xfc000000, "x,j(b)", pa10},
 248 { "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10},
 249 { "sth",        0x64000000, 0xfc000000, "x,j(b)", pa10},
 250 { "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10},
 251 { "stb",        0x60000000, 0xfc000000, "x,j(b)", pa10},
 252 { "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10},
 253 { "ldwm",       0x4c000000, 0xfc000000, "j(b),x", pa10},
 254 { "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10},
 255 { "stwm",       0x6c000000, 0xfc000000, "x,j(b)", pa10},
 256 { "ldwx",       0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10},
 257 { "ldwx",       0x0c000080, 0xfc001fc0, "cxx(b),t", pa10},
 258 { "ldhx",       0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10},
 259 { "ldhx",       0x0c000040, 0xfc001fc0, "cxx(b),t", pa10},
 260 { "ldbx",       0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10},
 261 { "ldbx",       0x0c000000, 0xfc001fc0, "cxx(b),t", pa10},
 262 { "ldwax",      0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10},
 263 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10},
 264 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10},
 265 { "ldws",       0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10},
 266 { "ldws",       0x0c001080, 0xfc001fc0, "cm5(b),t", pa10},
 267 { "ldhs",       0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10},
 268 { "ldhs",       0x0c001040, 0xfc001fc0, "cm5(b),t", pa10},
 269 { "ldbs",       0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10},
 270 { "ldbs",       0x0c001000, 0xfc001fc0, "cm5(b),t", pa10},
 271 { "ldwas",      0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10},
 272 { "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10},
 273 { "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10},
 274 { "stws",       0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10},
 275 { "stws",       0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10},
 276 { "sths",       0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10},
 277 { "sths",       0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10},
 278 { "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10},
 279 { "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10},
 280 { "stwas",      0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10},
 281 { "stbys",      0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10},
 282 { "stbys",      0x0c001300, 0xfc001fc0, "csx,V(b)", pa10},
 283
 284 /* Immediate instructions.  */
 285 { "ldo",        0x34000000, 0xfc00c000, "j(b),x", pa10},
 286 { "ldil",       0x20000000, 0xfc000000, "k,b", pa10},
 287 { "addil",      0x28000000, 0xfc000000, "k,b", pa10},
 288
 289 /* Branching instructions. */
 290 { "bl",         0xe8000000, 0xfc00e000, "nW,b", pa10},
 291 { "gate",       0xe8002000, 0xfc00e000, "nW,b", pa10},
 292 { "blr",        0xe8004000, 0xfc00e001, "nx,b", pa10},
 293 { "bv",         0xe800c000, 0xfc00fffd, "nx(b)", pa10},
 294 { "bv",         0xe800c000, 0xfc00fffd, "n(b)", pa10},
 295 { "be",         0xe0000000, 0xfc000000, "nz(S,b)", pa10},
 296 { "ble",        0xe4000000, 0xfc000000, "nz(S,b)", pa10},
 297 { "movb",       0xc8000000, 0xfc000000, "?ynx,b,w", pa10},
 298 { "movib",      0xcc000000, 0xfc000000, "?yn5,b,w", pa10},
 299 { "combt",      0x80000000, 0xfc000000, "?tnx,b,w", pa10},
 300 { "combf",      0x88000000, 0xfc000000, "?tnx,b,w", pa10},
 301 { "comibt",     0x84000000, 0xfc000000, "?tn5,b,w", pa10},
 302 { "comibf",     0x8c000000, 0xfc000000, "?tn5,b,w", pa10},
 303 { "addbt",      0xa0000000, 0xfc000000, "?dnx,b,w", pa10},
 304 { "addbf",      0xa8000000, 0xfc000000, "?dnx,b,w", pa10},
 305 { "addibt",     0xa4000000, 0xfc000000, "?dn5,b,w", pa10},
 306 { "addibf",     0xac000000, 0xfc000000, "?dn5,b,w", pa10},
 307 { "bb",         0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
 308 { "bb",         0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
 309 { "bb",         0xc4006000, 0xfc006000, "?Bnx,Q,w", pa20, FLAG_STRICT},
 310 { "bb",         0xc4004000, 0xfc004000, "?bnx,Q,w", pa10},
 311 { "bvb",        0xc0004000, 0xffe04000, "?bnx,w", pa10},
 312 { "clrbts",     0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
 313 { "popbts",     0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
 314 { "pushnom",    0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
 315 { "pushbts",    0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 316
 317 /* Computation Instructions */
 318
 319 { "cmpclr",     0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
 320 { "cmpclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
 321 { "comclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10},
 322 { "or",         0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 323 { "or",         0x08000240, 0xfc000fe0, "?lx,b,t", pa10},
 324 { "xor",        0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 325 { "xor",        0x08000280, 0xfc000fe0, "?lx,b,t", pa10},
 326 { "and",        0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 327 { "and",        0x08000200, 0xfc000fe0, "?lx,b,t", pa10},
 328 { "andcm",      0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 329 { "andcm",      0x08000000, 0xfc000fe0, "?lx,b,t", pa10},
 330 { "uxor",       0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
 331 { "uxor",       0x08000380, 0xfc000fe0, "?ux,b,t", pa10},
 332 { "uaddcm",     0x08000920, 0xfc000f20, "*?ux,b,t",pa20, FLAG_STRICT},
 333 { "uaddcm",     0x08000980, 0xfc000fe0, "?ux,b,t", pa10},
 334 { "uaddcmt",    0x080009c0, 0xfc000fe0, "?ux,b,t", pa10},
 335 { "dcor",       0x08000ba0, 0xfc1f0fa0, "%?ub,t",  pa20, FLAG_STRICT},
 336 { "dcor",       0x08000b80, 0xfc1f0fe0, "?ub,t",   pa10},
 337 { "idcor",      0x08000bc0, 0xfc1f0fe0, "?ub,t",   pa10},
 338 { "addi",       0xb4000000, 0xfc000800, "?ai,b,x", pa10},
 339 { "addio",      0xb4000800, 0xfc000800, "?ai,b,x", pa10},
 340 { "addit",      0xb0000000, 0xfc000800, "?ai,b,x", pa10},
 341 { "addito",     0xb0000800, 0xfc000800, "?ai,b,x", pa10},
 342 { "add",        0x08000600, 0xfc000fe0, "?ax,b,t", pa10},
 343 { "addl",       0x08000a00, 0xfc000fe0, "?ax,b,t", pa10},
 344 { "addo",       0x08000e00, 0xfc000fe0, "?ax,b,t", pa10},
 345 { "addc",       0x08000700, 0xfc000fe0, "?ax,b,t", pa10},
 346 { "addco",      0x08000f00, 0xfc000fe0, "?ax,b,t", pa10},
 347 { "sub",        0x08000400, 0xfc000fe0, "?sx,b,t", pa10},
 348 { "subo",       0x08000c00, 0xfc000fe0, "?sx,b,t", pa10},
 349 { "subb",       0x08000500, 0xfc000fe0, "?sx,b,t", pa10},
 350 { "subbo",      0x08000d00, 0xfc000fe0, "?sx,b,t", pa10},
 351 { "subt",       0x080004c0, 0xfc000fe0, "?sx,b,t", pa10},
 352 { "subto",      0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10},
 353 { "ds",         0x08000440, 0xfc000fe0, "?sx,b,t", pa10},
 354 { "subi",       0x94000000, 0xfc000800, "?si,b,x", pa10},
 355 { "subio",      0x94000800, 0xfc000800, "?si,b,x", pa10},
 356 { "cmpiclr",    0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
 357 { "cmpiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
 358 { "comiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10},
 359 { "sh1add",     0x08000640, 0xfc000fe0, "?ax,b,t", pa10},
 360 { "sh1addl",    0x08000a40, 0xfc000fe0, "?ax,b,t", pa10},
 361 { "sh1addo",    0x08000e40, 0xfc000fe0, "?ax,b,t", pa10},
 362 { "sh2add",     0x08000680, 0xfc000fe0, "?ax,b,t", pa10},
 363 { "sh2addl",    0x08000a80, 0xfc000fe0, "?ax,b,t", pa10},
 364 { "sh2addo",    0x08000e80, 0xfc000fe0, "?ax,b,t", pa10},
 365 { "sh3add",     0x080006c0, 0xfc000fe0, "?ax,b,t", pa10},
 366 { "sh3addl",    0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10},
 367 { "sh3addo",    0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10},
 368
 369 /* Subword Operation Instructions */
 370
 371 { "havg",       0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
 372 { "hshladd",    0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
 373 { "hshradd",    0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
 374
 375
 376 /* Extract and Deposit Instructions */
 377
 378 { "shrpd",      0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
 379 { "shrpd",      0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
 380 { "shrpw",      0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
 381 { "shrpw",      0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
 382 { "vshd",       0xd0000000, 0xfc001fe0, "?xx,b,t", pa10},
 383 { "shd",        0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10},
 384 { "vextru",     0xd0001000, 0xfc001fe0, "?xb,T,x", pa10},
 385 { "vextrs",     0xd0001400, 0xfc001fe0, "?xb,T,x", pa10},
 386 { "extru",      0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10},
 387 { "extrs",      0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10},
 388 { "zvdep",      0xd4000000, 0xfc001fe0, "?xx,T,b", pa10},
 389 { "vdep",       0xd4000400, 0xfc001fe0, "?xx,T,b", pa10},
 390 { "zdep",       0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10},
 391 { "dep",        0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10},
 392 { "zvdepi",     0xd4001000, 0xfc001fe0, "?x5,T,b", pa10},
 393 { "vdepi",      0xd4001400, 0xfc001fe0, "?x5,T,b", pa10},
 394 { "zdepi",      0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10},
 395 { "depi",       0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10},
 396
 397 /* System Control Instructions */
 398
 399 { "break",      0x00000000, 0xfc001fe0, "r,A", pa10},
 400 { "rfi",        0x00000c00, 0xffffffff, "", pa10},
 401 { "rfir",       0x00000ca0, 0xffffffff, "", pa11},
 402 { "ssm",        0x00000d60, 0xffe0ffe0, "R,t", pa10},
 403 { "rsm",        0x00000e60, 0xffe0ffe0, "R,t", pa10},
 404 { "mtsm",       0x00001860, 0xffe0ffff, "x", pa10},
 405 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10},
 406 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t", pa10},
 407 { "mtsp",       0x00001820, 0xffe01fff, "x,S", pa10},
 408 { "mtctl",      0x00001840, 0xfc00ffff, "x,^", pa10},
 409 { "mtsarcm",    0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 410 { "mfia",       0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
 411 { "mfsp",       0x000004a0, 0xffff1fe0, "S,t", pa10},
 412 { "mfctl",      0x000008a0, 0xfc1fffe0, "^,t", pa10},
 413 { "sync",       0x00000400, 0xffffffff, "", pa10},
 414 { "syncdma",    0x00100400, 0xffffffff, "", pa10},
 415 { "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t", pa10},
 416 { "prober",     0x04001180, 0xfc003fe0, "(b),x,t", pa10},
 417 { "proberi",    0x04003180, 0xfc003fe0, "(s,b),R,t", pa10},
 418 { "proberi",    0x04003180, 0xfc003fe0, "(b),R,t", pa10},
 419 { "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10},
 420 { "probew",     0x040011c0, 0xfc003fe0, "(b),x,t", pa10},
 421 { "probewi",    0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10},
 422 { "probewi",    0x040031c0, 0xfc003fe0, "(b),R,t", pa10},
 423 { "lpa",        0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10},
 424 { "lpa",        0x04001340, 0xfc003fc0, "cZx(b),t", pa10},
 425 { "lha",        0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10},
 426 { "lha",        0x04001300, 0xfc003fc0, "cZx(b),t", pa10},
 427 { "lci",        0x04001300, 0xfc003fe0, "x(s,b),t", pa10},
 428 { "lci",        0x04001300, 0xfc003fe0, "x(b),t", pa10},
 429 { "pdtlb",      0x04001200, 0xfc003fdf, "cZx(s,b)", pa10},
 430 { "pdtlb",      0x04001200, 0xfc003fdf, "cZx(b)", pa10},
 431 { "pitlb",      0x04000200, 0xfc001fdf, "cZx(S,b)", pa10},
 432 { "pitlb",      0x04000200, 0xfc001fdf, "cZx(b)", pa10},
 433 { "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(s,b)", pa10},
 434 { "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(b)", pa10},
 435 { "pitlbe",     0x04000240, 0xfc001fdf, "cZx(S,b)", pa10},
 436 { "pitlbe",     0x04000240, 0xfc001fdf, "cZx(b)", pa10},
 437 { "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)", pa10},
 438 { "idtlba",     0x04001040, 0xfc003fff, "x,(b)", pa10},
 439 { "iitlba",     0x04000040, 0xfc001fff, "x,(S,b)", pa10},
 440 { "iitlba",     0x04000040, 0xfc001fff, "x,(b)", pa10},
 441 { "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)", pa10},
 442 { "idtlbp",     0x04001000, 0xfc003fff, "x,(b)", pa10},
 443 { "iitlbp",     0x04000000, 0xfc001fff, "x,(S,b)", pa10},
 444 { "iitlbp",     0x04000000, 0xfc001fff, "x,(b)", pa10},
 445 { "pdc",        0x04001380, 0xfc003fdf, "cZx(s,b)", pa10},
 446 { "pdc",        0x04001380, 0xfc003fdf, "cZx(b)", pa10},
 447 { "fdc",        0x04001280, 0xfc003fdf, "cZx(s,b)", pa10},
 448 { "fdc",        0x04001280, 0xfc003fdf, "cZx(b)", pa10},
 449 { "fic",        0x04000280, 0xfc001fdf, "cZx(S,b)", pa10},
 450 { "fic",        0x04000280, 0xfc001fdf, "cZx(b)", pa10},
 451 { "fdce",       0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10},
 452 { "fdce",       0x040012c0, 0xfc003fdf, "cZx(b)", pa10},
 453 { "fice",       0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10},
 454 { "fice",       0x040002c0, 0xfc001fdf, "cZx(b)", pa10},
 455 { "diag",       0x14000000, 0xfc000000, "D", pa10},
 456
 457 /* These may be specific to certain versions of the PA.  Joel claimed
 458    they were 72000 (7200?) specific.  However, I'm almost certain the
 459    mtcpu/mfcpu were undocumented, but available in the older 700 machines.  */
 460 { "mtcpu",      0x14001600, 0xfc00ffff, "x,^"},
 461 { "mfcpu",      0x14001A00, 0xfc00ffff, "^,x"},
 462 { "tocen",      0x14403600, 0xffffffff, ""},
 463 { "tocdis",     0x14401620, 0xffffffff, ""},
 464 { "shdwgr",     0x14402600, 0xffffffff, ""},
 465 { "grshdw",     0x14400620, 0xffffffff, ""},
 466
 467 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
 468    the Timex FPU or the Mustang ERS (not sure which) manual.  */
 469 { "gfw",        0x04001680, 0xfc003fdf, "cZx(s,b)", pa11},
 470 { "gfw",        0x04001680, 0xfc003fdf, "cZx(b)", pa11},
 471 { "gfr",        0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11},
 472 { "gfr",        0x04001a80, 0xfc003fdf, "cZx(b)", pa11},
 473
 474 /* Floating Point Coprocessor Instructions */
 475
 476 { "fldwx",      0x24000000, 0xfc001f80, "cxx(s,b),v", pa10},
 477 { "fldwx",      0x24000000, 0xfc001f80, "cxx(b),v", pa10},
 478 { "flddx",      0x2c000000, 0xfc001fc0, "cxx(s,b),y", pa10},
 479 { "flddx",      0x2c000000, 0xfc001fc0, "cxx(b),y", pa10},
 480 { "fstwx",      0x24000200, 0xfc001f80, "cxv,x(s,b)", pa10},
 481 { "fstwx",      0x24000200, 0xfc001f80, "cxv,x(b)", pa10},
 482 { "fstdx",      0x2c000200, 0xfc001fc0, "cxy,x(s,b)", pa10},
 483 { "fstdx",      0x2c000200, 0xfc001fc0, "cxy,x(b)", pa10},
 484 { "fstqx",      0x3c000200, 0xfc001fc0, "cxy,x(s,b)", pa10},
 485 { "fstqx",      0x3c000200, 0xfc001fc0, "cxy,x(b)", pa10},
 486 { "fldws",      0x24001000, 0xfc001f80, "cm5(s,b),v", pa10},
 487 { "fldws",      0x24001000, 0xfc001f80, "cm5(b),v", pa10},
 488 { "fldds",      0x2c001000, 0xfc001fc0, "cm5(s,b),y", pa10},
 489 { "fldds",      0x2c001000, 0xfc001fc0, "cm5(b),y", pa10},
 490 { "fstws",      0x24001200, 0xfc001f80, "cmv,5(s,b)", pa10},
 491 { "fstws",      0x24001200, 0xfc001f80, "cmv,5(b)", pa10},
 492 { "fstds",      0x2c001200, 0xfc001fc0, "cmy,5(s,b)", pa10},
 493 { "fstds",      0x2c001200, 0xfc001fc0, "cmy,5(b)", pa10},
 494 { "fstqs",      0x3c001200, 0xfc001fc0, "cmy,5(s,b)", pa10},
 495 { "fstqs",      0x3c001200, 0xfc001fc0, "cmy,5(b)", pa10},
 496 { "fadd",       0x30000600, 0xfc00e7e0, "FE,X,v", pa10},
 497 { "fadd",       0x38000600, 0xfc00e720, "IJ,K,v", pa10},
 498 { "fsub",       0x30002600, 0xfc00e7e0, "FE,X,v", pa10},
 499 { "fsub",       0x38002600, 0xfc00e720, "IJ,K,v", pa10},
 500 { "fmpy",       0x30004600, 0xfc00e7e0, "FE,X,v", pa10},
 501 { "fmpy",       0x38004600, 0xfc00e720, "IJ,K,v", pa10},
 502 { "fdiv",       0x30006600, 0xfc00e7e0, "FE,X,v", pa10},
 503 { "fdiv",       0x38006600, 0xfc00e720, "IJ,K,v", pa10},
 504 { "fsqrt",      0x30008000, 0xfc1fe7e0, "FE,v", pa10},
 505 { "fsqrt",      0x38008000, 0xfc1fe720, "FJ,v", pa10},
 506 { "fabs",       0x30006000, 0xfc1fe7e0, "FE,v", pa10},
 507 { "fabs",       0x38006000, 0xfc1fe720, "FJ,v", pa10},
 508 { "frem",       0x30008600, 0xfc00e7e0, "FE,X,v", pa10},
 509 { "frem",       0x38008600, 0xfc00e720, "FJ,K,v", pa10},
 510 { "frnd",       0x3000a000, 0xfc1fe7e0, "FE,v", pa10},
 511 { "frnd",       0x3800a000, 0xfc1fe720, "FJ,v", pa10},
 512 { "fcpy",       0x30004000, 0xfc1fe7e0, "FE,v", pa10},
 513 { "fcpy",       0x38004000, 0xfc1fe720, "FJ,v", pa10},
 514 { "fcnvff",     0x30000200, 0xfc1f87e0, "FGE,v", pa10},
 515 { "fcnvff",     0x38000200, 0xfc1f8720, "FGJ,v", pa10},
 516 { "fcnvxf",     0x30008200, 0xfc1f87e0, "FGE,v", pa10},
 517 { "fcnvxf",     0x38008200, 0xfc1f8720, "FGJ,v", pa10},
 518 { "fcnvfx",     0x30010200, 0xfc1f87e0, "FGE,v", pa10},
 519 { "fcnvfx",     0x38010200, 0xfc1f8720, "FGJ,v", pa10},
 520 { "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGE,v", pa10},
 521 { "fcnvfxt",    0x38018200, 0xfc1f8720, "FGJ,v", pa10},
 522 { "fmpyfadd",   0xb8000000, 0xfc000020, "IJ,K,3,v", pa20, FLAG_STRICT},
 523 { "fmpynfadd",  0xb8000020, 0xfc000020, "IJ,K,3,v", pa20, FLAG_STRICT},
 524 { "fneg",       0x3000c000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
 525 { "fneg",       0x3800c000, 0xfc1fe720, "IJ,v", pa20, FLAG_STRICT},
 526 { "fnegabs",    0x3000e000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
 527 { "fnegabs",    0x3800e000, 0xfc1fe720, "IJ,v", pa20, FLAG_STRICT},
 528 { "fcmp",       0x30000400, 0xfc00e7e0, "F?fE,X", pa10},
 529 { "fcmp",       0x38000400, 0xfc00e720, "I?fJ,K", pa10},
 530 { "xmpyu",      0x38004700, 0xfc00e720, "J,K,v", pa11},
 531 { "fmpyadd",    0x18000000, 0xfc000000, "H4,6,7,9,8", pa11},
 532 { "fmpysub",    0x98000000, 0xfc000000, "H4,6,7,9,8", pa11},
 533 { "ftest",      0x30002420, 0xffffffff, "", pa10},
 534 { "fid",        0x30000000, 0xffffffff, "", pa11},
 535
 536
 537 /* Assist Instructions */
 538
 539 { "spop0",      0x10000000, 0xfc000600, "f,ON", pa10},
 540 { "spop1",      0x10000200, 0xfc000600, "f,oNt", pa10},
 541 { "spop2",      0x10000400, 0xfc000600, "f,1Nb", pa10},
 542 { "spop3",      0x10000600, 0xfc000600, "f,0Nx,b", pa10},
 543 { "copr",       0x30000000, 0xfc000000, "u,2N", pa10},
 544 { "cldwx",      0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10},
 545 { "cldwx",      0x24000000, 0xfc001e00, "ucxx(b),t", pa10},
 546 { "clddx",      0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10},
 547 { "clddx",      0x2c000000, 0xfc001e00, "ucxx(b),t", pa10},
 548 { "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10},
 549 { "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(b)", pa10},
 550 { "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10},
 551 { "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10},
 552 { "cldws",      0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10},
 553 { "cldws",      0x24001000, 0xfc001e00, "ucm5(b),t", pa10},
 554 { "cldds",      0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10},
 555 { "cldds",      0x2c001000, 0xfc001e00, "ucm5(b),t", pa10},
 556 { "cstws",      0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10},
 557 { "cstws",      0x24001200, 0xfc001e00, "ucmt,5(b)", pa10},
 558 { "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10},
 559 { "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10},
 560 };
 561
 562 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
 563
 564 /* SKV 12/18/92. Added some denotations for various operands. */
 565
 566 #define PA_IMM11_AT_31 'i'
 567 #define PA_IMM14_AT_31 'j'
 568 #define PA_IMM21_AT_31 'k'
 569 #define PA_DISP12 'w'
 570 #define PA_DISP17 'W'
 571
 572 #define N_HPPA_OPERAND_FORMATS 5