include/opcode/hppa.h

   1 /* Table of opcodes for the PA-RISC.
   2    Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc.
   3
   4    Contributed by the Center for Software Science at the
   5    University of Utah (pa-gdb-bugs@cs.utah.edu).
   6
   7 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
   8
   9 GAS/GDB is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 1, or (at your option)
  12 any later version.
  13
  14 GAS/GDB is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with GAS or GDB; see the file COPYING.  If not, write to
  21 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #if !defined(__STDC__) && !defined(const)
  24 #define const
  25 #endif
  26
  27 /*
  28  * Structure of an opcode table entry.
  29  */
  30
  31 /* There are two kinds of delay slot nullification: normal which is
  32  * controled by the nullification bit, and conditional, which depends
  33  * on the direction of the branch and its success or failure.
  34  *
  35  * NONE is unfortunately #defined in the hiux system include files.
  36  * #undef it away.
  37  */
  38 #undef NONE
  39 struct pa_opcode
  40 {
  41     const char *name;
  42     unsigned long int match;    /* Bits that must be set...  */
  43     unsigned long int mask;     /* ... in these bits. */
  44     char *args;
  45     enum pa_arch arch;
  46     char flags;
  47 };
  48
  49 /* Enable/disable strict syntax checking.  Not currently used, but will
  50    be necessary for PA2.0 support in the future.  */
  51 #define FLAG_STRICT 0x1
  52
  53 /*
  54    All hppa opcodes are 32 bits.
  55
  56    The match component is a mask saying which bits must match a
  57    particular opcode in order for an instruction to be an instance
  58    of that opcode.
  59
  60    The args component is a string containing one character for each operand of
  61    the instruction.  Characters used as a prefix allow any second character to
  62    be used without conflicting with the main operand characters.
  63
  64    Bit positions in this description follow HP usage of lsb = 31,
  65    "at" is lsb of field.
  66
  67    In the args field, the following characters must match exactly:
  68
  69         '+,() '
  70
  71    In the args field, the following characters are unused:
  72
  73         ' !"#$%&   *+- ./          :;< > @'
  74         '            M       U     [\]  '
  75         'a  d                      {|}~'
  76
  77    Here are all the characters:
  78
  79         ' !"#$%&'()*+-,./0123456789:;<=>?@'
  80         'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
  81         'abcdefghijklmnopqrstuvwxyz{|}~'
  82
  83 Kinds of operands:
  84    x    integer register field at 15.
  85    b    integer register field at 10.
  86    t    integer register field at 31.
  87    y    floating point register field at 31
  88    5    5 bit immediate at 15.
  89    s    2 bit space specifier at 17.
  90    S    3 bit space specifier at 18.
  91    c    indexed load completer.
  92    C    short load and store completer.
  93    Y    Store Bytes Short completer
  94    V    5 bit immediate value at 31
  95    i    11 bit immediate value at 31
  96    j    14 bit immediate value at 31
  97    k    21 bit immediate value at 31
  98    n    nullification for branch instructions
  99    N    nullification for spop and copr instructions
 100    w    12 bit branch displacement
 101    W    17 bit branch displacement (PC relative)
 102    z    17 bit branch displacement (just a number, not an address)
 103
 104 Condition operands all have '?' as the prefix:
 105
 106    ?f   Floating point compare conditions (encoded as 5 bits at 31)
 107
 108    ?a   add conditions
 109    ?A   64 bit add conditions
 110    ?@   add branch conditions followed by nullify
 111    ?d   non-negated add branch conditions
 112    ?D   negated add branch conditions
 113    ?w   wide mode non-negated add branch conditions
 114    ?W   wide mode negated add branch conditions
 115
 116    ?s   compare/subtract conditions
 117    ?S   64 bit compare/subtract conditions
 118    ?t   non-negated compare conditions
 119    ?T   negated compare conditions
 120    ?r   64 bit non-negated compare conditions
 121    ?R   64 bit negated compare conditions
 122    ?Q   64 bit compare conditions for CMPIB instruction
 123    ?n   compare conditions followed by nullify
 124
 125    ?l   logical conditions
 126    ?L   64 bit logical conditions
 127
 128    ?b   branch on bit conditions
 129    ?B   64 bit branch on bit conditions
 130
 131    ?x   shift/extract/deposit conditions
 132    ?X   64 bit shift/extract/deposit conditions
 133    ?y   shift/extract/deposit conditions followed by nullify for conditional
 134         branches
 135
 136    ?u   unit conditions
 137    ?U   64 bit unit conditions
 138
 139 Also these:
 140
 141    p    5 bit shift count at 26 (to support the SHD instruction) encoded as
 142         31-p
 143    P    5 bit bit position at 26
 144    T    5 bit field length at 31 (encoded as 32-T)
 145    A    13 bit immediate at 18 (to support the BREAK instruction)
 146    ^    like b, but describes a control register
 147    Z    System Control Completer (to support LPA, LHA, etc.)
 148    D    26 bit immediate at 31 (to support the DIAG instruction)
 149
 150    f    3 bit Special Function Unit identifier at 25
 151    O    20 bit Special Function Unit operation split between 15 bits at 20
 152         and 5 bits at 31
 153    o    15 bit Special Function Unit operation at 20
 154    2    22 bit Special Function Unit operation split between 17 bits at 20
 155         and 5 bits at 31
 156    1    15 bit Special Function Unit operation split between 10 bits at 20
 157         and 5 bits at 31
 158    0    10 bit Special Function Unit operation split between 5 bits at 20
 159         and 5 bits at 31
 160    u    3 bit coprocessor unit identifier at 25
 161    F    Source Floating Point Operand Format Completer encoded 2 bits at 20
 162    I    Source Floating Point Operand Format Completer encoded 1 bits at 20
 163         (for 0xe format FP instructions)
 164    G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
 165
 166    s    2 bit space specifier at 17.
 167    b    register field at 10.
 168    r    5 bit immediate value at 31 (for the break instruction)
 169         (very similar to V above, except the value is unsigned instead of
 170         low_sign_ext)
 171    R    5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
 172         (same as r above, except the value is in a different location)
 173    Q    5 bit immediate value at 10 (a bit position specified in
 174         the bb instruction. It's the same as r above, except the
 175         value is in a different location)
 176
 177 And these (PJH) for PA-89 F.P. registers and instructions:
 178
 179    v    a 't' operand type extended to handle L/R register halves.
 180    E    a 'b' operand type extended to handle L/R register halves.
 181    X    an 'x' operand type extended to handle L/R register halves.
 182    J    a 'b' operand type further extended to handle extra 1.1 registers
 183    K    a 'x' operand type further extended to handle extra 1.1 registers
 184    4    a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
 185    6    a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
 186    7    a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
 187    8    5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
 188    9    5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
 189    H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
 190         (very similar to 'F')
 191 */
 192
 193
 194 /* List of characters not to put a space after.  Note that
 195    "," is included, as the "spopN" operations use literal
 196    commas in their completer sections. */
 197 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
 198
 199 /* The order of the opcodes in this table is significant:
 200
 201    * The assembler requires that all instances of the same mnemonic must be
 202    consecutive.  If they aren't, the assembler will bomb at runtime.
 203
 204    * The disassembler should not care about the order of the opcodes.  */
 205
 206 static const struct pa_opcode pa_opcodes[] =
 207 {
 208
 209
 210 /* pseudo-instructions */
 211
 212 { "b",          0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */
 213 { "ldi",        0x34000000, 0xffe0c000, "j,x", pa10},   /* ldo val(r0),r */
 214 { "comib",      0x84000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/
 215 /* This entry is for the disassembler only.  It will never be used by
 216    assembler.  */
 217 { "comib",      0x8c000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/
 218 { "comb",       0x80000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */
 219 /* This entry is for the disassembler only.  It will never be used by
 220    assembler.  */
 221 { "comb",       0x88000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */
 222 { "addb",       0xa0000000, 0xfc000000, "?@nx,b,w", pa10}, /* addb{tf} */
 223 /* This entry is for the disassembler only.  It will never be used by
 224    assembler.  */
 225 { "addb",       0xa8000000, 0xfc000000, "?@nx,b,w", pa10},
 226 { "addib",      0xa4000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/
 227 /* This entry is for the disassembler only.  It will never be used by
 228    assembler.  */
 229 { "addib",      0xac000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/
 230 { "nop",        0x08000240, 0xffffffff, "", pa10},      /* or 0,0,0 */
 231 { "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10},   /* or r,0,t */
 232 { "mtsar",      0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */
 233
 234 /* Loads and Stores for integer registers.  */
 235 { "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10},
 236 { "ldw",        0x48000000, 0xfc000000, "j(b),x", pa10},
 237 { "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10},
 238 { "ldh",        0x44000000, 0xfc000000, "j(b),x", pa10},
 239 { "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10},
 240 { "ldb",        0x40000000, 0xfc000000, "j(b),x", pa10},
 241 { "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10},
 242 { "stw",        0x68000000, 0xfc000000, "x,j(b)", pa10},
 243 { "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10},
 244 { "sth",        0x64000000, 0xfc000000, "x,j(b)", pa10},
 245 { "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10},
 246 { "stb",        0x60000000, 0xfc000000, "x,j(b)", pa10},
 247 { "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10},
 248 { "ldwm",       0x4c000000, 0xfc000000, "j(b),x", pa10},
 249 { "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10},
 250 { "stwm",       0x6c000000, 0xfc000000, "x,j(b)", pa10},
 251 { "ldwx",       0x0c000080, 0xfc001fc0, "cx(s,b),t", pa10},
 252 { "ldwx",       0x0c000080, 0xfc001fc0, "cx(b),t", pa10},
 253 { "ldhx",       0x0c000040, 0xfc001fc0, "cx(s,b),t", pa10},
 254 { "ldhx",       0x0c000040, 0xfc001fc0, "cx(b),t", pa10},
 255 { "ldbx",       0x0c000000, 0xfc001fc0, "cx(s,b),t", pa10},
 256 { "ldbx",       0x0c000000, 0xfc001fc0, "cx(b),t", pa10},
 257 { "ldwax",      0x0c000180, 0xfc00dfc0, "cx(b),t", pa10},
 258 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(s,b),t", pa10},
 259 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(b),t", pa10},
 260 { "ldws",       0x0c001080, 0xfc001fc0, "C5(s,b),t", pa10},
 261 { "ldws",       0x0c001080, 0xfc001fc0, "C5(b),t", pa10},
 262 { "ldhs",       0x0c001040, 0xfc001fc0, "C5(s,b),t", pa10},
 263 { "ldhs",       0x0c001040, 0xfc001fc0, "C5(b),t", pa10},
 264 { "ldbs",       0x0c001000, 0xfc001fc0, "C5(s,b),t", pa10},
 265 { "ldbs",       0x0c001000, 0xfc001fc0, "C5(b),t", pa10},
 266 { "ldwas",      0x0c001180, 0xfc00dfc0, "C5(b),t", pa10},
 267 { "ldcws",      0x0c0011c0, 0xfc001fc0, "C5(s,b),t", pa10},
 268 { "ldcws",      0x0c0011c0, 0xfc001fc0, "C5(b),t", pa10},
 269 { "stws",       0x0c001280, 0xfc001fc0, "Cx,V(s,b)", pa10},
 270 { "stws",       0x0c001280, 0xfc001fc0, "Cx,V(b)", pa10},
 271 { "sths",       0x0c001240, 0xfc001fc0, "Cx,V(s,b)", pa10},
 272 { "sths",       0x0c001240, 0xfc001fc0, "Cx,V(b)", pa10},
 273 { "stbs",       0x0c001200, 0xfc001fc0, "Cx,V(s,b)", pa10},
 274 { "stbs",       0x0c001200, 0xfc001fc0, "Cx,V(b)", pa10},
 275 { "stwas",      0x0c001380, 0xfc00dfc0, "Cx,V(b)", pa10},
 276 { "stbys",      0x0c001300, 0xfc001fc0, "Yx,V(s,b)", pa10},
 277 { "stbys",      0x0c001300, 0xfc001fc0, "Yx,V(b)", pa10},
 278
 279 /* Immediate instructions.  */
 280 { "ldo",        0x34000000, 0xfc00c000, "j(b),x", pa10},
 281 { "ldil",       0x20000000, 0xfc000000, "k,b", pa10},
 282 { "addil",      0x28000000, 0xfc000000, "k,b", pa10},
 283
 284 /* Branching instructions. */
 285 { "bl",         0xe8000000, 0xfc00e000, "nW,b", pa10},
 286 { "gate",       0xe8002000, 0xfc00e000, "nW,b", pa10},
 287 { "blr",        0xe8004000, 0xfc00e001, "nx,b", pa10},
 288 { "bv",         0xe800c000, 0xfc00fffd, "nx(b)", pa10},
 289 { "bv",         0xe800c000, 0xfc00fffd, "n(b)", pa10},
 290 { "be",         0xe0000000, 0xfc000000, "nz(S,b)", pa10},
 291 { "ble",        0xe4000000, 0xfc000000, "nz(S,b)", pa10},
 292 { "movb",       0xc8000000, 0xfc000000, "?ynx,b,w", pa10},
 293 { "movib",      0xcc000000, 0xfc000000, "?yn5,b,w", pa10},
 294 { "combt",      0x80000000, 0xfc000000, "?tnx,b,w", pa10},
 295 { "combf",      0x88000000, 0xfc000000, "?tnx,b,w", pa10},
 296 { "comibt",     0x84000000, 0xfc000000, "?tn5,b,w", pa10},
 297 { "comibf",     0x8c000000, 0xfc000000, "?tn5,b,w", pa10},
 298 { "addbt",      0xa0000000, 0xfc000000, "?dnx,b,w", pa10},
 299 { "addbf",      0xa8000000, 0xfc000000, "?dnx,b,w", pa10},
 300 { "addibt",     0xa4000000, 0xfc000000, "?dn5,b,w", pa10},
 301 { "addibf",     0xac000000, 0xfc000000, "?dn5,b,w", pa10},
 302 { "bb",         0xc4004000, 0xfc004000, "?bnx,Q,w", pa10},
 303 { "bvb",        0xc0004000, 0xffe04000, "?bnx,w", pa10},
 304 { "clrbts",     0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
 305 { "pushnom",    0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
 306 { "pushbts",    0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 307
 308 /* Computation Instructions */
 309
 310 { "cmpclr",     0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
 311 { "cmpclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
 312 { "comclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10},
 313 { "or",         0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 314 { "or",         0x08000240, 0xfc000fe0, "?lx,b,t", pa10},
 315 { "xor",        0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 316 { "xor",        0x08000280, 0xfc000fe0, "?lx,b,t", pa10},
 317 { "and",        0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 318 { "and",        0x08000200, 0xfc000fe0, "?lx,b,t", pa10},
 319 { "andcm",      0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 320 { "andcm",      0x08000000, 0xfc000fe0, "?lx,b,t", pa10},
 321 { "uxor",       0x08000380, 0xfc000fe0, "?ux,b,t", pa10},
 322 { "uaddcm",     0x08000980, 0xfc000fe0, "?ux,b,t", pa10},
 323 { "uaddcmt",    0x080009c0, 0xfc000fe0, "?ux,b,t", pa10},
 324 { "dcor",       0x08000b80, 0xfc1f0fe0, "?ub,t",   pa10},
 325 { "idcor",      0x08000bc0, 0xfc1f0fe0, "?ub,t",   pa10},
 326 { "addi",       0xb4000000, 0xfc000800, "?ai,b,x", pa10},
 327 { "addio",      0xb4000800, 0xfc000800, "?ai,b,x", pa10},
 328 { "addit",      0xb0000000, 0xfc000800, "?ai,b,x", pa10},
 329 { "addito",     0xb0000800, 0xfc000800, "?ai,b,x", pa10},
 330 { "add",        0x08000600, 0xfc000fe0, "?ax,b,t", pa10},
 331 { "addl",       0x08000a00, 0xfc000fe0, "?ax,b,t", pa10},
 332 { "addo",       0x08000e00, 0xfc000fe0, "?ax,b,t", pa10},
 333 { "addc",       0x08000700, 0xfc000fe0, "?ax,b,t", pa10},
 334 { "addco",      0x08000f00, 0xfc000fe0, "?ax,b,t", pa10},
 335 { "sub",        0x08000400, 0xfc000fe0, "?sx,b,t", pa10},
 336 { "subo",       0x08000c00, 0xfc000fe0, "?sx,b,t", pa10},
 337 { "subb",       0x08000500, 0xfc000fe0, "?sx,b,t", pa10},
 338 { "subbo",      0x08000d00, 0xfc000fe0, "?sx,b,t", pa10},
 339 { "subt",       0x080004c0, 0xfc000fe0, "?sx,b,t", pa10},
 340 { "subto",      0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10},
 341 { "ds",         0x08000440, 0xfc000fe0, "?sx,b,t", pa10},
 342 { "subi",       0x94000000, 0xfc000800, "?si,b,x", pa10},
 343 { "subio",      0x94000800, 0xfc000800, "?si,b,x", pa10},
 344 { "cmpiclr",    0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
 345 { "cmpiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
 346 { "comiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10},
 347 { "sh1add",     0x08000640, 0xfc000fe0, "?ax,b,t", pa10},
 348 { "sh1addl",    0x08000a40, 0xfc000fe0, "?ax,b,t", pa10},
 349 { "sh1addo",    0x08000e40, 0xfc000fe0, "?ax,b,t", pa10},
 350 { "sh2add",     0x08000680, 0xfc000fe0, "?ax,b,t", pa10},
 351 { "sh2addl",    0x08000a80, 0xfc000fe0, "?ax,b,t", pa10},
 352 { "sh2addo",    0x08000e80, 0xfc000fe0, "?ax,b,t", pa10},
 353 { "sh3add",     0x080006c0, 0xfc000fe0, "?ax,b,t", pa10},
 354 { "sh3addl",    0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10},
 355 { "sh3addo",    0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10},
 356
 357 /* Extract and Deposit Instructions */
 358
 359 { "vshd",       0xd0000000, 0xfc001fe0, "?xx,b,t", pa10},
 360 { "shd",        0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10},
 361 { "vextru",     0xd0001000, 0xfc001fe0, "?xb,T,x", pa10},
 362 { "vextrs",     0xd0001400, 0xfc001fe0, "?xb,T,x", pa10},
 363 { "extru",      0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10},
 364 { "extrs",      0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10},
 365 { "zvdep",      0xd4000000, 0xfc001fe0, "?xx,T,b", pa10},
 366 { "vdep",       0xd4000400, 0xfc001fe0, "?xx,T,b", pa10},
 367 { "zdep",       0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10},
 368 { "dep",        0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10},
 369 { "zvdepi",     0xd4001000, 0xfc001fe0, "?x5,T,b", pa10},
 370 { "vdepi",      0xd4001400, 0xfc001fe0, "?x5,T,b", pa10},
 371 { "zdepi",      0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10},
 372 { "depi",       0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10},
 373
 374 /* System Control Instructions */
 375
 376 { "break",      0x00000000, 0xfc001fe0, "r,A", pa10},
 377 { "rfi",        0x00000c00, 0xffffffff, "", pa10},
 378 { "rfir",       0x00000ca0, 0xffffffff, "", pa11},
 379 { "ssm",        0x00000d60, 0xffe0ffe0, "R,t", pa10},
 380 { "rsm",        0x00000e60, 0xffe0ffe0, "R,t", pa10},
 381 { "mtsm",       0x00001860, 0xffe0ffff, "x", pa10},
 382 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10},
 383 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t", pa10},
 384 { "mtsp",       0x00001820, 0xffe01fff, "x,S", pa10},
 385 { "mtctl",      0x00001840, 0xfc00ffff, "x,^", pa10},
 386 { "mtsarcm",    0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 387 { "mfia",       0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
 388 { "mfsp",       0x000004a0, 0xffff1fe0, "S,t", pa10},
 389 { "mfctl",      0x000008a0, 0xfc1fffe0, "^,t", pa10},
 390 { "sync",       0x00000400, 0xffffffff, "", pa10},
 391 { "syncdma",    0x00100400, 0xffffffff, "", pa10},
 392 { "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t", pa10},
 393 { "prober",     0x04001180, 0xfc003fe0, "(b),x,t", pa10},
 394 { "proberi",    0x04003180, 0xfc003fe0, "(s,b),R,t", pa10},
 395 { "proberi",    0x04003180, 0xfc003fe0, "(b),R,t", pa10},
 396 { "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10},
 397 { "probew",     0x040011c0, 0xfc003fe0, "(b),x,t", pa10},
 398 { "probewi",    0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10},
 399 { "probewi",    0x040031c0, 0xfc003fe0, "(b),R,t", pa10},
 400 { "lpa",        0x04001340, 0xfc003fc0, "Zx(s,b),t", pa10},
 401 { "lpa",        0x04001340, 0xfc003fc0, "Zx(b),t", pa10},
 402 { "lha",        0x04001300, 0xfc003fc0, "Zx(s,b),t", pa10},
 403 { "lha",        0x04001300, 0xfc003fc0, "Zx(b),t", pa10},
 404 { "lci",        0x04001300, 0xfc003fe0, "x(s,b),t", pa10},
 405 { "lci",        0x04001300, 0xfc003fe0, "x(b),t", pa10},
 406 { "pdtlb",      0x04001200, 0xfc003fdf, "Zx(s,b)", pa10},
 407 { "pdtlb",      0x04001200, 0xfc003fdf, "Zx(b)", pa10},
 408 { "pitlb",      0x04000200, 0xfc001fdf, "Zx(S,b)", pa10},
 409 { "pitlb",      0x04000200, 0xfc001fdf, "Zx(b)", pa10},
 410 { "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(s,b)", pa10},
 411 { "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(b)", pa10},
 412 { "pitlbe",     0x04000240, 0xfc001fdf, "Zx(S,b)", pa10},
 413 { "pitlbe",     0x04000240, 0xfc001fdf, "Zx(b)", pa10},
 414 { "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)", pa10},
 415 { "idtlba",     0x04001040, 0xfc003fff, "x,(b)", pa10},
 416 { "iitlba",     0x04000040, 0xfc001fff, "x,(S,b)", pa10},
 417 { "iitlba",     0x04000040, 0xfc001fff, "x,(b)", pa10},
 418 { "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)", pa10},
 419 { "idtlbp",     0x04001000, 0xfc003fff, "x,(b)", pa10},
 420 { "iitlbp",     0x04000000, 0xfc001fff, "x,(S,b)", pa10},
 421 { "iitlbp",     0x04000000, 0xfc001fff, "x,(b)", pa10},
 422 { "pdc",        0x04001380, 0xfc003fdf, "Zx(s,b)", pa10},
 423 { "pdc",        0x04001380, 0xfc003fdf, "Zx(b)", pa10},
 424 { "fdc",        0x04001280, 0xfc003fdf, "Zx(s,b)", pa10},
 425 { "fdc",        0x04001280, 0xfc003fdf, "Zx(b)", pa10},
 426 { "fic",        0x04000280, 0xfc001fdf, "Zx(S,b)", pa10},
 427 { "fic",        0x04000280, 0xfc001fdf, "Zx(b)", pa10},
 428 { "fdce",       0x040012c0, 0xfc003fdf, "Zx(s,b)", pa10},
 429 { "fdce",       0x040012c0, 0xfc003fdf, "Zx(b)", pa10},
 430 { "fice",       0x040002c0, 0xfc001fdf, "Zx(S,b)", pa10},
 431 { "fice",       0x040002c0, 0xfc001fdf, "Zx(b)", pa10},
 432 { "diag",       0x14000000, 0xfc000000, "D", pa10},
 433
 434 /* These may be specific to certain versions of the PA.  Joel claimed
 435    they were 72000 (7200?) specific.  However, I'm almost certain the
 436    mtcpu/mfcpu were undocumented, but available in the older 700 machines.  */
 437 { "mtcpu",      0x14001600, 0xfc00ffff, "x,^"},
 438 { "mfcpu",      0x14001A00, 0xfc00ffff, "^,x"},
 439 { "tocen",      0x14403600, 0xffffffff, ""},
 440 { "tocdis",     0x14401620, 0xffffffff, ""},
 441 { "shdwgr",     0x14402600, 0xffffffff, ""},
 442 { "grshdw",     0x14400620, 0xffffffff, ""},
 443
 444 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
 445    the Timex FPU or the Mustang ERS (not sure which) manual.  */
 446 { "gfw",        0x04001680, 0xfc003fdf, "Zx(s,b)", pa11},
 447 { "gfw",        0x04001680, 0xfc003fdf, "Zx(b)", pa11},
 448 { "gfr",        0x04001a80, 0xfc003fdf, "Zx(s,b)", pa11},
 449 { "gfr",        0x04001a80, 0xfc003fdf, "Zx(b)", pa11},
 450
 451 /* Floating Point Coprocessor Instructions */
 452
 453 { "fldwx",      0x24000000, 0xfc001f80, "cx(s,b),v", pa10},
 454 { "fldwx",      0x24000000, 0xfc001f80, "cx(b),v", pa10},
 455 { "flddx",      0x2c000000, 0xfc001fc0, "cx(s,b),y", pa10},
 456 { "flddx",      0x2c000000, 0xfc001fc0, "cx(b),y", pa10},
 457 { "fstwx",      0x24000200, 0xfc001f80, "cv,x(s,b)", pa10},
 458 { "fstwx",      0x24000200, 0xfc001f80, "cv,x(b)", pa10},
 459 { "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(s,b)", pa10},
 460 { "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(b)", pa10},
 461 { "fstqx",      0x3c000200, 0xfc001fc0, "cy,x(s,b)", pa10},
 462 { "fstqx",      0x3c000200, 0xfc001fc0, "cy,x(b)", pa10},
 463 { "fldws",      0x24001000, 0xfc001f80, "C5(s,b),v", pa10},
 464 { "fldws",      0x24001000, 0xfc001f80, "C5(b),v", pa10},
 465 { "fldds",      0x2c001000, 0xfc001fc0, "C5(s,b),y", pa10},
 466 { "fldds",      0x2c001000, 0xfc001fc0, "C5(b),y", pa10},
 467 { "fstws",      0x24001200, 0xfc001f80, "Cv,5(s,b)", pa10},
 468 { "fstws",      0x24001200, 0xfc001f80, "Cv,5(b)", pa10},
 469 { "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(s,b)", pa10},
 470 { "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(b)", pa10},
 471 { "fstqs",      0x3c001200, 0xfc001fc0, "Cy,5(s,b)", pa10},
 472 { "fstqs",      0x3c001200, 0xfc001fc0, "Cy,5(b)", pa10},
 473 { "fadd",       0x30000600, 0xfc00e7e0, "FE,X,v", pa10},
 474 { "fadd",       0x38000600, 0xfc00e720, "IJ,K,v", pa10},
 475 { "fsub",       0x30002600, 0xfc00e7e0, "FE,X,v", pa10},
 476 { "fsub",       0x38002600, 0xfc00e720, "IJ,K,v", pa10},
 477 { "fmpy",       0x30004600, 0xfc00e7e0, "FE,X,v", pa10},
 478 { "fmpy",       0x38004600, 0xfc00e720, "IJ,K,v", pa10},
 479 { "fdiv",       0x30006600, 0xfc00e7e0, "FE,X,v", pa10},
 480 { "fdiv",       0x38006600, 0xfc00e720, "IJ,K,v", pa10},
 481 { "fsqrt",      0x30008000, 0xfc1fe7e0, "FE,v", pa10},
 482 { "fsqrt",      0x38008000, 0xfc1fe720, "FJ,v", pa10},
 483 { "fabs",       0x30006000, 0xfc1fe7e0, "FE,v", pa10},
 484 { "fabs",       0x38006000, 0xfc1fe720, "FJ,v", pa10},
 485 { "frem",       0x30008600, 0xfc00e7e0, "FE,X,v", pa10},
 486 { "frem",       0x38008600, 0xfc00e720, "FJ,K,v", pa10},
 487 { "frnd",       0x3000a000, 0xfc1fe7e0, "FE,v", pa10},
 488 { "frnd",       0x3800a000, 0xfc1fe720, "FJ,v", pa10},
 489 { "fcpy",       0x30004000, 0xfc1fe7e0, "FE,v", pa10},
 490 { "fcpy",       0x38004000, 0xfc1fe720, "FJ,v", pa10},
 491 { "fcnvff",     0x30000200, 0xfc1f87e0, "FGE,v", pa10},
 492 { "fcnvff",     0x38000200, 0xfc1f8720, "FGJ,v", pa10},
 493 { "fcnvxf",     0x30008200, 0xfc1f87e0, "FGE,v", pa10},
 494 { "fcnvxf",     0x38008200, 0xfc1f8720, "FGJ,v", pa10},
 495 { "fcnvfx",     0x30010200, 0xfc1f87e0, "FGE,v", pa10},
 496 { "fcnvfx",     0x38010200, 0xfc1f8720, "FGJ,v", pa10},
 497 { "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGE,v", pa10},
 498 { "fcnvfxt",    0x38018200, 0xfc1f8720, "FGJ,v", pa10},
 499 { "fmpyfadd",   0xb8000000, 0xfc000020, "FJ,K,3,v", pa20, FLAG_STRICT},
 500 { "fmpynfadd",  0xb8000020, 0xfc000020, "FJ,K,3,v", pa20, FLAG_STRICT},
 501 { "fneg",       0x3000c000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
 502 { "fneg",       0x3800c000, 0xfc1fe720, "FJ,v", pa20, FLAG_STRICT},
 503 { "fnegabs",    0x3000e000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
 504 { "fnegabs",    0x3800e000, 0xfc1fe720, "FJ,v", pa20, FLAG_STRICT},
 505 { "fcmp",       0x30000400, 0xfc00e7e0, "F?fE,X", pa10},
 506 { "fcmp",       0x38000400, 0xfc00e720, "I?fJ,K", pa10},
 507 { "xmpyu",      0x38004700, 0xfc00e720, "J,K,v", pa11},
 508 { "fmpyadd",    0x18000000, 0xfc000000, "H4,6,7,9,8", pa11},
 509 { "fmpysub",    0x98000000, 0xfc000000, "H4,6,7,9,8", pa11},
 510 { "ftest",      0x30002420, 0xffffffff, "", pa10},
 511 { "fid",        0x30000000, 0xffffffff, "", pa11},
 512
 513
 514 /* Assist Instructions */
 515
 516 { "spop0",      0x10000000, 0xfc000600, "f,ON", pa10},
 517 { "spop1",      0x10000200, 0xfc000600, "f,oNt", pa10},
 518 { "spop2",      0x10000400, 0xfc000600, "f,1Nb", pa10},
 519 { "spop3",      0x10000600, 0xfc000600, "f,0Nx,b", pa10},
 520 { "copr",       0x30000000, 0xfc000000, "u,2N", pa10},
 521 { "cldwx",      0x24000000, 0xfc001e00, "ucx(s,b),t", pa10},
 522 { "cldwx",      0x24000000, 0xfc001e00, "ucx(b),t", pa10},
 523 { "clddx",      0x2c000000, 0xfc001e00, "ucx(s,b),t", pa10},
 524 { "clddx",      0x2c000000, 0xfc001e00, "ucx(b),t", pa10},
 525 { "cstwx",      0x24000200, 0xfc001e00, "uct,x(s,b)", pa10},
 526 { "cstwx",      0x24000200, 0xfc001e00, "uct,x(b)", pa10},
 527 { "cstdx",      0x2c000200, 0xfc001e00, "uct,x(s,b)", pa10},
 528 { "cstdx",      0x2c000200, 0xfc001e00, "uct,x(b)", pa10},
 529 { "cldws",      0x24001000, 0xfc001e00, "uC5(s,b),t", pa10},
 530 { "cldws",      0x24001000, 0xfc001e00, "uC5(b),t", pa10},
 531 { "cldds",      0x2c001000, 0xfc001e00, "uC5(s,b),t", pa10},
 532 { "cldds",      0x2c001000, 0xfc001e00, "uC5(b),t", pa10},
 533 { "cstws",      0x24001200, 0xfc001e00, "uCt,5(s,b)", pa10},
 534 { "cstws",      0x24001200, 0xfc001e00, "uCt,5(b)", pa10},
 535 { "cstds",      0x2c001200, 0xfc001e00, "uCt,5(s,b)", pa10},
 536 { "cstds",      0x2c001200, 0xfc001e00, "uCt,5(b)", pa10},
 537 };
 538
 539 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
 540
 541 /* SKV 12/18/92. Added some denotations for various operands. */
 542
 543 #define PA_IMM11_AT_31 'i'
 544 #define PA_IMM14_AT_31 'j'
 545 #define PA_IMM21_AT_31 'k'
 546 #define PA_DISP12 'w'
 547 #define PA_DISP17 'W'
 548
 549 #define N_HPPA_OPERAND_FORMATS 5