1 /* Table of opcodes for the PA-RISC.
2 Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc.
4 Contributed by the Center for Software Science at the
5 University of Utah (pa-gdb-bugs@cs.utah.edu).
7 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 1, or (at your option)
14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS or GDB; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 #if !defined(__STDC__) && !defined(const)
28 * Structure of an opcode table entry.
31 /* There are two kinds of delay slot nullification: normal which is
32 * controled by the nullification bit, and conditional, which depends
33 * on the direction of the branch and its success or failure.
35 * NONE is unfortunately #defined in the hiux system include files.
42 unsigned long int match
; /* Bits that must be set... */
43 unsigned long int mask
; /* ... in these bits. */
49 /* Enable/disable strict syntax checking. Not currently used, but will
50 be necessary for PA2.0 support in the future. */
51 #define FLAG_STRICT 0x1
54 All hppa opcodes are 32 bits.
56 The match component is a mask saying which bits must match a
57 particular opcode in order for an instruction to be an instance
60 The args component is a string containing one character for each operand of
61 the instruction. Characters used as a prefix allow any second character to
62 be used without conflicting with the main operand characters.
64 Bit positions in this description follow HP usage of lsb = 31,
67 In the args field, the following characters must match exactly:
71 In the args field, the following characters are unused:
73 ' " & - / 34 6789:;< > @'
77 Here are all the characters:
79 ' !"#$%&'()*+-,./0123456789:;<=>?@'
80 'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
81 'abcdefghijklmnopqrstuvwxyz{|}~'
84 x integer register field at 15.
85 b integer register field at 10.
86 t integer register field at 31.
87 a integer register field at 10 and 15 (for PERMH)
88 5 5 bit immediate at 15.
89 s 2 bit space specifier at 17.
90 S 3 bit space specifier at 18.
91 V 5 bit immediate value at 31
92 i 11 bit immediate value at 31
93 j 14 bit immediate value at 31
94 k 21 bit immediate value at 31
95 n nullification for branch instructions
96 N nullification for spop and copr instructions
97 w 12 bit branch displacement
98 W 17 bit branch displacement (PC relative)
99 X 22 bit branch displacement (PC relative)
100 z 17 bit branch displacement (just a number, not an address)
104 . 2 bit shift amount at 25
105 * 4 bit shift amount at 25
106 p 5 bit shift count at 26 (to support the SHD instruction) encoded as
108 ~ 6 bit shift count at 20,22:26 encoded as 63-~.
109 P 5 bit bit position at 26
110 T 5 bit field length at 31 (encoded as 32-T)
111 A 13 bit immediate at 18 (to support the BREAK instruction)
112 ^ like b, but describes a control register
113 ! sar (cr11) register
114 D 26 bit immediate at 31 (to support the DIAG instruction)
115 $ 9 bit immediate at 28 (to support POPBTS)
117 v 3 bit Special Function Unit identifier at 25
118 O 20 bit Special Function Unit operation split between 15 bits at 20
120 o 15 bit Special Function Unit operation at 20
121 2 22 bit Special Function Unit operation split between 17 bits at 20
123 1 15 bit Special Function Unit operation split between 10 bits at 20
125 0 10 bit Special Function Unit operation split between 5 bits at 20
127 u 3 bit coprocessor unit identifier at 25
128 F Source Floating Point Operand Format Completer encoded 2 bits at 20
129 I Source Floating Point Operand Format Completer encoded 1 bits at 20
130 (for 0xe format FP instructions)
131 G Destination Floating Point Operand Format Completer encoded 2 bits at 18
132 H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
133 (very similar to 'F')
135 r 5 bit immediate value at 31 (for the break instruction)
136 (very similar to V above, except the value is unsigned instead of
138 R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
139 (same as r above, except the value is in a different location)
140 U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
141 Q 5 bit immediate value at 10 (a bit position specified in
142 the bb instruction. It's the same as r above, except the
143 value is in a different location)
144 Z %r1 -- implicit target of addil instruction.
145 g ,gate completer for new syntax branch
146 l ,l completer for new syntax branch
147 M ,push completer for new syntax branch
148 L ,%r2 completer for new syntax branch
149 B ,pop completer for new syntax branch
150 { Source format completer for fcnv
151 _ Destination format completer for fcnv
153 = gfx tests for ftest
154 d 14bit offset for single precision FP long load/store.
155 # 14bit offset for double precision FP load long/store.
156 J Yet another 14bit offset with an unusual encoding.
157 K Yet another 14bit offset with an unusual encoding.
159 Completer operands all have 'c' as the prefix:
161 cx indexed load completer.
162 cm short load and store completer.
163 cq short load and store completer (like cm, but inserted into a
164 different location in the target instruction).
165 cs store bytes short completer.
166 cc Another load/store completer with a different encoding than the
169 cw read/write completer for PROBE
170 cW wide completer for MFCTL
171 cL local processor completer for cache control
172 cZ System Control Completer (to support LPA, LHA, etc.)
174 ci correction completer for DCOR
176 cy 32 bit add carry completer
177 cY 64 bit add carry completer
178 cv signed overflow trap completer
179 ct trap on condition completer for ADDI, SUB
180 cT trap on condition completer for UADDCM
181 cb 32 bit borrow completer for SUB
182 cB 64 bit borrow completer for SUB
184 ch left/right half completer
185 cH signed/unsigned saturation completer
186 cS signed/unsigned completer at 21
187 c* permutation completer
189 Condition operands all have '?' as the prefix:
191 ?f Floating point compare conditions (encoded as 5 bits at 31)
194 ?A 64 bit add conditions
195 ?@ add branch conditions followed by nullify
196 ?d non-negated add branch conditions
197 ?D negated add branch conditions
198 ?w wide mode non-negated add branch conditions
199 ?W wide mode negated add branch conditions
201 ?s compare/subtract conditions
202 ?S 64 bit compare/subtract conditions
203 ?t non-negated compare conditions
204 ?T negated compare conditions
205 ?r 64 bit non-negated compare conditions
206 ?R 64 bit negated compare conditions
207 ?Q 64 bit compare conditions for CMPIB instruction
208 ?n compare conditions followed by nullify
210 ?l logical conditions
211 ?L 64 bit logical conditions
213 ?b branch on bit conditions
214 ?B 64 bit branch on bit conditions
216 ?x shift/extract/deposit conditions
217 ?X 64 bit shift/extract/deposit conditions
218 ?y shift/extract/deposit conditions followed by nullify for conditional
222 ?U 64 bit unit conditions
224 Floating point registers all have 'f' as a prefix:
226 ft target register at 31
227 fT target register with L/R halves at 31
228 fa operand 1 register at 10
229 fA operand 1 register with L/R halves at 10
230 fX Same as fA, except prints a space before register during disasm
231 fb operand 2 register at 15
232 fB operand 2 register with L/R halves at 15
233 fC operand 3 register with L/R halves at 16:18,21:23
234 fe Like fT, but encoding is different.
236 Float registers for fmpyadd and fmpysub:
238 fi mult operand 1 register at 10
239 fj mult operand 2 register at 15
240 fk mult target register at 20
241 fl add/sub operand register at 25
242 fm add/sub target register at 31
247 /* List of characters not to put a space after. Note that
248 "," is included, as the "spopN" operations use literal
249 commas in their completer sections. */
250 static const char *const completer_chars
= ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
252 /* The order of the opcodes in this table is significant:
254 * The assembler requires that all instances of the same mnemonic must be
255 consecutive. If they aren't, the assembler will bomb at runtime.
257 * The disassembler should not care about the order of the opcodes. */
259 static const struct pa_opcode pa_opcodes
[] =
263 { "b", 0xe8002000, 0xfc00e000, "gnW,b", pa10
, FLAG_STRICT
},
264 { "b", 0xe8008000, 0xfc00e000, "lMnXL", pa20
, FLAG_STRICT
},
265 { "b", 0xe800a000, 0xfc00e000, "lnXL", pa20
, FLAG_STRICT
},
266 { "b", 0xe8000000, 0xfc00e000, "lnW,b", pa10
, FLAG_STRICT
},
267 { "b", 0xe8000000, 0xffe0e000, "nW", pa10
}, /* bl foo,r0 */
268 { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10
}, /* ldo val(r0),r */
269 { "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10
}, /* comib{tf}*/
270 /* This entry is for the disassembler only. It will never be used by
272 { "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10
}, /* comib{tf}*/
273 { "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10
}, /* comb{tf} */
274 /* This entry is for the disassembler only. It will never be used by
276 { "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10
}, /* comb{tf} */
277 { "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10
}, /* addb{tf} */
278 /* This entry is for the disassembler only. It will never be used by
280 { "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10
},
281 { "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10
}, /* addib{tf}*/
282 /* This entry is for the disassembler only. It will never be used by
284 { "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10
}, /* addib{tf}*/
285 { "nop", 0x08000240, 0xffffffff, "", pa10
}, /* or 0,0,0 */
286 { "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10
}, /* or r,0,t */
287 { "mtsar", 0x01601840, 0xffe0ffff, "x", pa10
}, /* mtctl r,cr11 */
289 /* Loads and Stores for integer registers. */
290 { "ldd", 0x0c0000c0, 0xfc001fc0, "cxx(s,b),t", pa20
, FLAG_STRICT
},
291 { "ldd", 0x0c0000c0, 0xfc001fc0, "cxx(b),t", pa20
, FLAG_STRICT
},
292 { "ldd", 0x0c0010c0, 0xfc001fc0, "cm5(s,b),t", pa20
, FLAG_STRICT
},
293 { "ldd", 0x0c0010c0, 0xfc001fc0, "cm5(b),t", pa20
, FLAG_STRICT
},
294 { "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20
, FLAG_STRICT
},
295 { "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20
, FLAG_STRICT
},
296 { "ldw", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10
, FLAG_STRICT
},
297 { "ldw", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10
, FLAG_STRICT
},
298 { "ldw", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10
, FLAG_STRICT
},
299 { "ldw", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10
, FLAG_STRICT
},
300 { "ldw", 0x4c000000, 0xfc000000, "ccJ(s,b),x", pa10
, FLAG_STRICT
},
301 { "ldw", 0x4c000000, 0xfc000000, "ccJ(b),x", pa10
, FLAG_STRICT
},
302 { "ldw", 0x5c000004, 0xfc000006, "ccK(s,b),x", pa20
, FLAG_STRICT
},
303 { "ldw", 0x5c000004, 0xfc000006, "ccK(b),x", pa20
, FLAG_STRICT
},
304 { "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10
},
305 { "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10
},
306 { "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10
},
307 { "ldh", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10
, FLAG_STRICT
},
308 { "ldh", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10
, FLAG_STRICT
},
309 { "ldh", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10
, FLAG_STRICT
},
310 { "ldh", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10
, FLAG_STRICT
},
311 { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10
},
312 { "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10
},
313 { "ldb", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10
, FLAG_STRICT
},
314 { "ldb", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10
, FLAG_STRICT
},
315 { "ldb", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10
, FLAG_STRICT
},
316 { "ldb", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10
, FLAG_STRICT
},
317 { "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10
},
318 { "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10
},
319 { "std", 0x0c0012c0, 0xfc001fc0, "cmx,V(s,b)", pa20
, FLAG_STRICT
},
320 { "std", 0x0c0012c0, 0xfc001fc0, "cmx,V(b)", pa20
, FLAG_STRICT
},
321 { "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20
, FLAG_STRICT
},
322 { "std", 0x70000000, 0xfc000002, "cqx,#(b)", pa20
, FLAG_STRICT
},
323 { "stw", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10
, FLAG_STRICT
},
324 { "stw", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10
, FLAG_STRICT
},
325 { "stw", 0x6c000000, 0xfc000000, "ccx,J(s,b)", pa10
, FLAG_STRICT
},
326 { "stw", 0x6c000000, 0xfc000000, "ccx,J(b)", pa10
, FLAG_STRICT
},
327 { "stw", 0x7c000004, 0xfc000006, "ccx,K(s,b)", pa20
, FLAG_STRICT
},
328 { "stw", 0x7c000004, 0xfc000006, "ccx,K(b)", pa20
, FLAG_STRICT
},
329 { "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10
},
330 { "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10
},
331 { "sth", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10
, FLAG_STRICT
},
332 { "sth", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10
, FLAG_STRICT
},
333 { "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10
},
334 { "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10
},
335 { "stb", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10
, FLAG_STRICT
},
336 { "stb", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10
, FLAG_STRICT
},
337 { "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10
},
338 { "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10
},
339 { "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10
},
340 { "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10
},
341 { "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10
},
342 { "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10
},
343 { "ldwx", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10
},
344 { "ldwx", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10
},
345 { "ldhx", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10
},
346 { "ldhx", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10
},
347 { "ldbx", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10
},
348 { "ldbx", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10
},
349 { "ldwa", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10
, FLAG_STRICT
},
350 { "ldwa", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10
, FLAG_STRICT
},
351 { "ldcw", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10
, FLAG_STRICT
},
352 { "ldcw", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10
, FLAG_STRICT
},
353 { "ldcw", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10
, FLAG_STRICT
},
354 { "ldcw", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10
, FLAG_STRICT
},
355 { "stwa", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10
, FLAG_STRICT
},
356 { "stby", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10
, FLAG_STRICT
},
357 { "stby", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10
, FLAG_STRICT
},
358 { "ldda", 0x0c000100, 0xfc00dfc0, "cxx(b),t", pa20
, FLAG_STRICT
},
359 { "ldda", 0x0c001100, 0xfc00dfc0, "cm5(b),t", pa20
, FLAG_STRICT
},
360 { "ldcd", 0x0c000140, 0xfc001fc0, "cxx(s,b),t", pa20
, FLAG_STRICT
},
361 { "ldcd", 0x0c000140, 0xfc001fc0, "cxx(b),t", pa20
, FLAG_STRICT
},
362 { "ldcd", 0x0c001140, 0xfc001fc0, "cm5(s,b),t", pa20
, FLAG_STRICT
},
363 { "ldcd", 0x0c001140, 0xfc001fc0, "cm5(b),t", pa20
, FLAG_STRICT
},
364 { "stda", 0x0c0013c0, 0xfc001fc0, "cmx,V(s,b)", pa20
, FLAG_STRICT
},
365 { "stda", 0x0c0013c0, 0xfc001fc0, "cmx,V(b)", pa20
, FLAG_STRICT
},
366 { "ldwax", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10
},
367 { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10
},
368 { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10
},
369 { "ldws", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10
},
370 { "ldws", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10
},
371 { "ldhs", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10
},
372 { "ldhs", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10
},
373 { "ldbs", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10
},
374 { "ldbs", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10
},
375 { "ldwas", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10
},
376 { "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10
},
377 { "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10
},
378 { "stws", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10
},
379 { "stws", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10
},
380 { "sths", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10
},
381 { "sths", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10
},
382 { "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10
},
383 { "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10
},
384 { "stwas", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10
},
385 { "stdby", 0x0c001340, 0xfc001fc0, "csx,V(s,b)", pa20
, FLAG_STRICT
},
386 { "stdby", 0x0c001340, 0xfc001fc0, "csx,V(b)", pa20
, FLAG_STRICT
},
387 { "stbys", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10
},
388 { "stbys", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10
},
390 /* Immediate instructions. */
391 { "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10
},
392 { "ldil", 0x20000000, 0xfc000000, "k,b", pa10
},
393 { "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10
},
394 { "addil", 0x28000000, 0xfc000000, "k,b", pa10
},
396 /* Branching instructions. */
397 { "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10
},
398 { "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10
},
399 { "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10
},
400 { "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10
},
401 { "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10
},
402 { "bve", 0xe800f000, 0xfc00fffe, "ln(b)L", pa20
, FLAG_STRICT
},
403 { "bve", 0xe800f001, 0xfc00fffe, "lMn(b)L", pa20
, FLAG_STRICT
},
404 { "bve", 0xe800f001, 0xfc00fffe, "Bn(b)", pa20
, FLAG_STRICT
},
405 { "bve", 0xe800d000, 0xfc00fffe, "n(b)", pa20
, FLAG_STRICT
},
406 { "be", 0xe4000000, 0xfc000000, "lnz(S,b)", pa10
, FLAG_STRICT
},
407 { "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10
, FLAG_STRICT
},
408 { "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10
},
409 { "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10
},
410 { "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10
},
411 { "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10
},
412 { "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10
},
413 { "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10
},
414 { "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10
},
415 { "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10
},
416 { "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10
},
417 { "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10
},
418 { "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10
},
419 { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10
},
420 { "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20
, FLAG_STRICT
},
421 { "bb", 0xc4006000, 0xfc006000, "?Bnx,Q,w", pa20
, FLAG_STRICT
},
422 { "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10
, FLAG_STRICT
},
423 { "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10
},
424 { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10
},
425 { "clrbts", 0xe8004005, 0xffffffff, "", pa20
, FLAG_STRICT
},
426 { "popbts", 0xe8004005, 0xfffff007, "$", pa20
, FLAG_STRICT
},
427 { "pushnom", 0xe8004001, 0xffffffff, "", pa20
, FLAG_STRICT
},
428 { "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20
, FLAG_STRICT
},
430 /* Computation Instructions */
432 { "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20
, FLAG_STRICT
},
433 { "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10
, FLAG_STRICT
},
434 { "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10
},
435 { "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20
, FLAG_STRICT
},
436 { "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10
},
437 { "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20
, FLAG_STRICT
},
438 { "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10
},
439 { "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20
, FLAG_STRICT
},
440 { "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10
},
441 { "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20
, FLAG_STRICT
},
442 { "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10
},
443 { "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20
, FLAG_STRICT
},
444 { "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10
},
445 { "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20
, FLAG_STRICT
},
446 { "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10
, FLAG_STRICT
},
447 { "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10
},
448 { "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10
},
449 { "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20
, FLAG_STRICT
},
450 { "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10
, FLAG_STRICT
},
451 { "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10
},
452 { "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10
},
453 { "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10
, FLAG_STRICT
},
454 { "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10
, FLAG_STRICT
},
455 { "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10
},
456 { "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10
},
457 { "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10
},
458 { "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10
},
459 { "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20
, FLAG_STRICT
},
460 { "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10
, FLAG_STRICT
},
461 { "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20
, FLAG_STRICT
},
462 { "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10
, FLAG_STRICT
},
463 { "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10
},
464 { "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10
},
465 { "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10
},
466 { "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10
},
467 { "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10
},
468 { "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20
, FLAG_STRICT
},
469 { "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10
, FLAG_STRICT
},
470 { "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20
, FLAG_STRICT
},
471 { "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10
, FLAG_STRICT
},
472 { "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20
, FLAG_STRICT
},
473 { "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10
, FLAG_STRICT
},
474 { "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10
},
475 { "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10
},
476 { "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10
},
477 { "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10
},
478 { "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10
},
479 { "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10
},
480 { "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10
},
481 { "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10
, FLAG_STRICT
},
482 { "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10
},
483 { "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10
},
484 { "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20
, FLAG_STRICT
},
485 { "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10
, FLAG_STRICT
},
486 { "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10
},
487 { "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20
, FLAG_STRICT
},
488 { "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10
, FLAG_STRICT
},
489 { "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10
},
490 { "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10
},
491 { "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10
},
492 { "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10
},
493 { "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10
},
494 { "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10
},
495 { "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10
},
496 { "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10
},
497 { "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10
},
499 /* Subword Operation Instructions */
501 { "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20
, FLAG_STRICT
},
502 { "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20
, FLAG_STRICT
},
503 { "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20
, FLAG_STRICT
},
504 { "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20
, FLAG_STRICT
},
505 { "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20
, FLAG_STRICT
},
506 { "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20
, FLAG_STRICT
},
507 { "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20
, FLAG_STRICT
},
508 { "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20
, FLAG_STRICT
},
509 { "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20
, FLAG_STRICT
},
510 { "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20
, FLAG_STRICT
},
513 /* Extract and Deposit Instructions */
515 { "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20
, FLAG_STRICT
},
516 { "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20
, FLAG_STRICT
},
517 { "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10
, FLAG_STRICT
},
518 { "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10
, FLAG_STRICT
},
519 { "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10
},
520 { "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10
},
521 { "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20
, FLAG_STRICT
},
522 { "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20
, FLAG_STRICT
},
523 { "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10
, FLAG_STRICT
},
524 { "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10
, FLAG_STRICT
},
525 { "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10
},
526 { "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10
},
527 { "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10
},
528 { "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10
},
529 { "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20
, FLAG_STRICT
},
530 { "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20
, FLAG_STRICT
},
531 { "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20
, FLAG_STRICT
},
532 { "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20
, FLAG_STRICT
},
533 { "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10
, FLAG_STRICT
},
534 { "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10
, FLAG_STRICT
},
535 { "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10
, FLAG_STRICT
},
536 { "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10
, FLAG_STRICT
},
537 { "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10
},
538 { "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10
},
539 { "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10
},
540 { "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10
},
541 { "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10
},
542 { "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10
},
543 { "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10
},
544 { "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10
},
546 /* System Control Instructions */
548 { "break", 0x00000000, 0xfc001fe0, "r,A", pa10
},
549 { "rfi", 0x00000c00, 0xffffff1f, "cr", pa10
, FLAG_STRICT
},
550 { "rfi", 0x00000c00, 0xffffffff, "", pa10
},
551 { "rfir", 0x00000ca0, 0xffffffff, "", pa11
},
552 { "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20
, FLAG_STRICT
},
553 { "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10
},
554 { "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20
, FLAG_STRICT
},
555 { "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10
},
556 { "mtsm", 0x00001860, 0xffe0ffff, "x", pa10
},
557 { "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10
},
558 { "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10
},
559 { "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10
},
560 { "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10
},
561 { "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20
, FLAG_STRICT
},
562 { "mfia", 0x000014A0, 0xffffffe0, "t", pa20
, FLAG_STRICT
},
563 { "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10
},
564 { "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20
, FLAG_STRICT
},
565 { "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10
},
566 { "sync", 0x00000400, 0xffffffff, "", pa10
},
567 { "syncdma", 0x00100400, 0xffffffff, "", pa10
},
568 { "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10
, FLAG_STRICT
},
569 { "probe", 0x04001180, 0xfc003fa0, "cw(b),x,t", pa10
, FLAG_STRICT
},
570 { "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10
, FLAG_STRICT
},
571 { "probei", 0x04003180, 0xfc003fa0, "cw(b),R,t", pa10
, FLAG_STRICT
},
572 { "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10
},
573 { "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10
},
574 { "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10
},
575 { "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10
},
576 { "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10
},
577 { "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10
},
578 { "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10
},
579 { "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10
},
580 { "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10
},
581 { "lpa", 0x04001340, 0xfc003fc0, "cZx(b),t", pa10
},
582 { "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10
},
583 { "lha", 0x04001300, 0xfc003fc0, "cZx(b),t", pa10
},
584 { "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10
},
585 { "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10
},
586 { "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20
, FLAG_STRICT
},
587 { "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(b)", pa20
, FLAG_STRICT
},
588 { "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10
},
589 { "pdtlb", 0x04001200, 0xfc003fdf, "cZx(b)", pa10
},
590 { "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20
, FLAG_STRICT
},
591 { "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(b)", pa20
, FLAG_STRICT
},
592 { "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10
},
593 { "pitlb", 0x04000200, 0xfc001fdf, "cZx(b)", pa10
},
594 { "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10
},
595 { "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(b)", pa10
},
596 { "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10
},
597 { "pitlbe", 0x04000240, 0xfc001fdf, "cZx(b)", pa10
},
598 { "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10
},
599 { "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10
},
600 { "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10
},
601 { "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10
},
602 { "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10
},
603 { "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10
},
604 { "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10
},
605 { "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10
},
606 { "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10
},
607 { "pdc", 0x04001380, 0xfc003fdf, "cZx(b)", pa10
},
608 { "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10
},
609 { "fdc", 0x04001280, 0xfc003fdf, "cZx(b)", pa10
},
610 { "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10
},
611 { "fic", 0x04000280, 0xfc001fdf, "cZx(b)", pa10
},
612 { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10
},
613 { "fdce", 0x040012c0, 0xfc003fdf, "cZx(b)", pa10
},
614 { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10
},
615 { "fice", 0x040002c0, 0xfc001fdf, "cZx(b)", pa10
},
616 { "diag", 0x14000000, 0xfc000000, "D", pa10
},
617 { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20
, FLAG_STRICT
},
618 { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20
, FLAG_STRICT
},
620 /* These may be specific to certain versions of the PA. Joel claimed
621 they were 72000 (7200?) specific. However, I'm almost certain the
622 mtcpu/mfcpu were undocumented, but available in the older 700 machines. */
623 { "mtcpu", 0x14001600, 0xfc00ffff, "x,^"},
624 { "mfcpu", 0x14001A00, 0xfc00ffff, "^,x"},
625 { "tocen", 0x14403600, 0xffffffff, ""},
626 { "tocdis", 0x14401620, 0xffffffff, ""},
627 { "shdwgr", 0x14402600, 0xffffffff, ""},
628 { "grshdw", 0x14400620, 0xffffffff, ""},
630 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
631 the Timex FPU or the Mustang ERS (not sure which) manual. */
632 { "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11
},
633 { "gfw", 0x04001680, 0xfc003fdf, "cZx(b)", pa11
},
634 { "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11
},
635 { "gfr", 0x04001a80, 0xfc003fdf, "cZx(b)", pa11
},
637 /* Floating Point Coprocessor Instructions */
639 { "fldw", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10
, FLAG_STRICT
},
640 { "fldw", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10
, FLAG_STRICT
},
641 { "fldw", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10
, FLAG_STRICT
},
642 { "fldw", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10
, FLAG_STRICT
},
643 { "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20
, FLAG_STRICT
},
644 { "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20
, FLAG_STRICT
},
645 { "fldw", 0x58000000, 0xfc000004, "cJd(s,b),fe", pa20
, FLAG_STRICT
},
646 { "fldw", 0x58000000, 0xfc000004, "cJd(b),fe", pa20
, FLAG_STRICT
},
647 { "fldd", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10
, FLAG_STRICT
},
648 { "fldd", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10
, FLAG_STRICT
},
649 { "fldd", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10
, FLAG_STRICT
},
650 { "fldd", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10
, FLAG_STRICT
},
651 { "fldd", 0x50000002, 0xfc000002, "cq#(s,b),x", pa20
, FLAG_STRICT
},
652 { "fldd", 0x50000002, 0xfc000002, "cq#(b),x", pa20
, FLAG_STRICT
},
653 { "fstw", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10
, FLAG_STRICT
},
654 { "fstw", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10
, FLAG_STRICT
},
655 { "fstw", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10
, FLAG_STRICT
},
656 { "fstw", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10
, FLAG_STRICT
},
657 { "fstw", 0x78000000, 0xfc000004, "fe,d(s,b)", pa20
, FLAG_STRICT
},
658 { "fstw", 0x78000000, 0xfc000004, "fe,d(b)", pa20
, FLAG_STRICT
},
659 { "fstw", 0x7c000000, 0xfc000004, "cJfe,d(s,b)", pa20
, FLAG_STRICT
},
660 { "fstw", 0x7c000000, 0xfc000004, "cJfe,d(b)", pa20
, FLAG_STRICT
},
661 { "fstd", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10
, FLAG_STRICT
},
662 { "fstd", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10
, FLAG_STRICT
},
663 { "fstd", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10
, FLAG_STRICT
},
664 { "fstd", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10
, FLAG_STRICT
},
665 { "fstd", 0x70000002, 0xfc000002, "cqx,#(s,b)", pa20
, FLAG_STRICT
},
666 { "fstd", 0x70000002, 0xfc000002, "cqx,#(b)", pa20
, FLAG_STRICT
},
667 { "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10
},
668 { "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10
},
669 { "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10
},
670 { "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10
},
671 { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10
},
672 { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10
},
673 { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10
},
674 { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10
},
675 { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10
},
676 { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10
},
677 { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10
},
678 { "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10
},
679 { "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10
},
680 { "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10
},
681 { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10
},
682 { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10
},
683 { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10
},
684 { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10
},
685 { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10
},
686 { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10
},
687 { "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10
},
688 { "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10
},
689 { "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10
},
690 { "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10
},
691 { "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10
},
692 { "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10
},
693 { "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10
},
694 { "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10
},
695 { "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10
},
696 { "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10
},
697 { "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10
},
698 { "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10
},
699 { "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10
},
700 { "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10
},
701 { "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10
},
702 { "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10
},
703 { "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10
},
704 { "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10
},
705 { "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10
},
706 { "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10
},
707 { "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10
},
708 { "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10
},
709 { "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10
},
710 { "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10
},
711 { "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10
},
712 { "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10
},
713 { "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20
, FLAG_STRICT
},
714 { "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20
, FLAG_STRICT
},
715 { "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20
, FLAG_STRICT
},
716 { "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20
, FLAG_STRICT
},
717 { "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20
, FLAG_STRICT
},
718 { "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20
, FLAG_STRICT
},
719 { "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20
, FLAG_STRICT
},
720 { "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20
, FLAG_STRICT
},
721 { "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20
, FLAG_STRICT
},
722 { "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20
, FLAG_STRICT
},
723 { "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10
},
724 { "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10
},
725 { "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11
},
726 { "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11
},
727 { "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11
},
728 { "ftest", 0x30002420, 0xffffffe0, ",=", pa20
, FLAG_STRICT
},
729 { "ftest", 0x30000420, 0xffff1fff, "m", pa20
, FLAG_STRICT
},
730 { "ftest", 0x30002420, 0xffffffff, "", pa10
},
731 { "fid", 0x30000000, 0xffffffff, "", pa11
},
733 /* Performance Monitor Instructions */
735 { "pmdis", 0x30000280, 0xffffffdf, "N", pa20
, FLAG_STRICT
},
736 { "pmenb", 0x30000680, 0xffffffff, "", pa20
, FLAG_STRICT
},
738 /* Assist Instructions */
740 { "spop0", 0x10000000, 0xfc000600, "v,ON", pa10
},
741 { "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10
},
742 { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10
},
743 { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10
},
744 { "copr", 0x30000000, 0xfc000000, "u,2N", pa10
},
745 { "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10
},
746 { "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10
},
747 { "clddx", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10
},
748 { "clddx", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10
},
749 { "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10
},
750 { "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10
},
751 { "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10
},
752 { "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10
},
753 { "cldws", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10
},
754 { "cldws", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10
},
755 { "cldds", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10
},
756 { "cldds", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa10
},
757 { "cstws", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10
},
758 { "cstws", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10
},
759 { "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10
},
760 { "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10
},
761 { "cldw", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10
, FLAG_STRICT
},
762 { "cldw", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10
, FLAG_STRICT
},
763 { "cldw", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10
, FLAG_STRICT
},
764 { "cldw", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10
, FLAG_STRICT
},
765 { "cldd", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10
, FLAG_STRICT
},
766 { "cldd", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10
, FLAG_STRICT
},
767 { "cldd", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10
, FLAG_STRICT
},
768 { "cldd", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa20
, FLAG_STRICT
},
769 { "cstw", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10
, FLAG_STRICT
},
770 { "cstw", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10
, FLAG_STRICT
},
771 { "cstw", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10
, FLAG_STRICT
},
772 { "cstw", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10
, FLAG_STRICT
},
773 { "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10
, FLAG_STRICT
},
774 { "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10
, FLAG_STRICT
},
775 { "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10
, FLAG_STRICT
},
776 { "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10
, FLAG_STRICT
},
779 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
781 /* SKV 12/18/92. Added some denotations for various operands. */
783 #define PA_IMM11_AT_31 'i'
784 #define PA_IMM14_AT_31 'j'
785 #define PA_IMM21_AT_31 'k'
786 #define PA_DISP12 'w'
787 #define PA_DISP17 'W'
789 #define N_HPPA_OPERAND_FORMATS 5
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