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Extend the i386 gas testsuite to do some tests for intel_syntax. Fix all
[deliverable/binutils-gdb.git] / include / opcode / i386.h
1 /* opcode/i386.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation.
3
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20 /* The UnixWare assembler, and probably other AT&T derived ix86 Unix
21 assemblers, generate floating point instructions with reversed
22 source and destination registers in certain cases. Unfortunately,
23 gcc and possibly many other programs use this reversed syntax, so
24 we're stuck with it.
25
26 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
27 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
28 the expected st(3) = st(3) - st
29
30 This happens with all the non-commutative arithmetic floating point
31 operations with two register operands, where the source register is
32 %st, and destination register is %st(i). See FloatDR below.
33
34 The affected opcode map is dceX, dcfX, deeX, defX. */
35
36 #ifndef UNIXWARE_COMPAT
37 /* Set non-zero for broken, compatible instructions. Set to zero for
38 non-broken opcodes at your peril. gcc generates UnixWare
39 compatible instructions. */
40 #define UNIXWARE_COMPAT 1
41 #endif
42
43
44 static const template i386_optab[] = {
45
46 #define X None
47 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
48 #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
49 #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
50 #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf)
51 #define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
52 #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf)
53 #define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf)
54 #define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf)
55 #define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf)
56 #define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf)
57 #define sld_Suf (No_bSuf|No_wSuf|No_xSuf)
58 #define sldx_Suf (No_bSuf|No_wSuf)
59 #define bwl_Suf (No_sSuf|No_dSuf|No_xSuf)
60 #define bwld_Suf (No_sSuf|No_xSuf)
61 #define FP (NoSuf|IgnoreSize)
62 #define l_FP (l_Suf|IgnoreSize)
63 #define d_FP (d_Suf|IgnoreSize)
64 #define x_FP (x_Suf|IgnoreSize)
65 #define sl_FP (sl_Suf|IgnoreSize)
66 #define sld_FP (sld_Suf|IgnoreSize)
67 #define sldx_FP (sldx_Suf|IgnoreSize)
68 #if UNIXWARE_COMPAT
69 /* Someone forgot that the FloatR bit reverses the operation when not
70 equal to the FloatD bit. ie. Changing only FloatD results in the
71 destination being swapped *and* the direction being reversed. */
72 #define FloatDR FloatD
73 #else
74 #define FloatDR (FloatD|FloatR)
75 #endif
76
77 /* move instructions */
78 #define MOV_AX_DISP32 0xa0
79 { "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
80 { "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
81 { "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } },
82 { "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } },
83 /* The next two instructions accept WordReg so that a segment register
84 can be copied to a 32 bit register, and vice versa, without using a
85 size prefix. When moving to a 32 bit register, the upper 16 bits
86 are set to an implementation defined value (on the Pentium Pro,
87 the implementation defined value is zero). */
88 { "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } },
89 { "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } },
90 /* move to/from control debug registers */
91 { "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} },
92 { "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} },
93 { "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
94
95 /* move with sign extend */
96 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
97 conflict with the "movs" string move instruction. */
98 {"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
99 {"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
100 {"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
101 /* Intel Syntax */
102 {"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
103 {"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
104
105 /* move with zero extend */
106 {"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
107 {"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
108 /* Intel Syntax */
109 {"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
110 {"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
111
112 /* push instructions */
113 {"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
114 {"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
115 {"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
116 {"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
117 {"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
118 {"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
119 /* push all */
120 {"pusha", 0, 0x60, X, wl_Suf|DefaultSize, { 0, 0, 0 } },
121
122 /* pop instructions */
123 {"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
124 {"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
125 #define POP_SEG_SHORT 0x07
126 {"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
127 {"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
128 /* pop all */
129 {"popa", 0, 0x61, X, wl_Suf|DefaultSize, { 0, 0, 0 } },
130
131 /* xchg exchange instructions
132 xchg commutes: we allow both operand orders */
133 {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
134 {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
135 {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
136 {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
137
138 /* in/out from ports */
139 {"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } },
140 {"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
141 {"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } },
142 {"in", 1, 0xec, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
143 {"out", 2, 0xe6, X, bwl_Suf|W, { Acc, Imm8, 0 } },
144 {"out", 2, 0xee, X, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
145 {"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } },
146 {"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
147
148 /* load effective address */
149 {"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } },
150
151 /* load segment registers from memory */
152 {"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
153 {"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
154 {"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
155 {"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
156 {"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
157
158 /* flags register instructions */
159 {"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} },
160 {"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} },
161 {"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} },
162 {"clts", 0, 0x0f06, X, NoSuf, { 0, 0, 0} },
163 {"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} },
164 {"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} },
165 {"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} },
166 {"pushf", 0, 0x9c, X, wl_Suf|DefaultSize, { 0, 0, 0} },
167 {"popf", 0, 0x9d, X, wl_Suf|DefaultSize, { 0, 0, 0} },
168 {"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} },
169 {"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} },
170 {"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} },
171
172 /* arithmetic */
173 {"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
174 {"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
175 {"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} },
176 {"add", 2, 0x80, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
177
178 {"inc", 1, 0x40, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
179 {"inc", 1, 0xfe, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
180
181 {"sub", 2, 0x28, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
182 {"sub", 2, 0x83, 5, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
183 {"sub", 2, 0x2c, X, bwl_Suf|W, { Imm, Acc, 0} },
184 {"sub", 2, 0x80, 5, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
185
186 {"dec", 1, 0x48, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
187 {"dec", 1, 0xfe, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
188
189 {"sbb", 2, 0x18, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
190 {"sbb", 2, 0x83, 3, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
191 {"sbb", 2, 0x1c, X, bwl_Suf|W, { Imm, Acc, 0} },
192 {"sbb", 2, 0x80, 3, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
193
194 {"cmp", 2, 0x38, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
195 {"cmp", 2, 0x83, 7, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
196 {"cmp", 2, 0x3c, X, bwl_Suf|W, { Imm, Acc, 0} },
197 {"cmp", 2, 0x80, 7, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
198
199 {"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
200 {"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
201 {"test", 2, 0xa8, X, bwl_Suf|W, { Imm, Acc, 0} },
202 {"test", 2, 0xf6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
203
204 {"and", 2, 0x20, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
205 {"and", 2, 0x83, 4, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
206 {"and", 2, 0x24, X, bwl_Suf|W, { Imm, Acc, 0} },
207 {"and", 2, 0x80, 4, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
208
209 {"or", 2, 0x08, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
210 {"or", 2, 0x83, 1, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
211 {"or", 2, 0x0c, X, bwl_Suf|W, { Imm, Acc, 0} },
212 {"or", 2, 0x80, 1, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
213
214 {"xor", 2, 0x30, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
215 {"xor", 2, 0x83, 6, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
216 {"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} },
217 {"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
218
219 /* iclr with 1 operand is really xor with 2 operands. */
220 {"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
221
222 {"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
223 {"adc", 2, 0x83, 2, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
224 {"adc", 2, 0x14, X, bwl_Suf|W, { Imm, Acc, 0} },
225 {"adc", 2, 0x80, 2, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
226
227 {"neg", 1, 0xf6, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
228 {"not", 1, 0xf6, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
229
230 {"aaa", 0, 0x37, X, NoSuf, { 0, 0, 0} },
231 {"aas", 0, 0x3f, X, NoSuf, { 0, 0, 0} },
232 {"daa", 0, 0x27, X, NoSuf, { 0, 0, 0} },
233 {"das", 0, 0x2f, X, NoSuf, { 0, 0, 0} },
234 {"aad", 0, 0xd50a, X, NoSuf, { 0, 0, 0} },
235 {"aad", 1, 0xd5, X, NoSuf, { Imm8S, 0, 0} },
236 {"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} },
237 {"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} },
238
239 /* conversion insns */
240 /* conversion: intel naming */
241 {"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
242 {"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
243 {"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
244 {"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
245 /* att naming */
246 {"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
247 {"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
248 {"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
249 {"cltd", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
250
251 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
252 expanding 64-bit multiplies, and *cannot* be selected to accomplish
253 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
254 These multiplies can only be selected with single operand forms. */
255 {"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
256 {"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
257 {"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
258 {"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
259 {"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} },
260 /* imul with 2 operands mimics imul with 3 by putting the register in
261 both i.rm.reg & i.rm.regmem fields. regKludge enables this
262 transformation. */
263 {"imul", 2, 0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
264 {"imul", 2, 0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
265
266 {"div", 1, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
267 {"div", 2, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
268 {"idiv", 1, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
269 {"idiv", 2, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
270
271 {"rol", 2, 0xd0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
272 {"rol", 2, 0xc0, 0, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
273 {"rol", 2, 0xd2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
274 {"rol", 1, 0xd0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
275
276 {"ror", 2, 0xd0, 1, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
277 {"ror", 2, 0xc0, 1, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
278 {"ror", 2, 0xd2, 1, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
279 {"ror", 1, 0xd0, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
280
281 {"rcl", 2, 0xd0, 2, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
282 {"rcl", 2, 0xc0, 2, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
283 {"rcl", 2, 0xd2, 2, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
284 {"rcl", 1, 0xd0, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
285
286 {"rcr", 2, 0xd0, 3, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
287 {"rcr", 2, 0xc0, 3, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
288 {"rcr", 2, 0xd2, 3, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
289 {"rcr", 1, 0xd0, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
290
291 {"sal", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
292 {"sal", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
293 {"sal", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
294 {"sal", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
295 {"shl", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
296 {"shl", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
297 {"shl", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
298 {"shl", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
299
300 {"shld", 3, 0x0fa4, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
301 {"shld", 3, 0x0fa5, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
302 {"shld", 2, 0x0fa5, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
303
304 {"shr", 2, 0xd0, 5, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
305 {"shr", 2, 0xc0, 5, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
306 {"shr", 2, 0xd2, 5, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
307 {"shr", 1, 0xd0, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
308
309 {"shrd", 3, 0x0fac, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
310 {"shrd", 3, 0x0fad, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
311 {"shrd", 2, 0x0fad, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
312
313 {"sar", 2, 0xd0, 7, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
314 {"sar", 2, 0xc0, 7, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
315 {"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
316 {"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
317
318 /* control transfer instructions */
319 {"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
320 {"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
321 /* Intel Syntax */
322 {"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
323 /* Intel Syntax */
324 {"call", 1, 0xff, 3, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
325 {"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
326 {"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} },
327
328 #define JUMP_PC_RELATIVE 0xeb
329 {"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} },
330 {"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
331 /* Intel Syntax */
332 {"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
333 /* Intel Syntax */
334 {"jmp", 1, 0xff, 5, x_Suf|Modrm, { WordMem, 0, 0} },
335 {"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
336 {"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
337
338 {"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} },
339 {"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} },
340 {"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} },
341 {"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} },
342 {"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} },
343 {"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} },
344
345 /* conditional jumps */
346 {"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} },
347 {"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} },
348 {"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
349 {"jc", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
350 {"jnae", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
351 {"jnb", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
352 {"jnc", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
353 {"jae", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
354 {"je", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
355 {"jz", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
356 {"jne", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
357 {"jnz", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
358 {"jbe", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
359 {"jna", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
360 {"jnbe", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
361 {"ja", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
362 {"js", 1, 0x78, X, NoSuf|Jump, { Disp, 0, 0} },
363 {"jns", 1, 0x79, X, NoSuf|Jump, { Disp, 0, 0} },
364 {"jp", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
365 {"jpe", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
366 {"jnp", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
367 {"jpo", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
368 {"jl", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
369 {"jnge", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
370 {"jnl", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
371 {"jge", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
372 {"jle", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
373 {"jng", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
374 {"jnle", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
375 {"jg", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
376
377 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
378 {"jcxz", 1, 0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
379 {"jecxz", 1, 0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
380
381 /* The loop instructions also use the address size prefix to select
382 %cx rather than %ecx for the loop count, so the `w' form of these
383 instructions emit an address size prefix rather than a data size
384 prefix. */
385 {"loop", 1, 0xe2, X, wl_Suf|JumpByte, { Disp, 0, 0} },
386 {"loopz", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
387 {"loope", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
388 {"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
389 {"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
390
391 /* set byte on flag instructions */
392 {"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
393 {"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
394 {"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
395 {"setc", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
396 {"setnae", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
397 {"setnb", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
398 {"setnc", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
399 {"setae", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
400 {"sete", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
401 {"setz", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
402 {"setne", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
403 {"setnz", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
404 {"setbe", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
405 {"setna", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
406 {"setnbe", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
407 {"seta", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
408 {"sets", 1, 0x0f98, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
409 {"setns", 1, 0x0f99, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
410 {"setp", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
411 {"setpe", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
412 {"setnp", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
413 {"setpo", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
414 {"setl", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
415 {"setnge", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
416 {"setnl", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
417 {"setge", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
418 {"setle", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
419 {"setng", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
420 {"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
421 {"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
422
423 /* string manipulation */
424 {"cmps", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} },
425 {"cmps", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
426 {"scmp", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} },
427 {"scmp", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
428 {"ins", 0, 0x6c, X, bwld_Suf|W|IsString, { 0, 0, 0} },
429 {"ins", 2, 0x6c, X, bwld_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
430 {"outs", 0, 0x6e, X, bwld_Suf|W|IsString, { 0, 0, 0} },
431 {"outs", 2, 0x6e, X, bwld_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
432 {"lods", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} },
433 {"lods", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} },
434 {"lods", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} },
435 {"slod", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} },
436 {"slod", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} },
437 {"slod", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} },
438 {"movs", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} },
439 {"movs", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
440 {"smov", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} },
441 {"smov", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
442 {"scas", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} },
443 {"scas", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
444 {"scas", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
445 {"ssca", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} },
446 {"ssca", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
447 {"ssca", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
448 {"stos", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} },
449 {"stos", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
450 {"stos", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
451 {"ssto", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} },
452 {"ssto", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
453 {"ssto", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
454 {"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} },
455 {"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} },
456
457 /* bit manipulation */
458 {"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
459 {"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
460 {"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
461 {"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
462 {"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
463 {"btc", 2, 0x0fba, 7, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
464 {"btr", 2, 0x0fb3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
465 {"btr", 2, 0x0fba, 6, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
466 {"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
467 {"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
468
469 /* interrupts & op. sys insns */
470 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
471 int 3 insn. */
472 #define INT_OPCODE 0xcd
473 #define INT3_OPCODE 0xcc
474 {"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} },
475 {"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} },
476 {"into", 0, 0xce, X, NoSuf, { 0, 0, 0} },
477 {"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} },
478 /* i386sl, i486sl, later 486, and Pentium */
479 {"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} },
480
481 {"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} },
482
483 {"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} },
484 /* nop is actually 'xchgl %eax, %eax' */
485 {"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} },
486
487 /* protection control */
488 {"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
489 {"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
490 {"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} },
491 {"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
492 {"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
493 {"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
494 {"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
495 {"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
496
497 {"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} },
498 {"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} },
499 {"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
500 {"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
501 {"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
502
503 {"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
504 {"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
505
506 /* floating point instructions */
507
508 /* load */
509 {"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
510 {"fld", 1, 0xd9, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 <-- mem float/double */
511 {"fld", 1, 0xd9c0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
512 /* Intel Syntax */
513 {"fld", 1, 0xdb, 5, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
514 {"fild", 1, 0xdf, 0, sl_Suf|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */
515 /* Intel Syntax */
516 {"fildd", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
517 {"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
518 {"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
519 {"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
520 {"fbld", 1, 0xdf, 4, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem bcd */
521
522 /* store (no pop) */
523 {"fst", 1, 0xddd0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
524 {"fst", 1, 0xd9, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
525 {"fst", 1, 0xddd0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
526 {"fist", 1, 0xdf, 2, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
527
528 /* store (with pop) */
529 {"fstp", 1, 0xddd8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
530 {"fstp", 1, 0xd9, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
531 {"fstp", 1, 0xddd8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
532 /* Intel Syntax */
533 {"fstp", 1, 0xdb, 7, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */
534 {"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
535 /* Intel Syntax */
536 {"fistpd", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
537 {"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
538 {"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
539 {"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */
540 {"fbstp", 1, 0xdf, 6, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem bcd */
541
542 /* exchange %st<n> with %st0 */
543 {"fxch", 1, 0xd9c8, X, FP|ShortForm, { FloatReg, 0, 0} },
544 {"fxch", 0, 0xd9c9, X, FP, { 0, 0, 0} }, /* alias for fxch %st(1) */
545
546 /* comparison (without pop) */
547 {"fcom", 1, 0xd8d0, X, FP|ShortForm, { FloatReg, 0, 0} },
548 {"fcom", 0, 0xd8d1, X, FP, { 0, 0, 0} }, /* alias for fcom %st(1) */
549 {"fcom", 1, 0xd8, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
550 {"fcom", 1, 0xd8d0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
551 {"ficom", 1, 0xde, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
552
553 /* comparison (with pop) */
554 {"fcomp", 1, 0xd8d8, X, FP|ShortForm, { FloatReg, 0, 0} },
555 {"fcomp", 0, 0xd8d9, X, FP, { 0, 0, 0} }, /* alias for fcomp %st(1) */
556 {"fcomp", 1, 0xd8, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
557 {"fcomp", 1, 0xd8d8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
558 {"ficomp", 1, 0xde, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
559 {"fcompp", 0, 0xded9, X, FP, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
560
561 /* unordered comparison (with pop) */
562 {"fucom", 1, 0xdde0, X, FP|ShortForm, { FloatReg, 0, 0} },
563 {"fucom", 0, 0xdde1, X, FP, { 0, 0, 0} }, /* alias for fucom %st(1) */
564 {"fucomp", 1, 0xdde8, X, FP|ShortForm, { FloatReg, 0, 0} },
565 {"fucomp", 0, 0xdde9, X, FP, { 0, 0, 0} }, /* alias for fucomp %st(1) */
566 {"fucompp",0, 0xdae9, X, FP, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
567
568 {"ftst", 0, 0xd9e4, X, FP, { 0, 0, 0} }, /* test %st0 */
569 {"fxam", 0, 0xd9e5, X, FP, { 0, 0, 0} }, /* examine %st0 */
570
571 /* load constants into %st0 */
572 {"fld1", 0, 0xd9e8, X, FP, { 0, 0, 0} }, /* %st0 <-- 1.0 */
573 {"fldl2t", 0, 0xd9e9, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(10) */
574 {"fldl2e", 0, 0xd9ea, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(e) */
575 {"fldpi", 0, 0xd9eb, X, FP, { 0, 0, 0} }, /* %st0 <-- pi */
576 {"fldlg2", 0, 0xd9ec, X, FP, { 0, 0, 0} }, /* %st0 <-- log10(2) */
577 {"fldln2", 0, 0xd9ed, X, FP, { 0, 0, 0} }, /* %st0 <-- ln(2) */
578 {"fldz", 0, 0xd9ee, X, FP, { 0, 0, 0} }, /* %st0 <-- 0.0 */
579
580 /* arithmetic */
581
582 /* add */
583 {"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
584 {"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */
585 #if UNIXWARE_COMPAT
586 {"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, /* alias for faddp */
587 #endif
588 {"fadd", 1, 0xd8, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
589 {"fiadd", 1, 0xde, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
590
591 {"faddp", 2, 0xdec0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
592 {"faddp", 1, 0xdec0, X, FP|ShortForm, { FloatReg, 0, 0} },
593 {"faddp", 0, 0xdec1, X, FP, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
594 {"faddp", 2, 0xdec0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
595
596 /* subtract */
597 {"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
598 {"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} },
599 #if UNIXWARE_COMPAT
600 {"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubp */
601 #endif
602 {"fsub", 1, 0xd8, 4, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
603 {"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
604
605 #if UNIXWARE_COMPAT
606 {"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
607 {"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
608 {"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} },
609 {"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
610 #else
611 {"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
612 {"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
613 {"fsubp", 0, 0xdee9, X, FP, { 0, 0, 0} },
614 #endif
615
616 /* subtract reverse */
617 {"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
618 {"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} },
619 #if UNIXWARE_COMPAT
620 {"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubrp */
621 #endif
622 {"fsubr", 1, 0xd8, 5, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
623 {"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
624
625 #if UNIXWARE_COMPAT
626 {"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
627 {"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
628 {"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} },
629 {"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
630 #else
631 {"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
632 {"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
633 {"fsubrp", 0, 0xdee1, X, FP, { 0, 0, 0} },
634 #endif
635
636 /* multiply */
637 {"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
638 {"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} },
639 #if UNIXWARE_COMPAT
640 {"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fmulp */
641 #endif
642 {"fmul", 1, 0xd8, 1, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
643 {"fimul", 1, 0xde, 1, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
644
645 {"fmulp", 2, 0xdec8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
646 {"fmulp", 1, 0xdec8, X, FP|ShortForm, { FloatReg, 0, 0} },
647 {"fmulp", 0, 0xdec9, X, FP, { 0, 0, 0} },
648 {"fmulp", 2, 0xdec8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
649
650 /* divide */
651 {"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
652 {"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} },
653 #if UNIXWARE_COMPAT
654 {"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivp */
655 #endif
656 {"fdiv", 1, 0xd8, 6, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
657 {"fidiv", 1, 0xde, 6, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
658
659 #if UNIXWARE_COMPAT
660 {"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
661 {"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
662 {"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} },
663 {"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
664 #else
665 {"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
666 {"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
667 {"fdivp", 0, 0xdef9, X, FP, { 0, 0, 0} },
668 #endif
669
670 /* divide reverse */
671 {"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
672 {"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} },
673 #if UNIXWARE_COMPAT
674 {"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivrp */
675 #endif
676 {"fdivr", 1, 0xd8, 7, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
677 {"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
678
679 #if UNIXWARE_COMPAT
680 {"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
681 {"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
682 {"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} },
683 {"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
684 #else
685 {"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
686 {"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
687 {"fdivrp", 0, 0xdef1, X, FP, { 0, 0, 0} },
688 #endif
689
690 {"f2xm1", 0, 0xd9f0, X, FP, { 0, 0, 0} },
691 {"fyl2x", 0, 0xd9f1, X, FP, { 0, 0, 0} },
692 {"fptan", 0, 0xd9f2, X, FP, { 0, 0, 0} },
693 {"fpatan", 0, 0xd9f3, X, FP, { 0, 0, 0} },
694 {"fxtract",0, 0xd9f4, X, FP, { 0, 0, 0} },
695 {"fprem1", 0, 0xd9f5, X, FP, { 0, 0, 0} },
696 {"fdecstp",0, 0xd9f6, X, FP, { 0, 0, 0} },
697 {"fincstp",0, 0xd9f7, X, FP, { 0, 0, 0} },
698 {"fprem", 0, 0xd9f8, X, FP, { 0, 0, 0} },
699 {"fyl2xp1",0, 0xd9f9, X, FP, { 0, 0, 0} },
700 {"fsqrt", 0, 0xd9fa, X, FP, { 0, 0, 0} },
701 {"fsincos",0, 0xd9fb, X, FP, { 0, 0, 0} },
702 {"frndint",0, 0xd9fc, X, FP, { 0, 0, 0} },
703 {"fscale", 0, 0xd9fd, X, FP, { 0, 0, 0} },
704 {"fsin", 0, 0xd9fe, X, FP, { 0, 0, 0} },
705 {"fcos", 0, 0xd9ff, X, FP, { 0, 0, 0} },
706 {"fchs", 0, 0xd9e0, X, FP, { 0, 0, 0} },
707 {"fabs", 0, 0xd9e1, X, FP, { 0, 0, 0} },
708
709 /* processor control */
710 {"fninit", 0, 0xdbe3, X, FP, { 0, 0, 0} },
711 {"finit", 0, 0xdbe3, X, FP|FWait, { 0, 0, 0} },
712 {"fldcw", 1, 0xd9, 5, FP|Modrm, { ShortMem, 0, 0} },
713 {"fnstcw", 1, 0xd9, 7, FP|Modrm, { ShortMem, 0, 0} },
714 {"fstcw", 1, 0xd9, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
715 {"fnstsw", 1, 0xdfe0, X, FP, { Acc, 0, 0} },
716 {"fnstsw", 1, 0xdd, 7, FP|Modrm, { ShortMem, 0, 0} },
717 {"fnstsw", 0, 0xdfe0, X, FP, { 0, 0, 0} },
718 {"fstsw", 1, 0xdfe0, X, FP|FWait, { Acc, 0, 0} },
719 {"fstsw", 1, 0xdd, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
720 {"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} },
721 {"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} },
722 {"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} },
723 /* Short forms of fldenv, fstenv use data size prefix.
724 FIXME: Are these the right suffixes? */
725 {"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
726 {"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
727 {"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
728 {"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
729 {"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
730 {"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
731
732 {"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} },
733 /* P6:free st(i), pop st */
734 {"ffreep", 1, 0xdfc0, X, FP|ShortForm, { FloatReg, 0, 0} },
735 {"fnop", 0, 0xd9d0, X, FP, { 0, 0, 0} },
736 #define FWAIT_OPCODE 0x9b
737 {"fwait", 0, 0x9b, X, FP, { 0, 0, 0} },
738
739 /*
740 opcode prefixes; we allow them as seperate insns too
741 */
742 #define ADDR_PREFIX_OPCODE 0x67
743 {"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
744 {"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
745 {"aword", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
746 {"adword", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
747 #define DATA_PREFIX_OPCODE 0x66
748 {"data16", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
749 {"data32", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
750 {"word", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
751 {"dword", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
752 #define LOCK_PREFIX_OPCODE 0xf0
753 {"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} },
754 {"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} },
755 #define CS_PREFIX_OPCODE 0x2e
756 {"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} },
757 #define DS_PREFIX_OPCODE 0x3e
758 {"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} },
759 #define ES_PREFIX_OPCODE 0x26
760 {"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} },
761 #define FS_PREFIX_OPCODE 0x64
762 {"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} },
763 #define GS_PREFIX_OPCODE 0x65
764 {"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} },
765 #define SS_PREFIX_OPCODE 0x36
766 {"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} },
767 #define REPNE_PREFIX_OPCODE 0xf2
768 #define REPE_PREFIX_OPCODE 0xf3
769 {"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
770 {"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
771 {"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
772 {"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
773 {"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
774
775 /* 486 extensions */
776
777 {"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } },
778 {"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
779 {"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
780 {"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} },
781 {"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} },
782 {"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} },
783
784 /* 586 and late 486 extensions */
785 {"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} },
786
787 /* Pentium extensions */
788 {"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} },
789 {"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} },
790 {"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} },
791 {"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} },
792 {"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} },
793 {"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} },
794 {"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} },
795 {"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} },
796
797 /* Pentium Pro extensions */
798 {"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} },
799
800 {"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* official undefined instr. */
801 {"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* alias for ud2 */
802 {"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */
803
804 {"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
805 {"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
806 {"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
807 {"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
808 {"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
809 {"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
810 {"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
811 {"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
812 {"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
813 {"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
814 {"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
815 {"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
816 {"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
817 {"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
818 {"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
819 {"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
820 {"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
821 {"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
822 {"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
823 {"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
824 {"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
825 {"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
826 {"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
827 {"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
828 {"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
829 {"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
830 {"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
831 {"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
832
833 {"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
834 {"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
835 {"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
836 {"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
837 {"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
838 {"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
839 {"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
840 {"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
841 {"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
842 {"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
843 {"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
844 {"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
845
846 {"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
847 {"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} },
848 {"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} },
849 {"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
850 {"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} },
851 {"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} },
852 {"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
853 {"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
854 {"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} },
855 {"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} },
856 {"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
857 {"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
858 {"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} },
859 {"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} },
860
861 /* MMX instructions. */
862
863 {"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } },
864 {"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } },
865 {"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } },
866 {"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
867 {"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
868 {"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
869 {"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
870 {"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
871 {"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
872 {"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
873 {"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
874 {"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
875 {"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
876 {"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
877 {"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
878 {"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
879 {"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
880 {"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
881 {"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
882 {"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
883 {"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
884 {"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
885 {"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
886 {"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
887 {"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
888 {"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
889 {"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
890 {"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
891 {"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } },
892 {"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
893 {"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } },
894 {"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
895 {"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } },
896 {"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
897 {"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } },
898 {"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
899 {"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } },
900 {"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
901 {"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } },
902 {"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
903 {"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } },
904 {"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
905 {"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } },
906 {"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
907 {"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
908 {"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
909 {"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
910 {"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
911 {"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
912 {"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
913 {"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
914 {"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
915 {"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
916 {"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
917 {"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
918 {"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
919 {"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
920
921
922 /* PIII Katmai New Instructions / SIMD instructions */
923
924 {"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
925 {"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
926 {"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
927 {"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
928 {"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
929 {"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
930 {"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
931 {"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
932 {"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
933 {"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
934 {"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
935 {"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
936 {"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
937 {"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
938 {"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
939 {"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
940 {"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
941 {"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
942 {"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
943 {"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
944 {"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
945 {"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
946 {"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
947 {"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
948 {"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
949 {"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } },
950 {"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
951 {"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
952 {"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
953 {"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
954 {"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
955 {"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } },
956 {"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
957 {"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
958 {"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
959 {"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
960 {"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
961 {"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
962 {"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
963 {"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
964 {"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } },
965 {"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } },
966 {"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
967 {"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } },
968 {"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } },
969 {"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } },
970 {"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } },
971 {"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } },
972 {"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
973 {"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
974 {"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
975 {"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
976 {"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
977 {"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
978 {"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
979 {"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
980 {"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
981 {"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } },
982 {"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } },
983 {"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
984 {"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
985 {"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
986 {"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
987 {"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } },
988 {"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
989 {"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } },
990 {"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } },
991 {"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } },
992 {"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } },
993 {"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
994 {"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
995 {"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
996 {"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
997 {"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
998 {"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
999 {"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } },
1000 {"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1001 {"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1002 {"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1003 {"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } },
1004 {"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1005 {"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1006 {"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1007 {"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1008 {"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1009 {"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1010
1011 /* AMD 3DNow! instructions */
1012
1013 {"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } },
1014 {"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } },
1015 {"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } },
1016 {"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1017 {"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1018 {"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1019 {"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1020 {"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1021 {"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1022 {"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1023 {"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1024 {"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1025 {"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1026 {"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1027 {"pfnacc", 2, 0x0f0f, 0x8a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1028 {"pfpnacc", 2, 0x0f0f, 0x8e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1029 {"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1030 {"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1031 {"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1032 {"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1033 {"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1034 {"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1035 {"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1036 {"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1037 {"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1038 {"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1039 {"pswapd", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1040
1041 {NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
1042 };
1043 #undef X
1044 #undef NoSuf
1045 #undef b_Suf
1046 #undef w_Suf
1047 #undef l_Suf
1048 #undef d_Suf
1049 #undef x_Suf
1050 #undef bw_Suf
1051 #undef bl_Suf
1052 #undef wl_Suf
1053 #undef sl_Suf
1054 #undef sld_Suf
1055 #undef sldx_Suf
1056 #undef bwl_Suf
1057 #undef bwld_Suf
1058 #undef FP
1059 #undef l_FP
1060 #undef d_FP
1061 #undef x_FP
1062 #undef sl_FP
1063 #undef sld_FP
1064 #undef sldx_FP
1065
1066 #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
1067
1068
1069 /* 386 register table */
1070
1071 static const reg_entry i386_regtab[] = {
1072 /* make %st first as we test for it */
1073 {"st", FloatReg|FloatAcc, 0},
1074 /* 8 bit regs */
1075 {"al", Reg8|Acc, 0},
1076 {"cl", Reg8|ShiftCount, 1},
1077 {"dl", Reg8, 2},
1078 {"bl", Reg8, 3},
1079 {"ah", Reg8, 4},
1080 {"ch", Reg8, 5},
1081 {"dh", Reg8, 6},
1082 {"bh", Reg8, 7},
1083 /* 16 bit regs */
1084 {"ax", Reg16|Acc, 0},
1085 {"cx", Reg16, 1},
1086 {"dx", Reg16|InOutPortReg, 2},
1087 {"bx", Reg16|BaseIndex, 3},
1088 {"sp", Reg16, 4},
1089 {"bp", Reg16|BaseIndex, 5},
1090 {"si", Reg16|BaseIndex, 6},
1091 {"di", Reg16|BaseIndex, 7},
1092 /* 32 bit regs */
1093 {"eax", Reg32|BaseIndex|Acc, 0},
1094 {"ecx", Reg32|BaseIndex, 1},
1095 {"edx", Reg32|BaseIndex, 2},
1096 {"ebx", Reg32|BaseIndex, 3},
1097 {"esp", Reg32, 4},
1098 {"ebp", Reg32|BaseIndex, 5},
1099 {"esi", Reg32|BaseIndex, 6},
1100 {"edi", Reg32|BaseIndex, 7},
1101 /* segment registers */
1102 {"es", SReg2, 0},
1103 {"cs", SReg2, 1},
1104 {"ss", SReg2, 2},
1105 {"ds", SReg2, 3},
1106 {"fs", SReg3, 4},
1107 {"gs", SReg3, 5},
1108 /* control registers */
1109 {"cr0", Control, 0},
1110 {"cr1", Control, 1},
1111 {"cr2", Control, 2},
1112 {"cr3", Control, 3},
1113 {"cr4", Control, 4},
1114 {"cr5", Control, 5},
1115 {"cr6", Control, 6},
1116 {"cr7", Control, 7},
1117 /* debug registers */
1118 {"db0", Debug, 0},
1119 {"db1", Debug, 1},
1120 {"db2", Debug, 2},
1121 {"db3", Debug, 3},
1122 {"db4", Debug, 4},
1123 {"db5", Debug, 5},
1124 {"db6", Debug, 6},
1125 {"db7", Debug, 7},
1126 {"dr0", Debug, 0},
1127 {"dr1", Debug, 1},
1128 {"dr2", Debug, 2},
1129 {"dr3", Debug, 3},
1130 {"dr4", Debug, 4},
1131 {"dr5", Debug, 5},
1132 {"dr6", Debug, 6},
1133 {"dr7", Debug, 7},
1134 /* test registers */
1135 {"tr0", Test, 0},
1136 {"tr1", Test, 1},
1137 {"tr2", Test, 2},
1138 {"tr3", Test, 3},
1139 {"tr4", Test, 4},
1140 {"tr5", Test, 5},
1141 {"tr6", Test, 6},
1142 {"tr7", Test, 7},
1143 /* mmx and simd registers */
1144 {"mm0", RegMMX, 0},
1145 {"mm1", RegMMX, 1},
1146 {"mm2", RegMMX, 2},
1147 {"mm3", RegMMX, 3},
1148 {"mm4", RegMMX, 4},
1149 {"mm5", RegMMX, 5},
1150 {"mm6", RegMMX, 6},
1151 {"mm7", RegMMX, 7},
1152 {"xmm0", RegXMM, 0},
1153 {"xmm1", RegXMM, 1},
1154 {"xmm2", RegXMM, 2},
1155 {"xmm3", RegXMM, 3},
1156 {"xmm4", RegXMM, 4},
1157 {"xmm5", RegXMM, 5},
1158 {"xmm6", RegXMM, 6},
1159 {"xmm7", RegXMM, 7}
1160 };
1161
1162 static const reg_entry i386_float_regtab[] = {
1163 {"st(0)", FloatReg|FloatAcc, 0},
1164 {"st(1)", FloatReg, 1},
1165 {"st(2)", FloatReg, 2},
1166 {"st(3)", FloatReg, 3},
1167 {"st(4)", FloatReg, 4},
1168 {"st(5)", FloatReg, 5},
1169 {"st(6)", FloatReg, 6},
1170 {"st(7)", FloatReg, 7}
1171 };
1172
1173 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
1174
1175 /* segment stuff */
1176 static const seg_entry cs = { "cs", 0x2e };
1177 static const seg_entry ds = { "ds", 0x3e };
1178 static const seg_entry ss = { "ss", 0x36 };
1179 static const seg_entry es = { "es", 0x26 };
1180 static const seg_entry fs = { "fs", 0x64 };
1181 static const seg_entry gs = { "gs", 0x65 };
1182
1183 /* end of opcode/i386.h */
GDB Binutils - Deliverables
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