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* configure.in: Add support for x86_64 and x86_64-*-linux-gnu*
[deliverable/binutils-gdb.git] / include / opcode / i386.h
1 /* opcode/i386.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation.
4
5 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
22 ix86 Unix assemblers, generate floating point instructions with
23 reversed source and destination registers in certain cases.
24 Unfortunately, gcc and possibly many other programs use this
25 reversed syntax, so we're stuck with it.
26
27 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
28 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
29 the expected st(3) = st(3) - st
30
31 This happens with all the non-commutative arithmetic floating point
32 operations with two register operands, where the source register is
33 %st, and destination register is %st(i). See FloatDR below.
34
35 The affected opcode map is dceX, dcfX, deeX, defX. */
36
37 #ifndef SYSV386_COMPAT
38 /* Set non-zero for broken, compatible instructions. Set to zero for
39 non-broken opcodes at your peril. gcc generates SystemV/386
40 compatible instructions. */
41 #define SYSV386_COMPAT 1
42 #endif
43 #ifndef OLDGCC_COMPAT
44 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
45 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
46 reversed. */
47 #define OLDGCC_COMPAT SYSV386_COMPAT
48 #endif
49
50 static const template i386_optab[] = {
51
52 #define X None
53 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
54 #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
55 #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
56 #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf)
57 #define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
58 #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf)
59 #define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf)
60 #define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf)
61 #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf)
62 #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
63 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
64 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
65 #define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)
66 #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
67 #define bwlq_Suf (No_sSuf|No_xSuf)
68 #define FP (NoSuf|IgnoreSize)
69 #define l_FP (l_Suf|IgnoreSize)
70 #define x_FP (x_Suf|IgnoreSize)
71 #define sl_FP (sl_Suf|IgnoreSize)
72 #if SYSV386_COMPAT
73 /* Someone forgot that the FloatR bit reverses the operation when not
74 equal to the FloatD bit. ie. Changing only FloatD results in the
75 destination being swapped *and* the direction being reversed. */
76 #define FloatDR FloatD
77 #else
78 #define FloatDR (FloatD|FloatR)
79 #endif
80
81 /* Move instructions. */
82 #define MOV_AX_DISP32 0xa0
83 /* In the 64bit mode the short form mov immediate is redefined to have
84 64bit displacement value. */
85 { "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
86 { "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
87 /* In the 64bit mode the short form mov immediate is redefined to have
88 64bit displacement value. */
89 { "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } },
90 { "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } },
91 { "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
92 /* The segment register moves accept WordReg so that a segment register
93 can be copied to a 32 bit register, and vice versa, without using a
94 size prefix. When moving to a 32 bit register, the upper 16 bits
95 are set to an implementation defined value (on the Pentium Pro,
96 the implementation defined value is zero). */
97 { "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } },
98 { "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } },
99 { "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } },
100 { "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } },
101 /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit
102 mode they are 64bit.*/
103 { "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} },
104 { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
105 { "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },
106 { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
107 { "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
108 { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } },
109 { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
110
111 /* Move with sign extend. */
112 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
113 conflict with the "movs" string move instruction. */
114 {"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
115 {"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
116 {"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} },
117 {"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
118 {"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} },
119 {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
120 /* Intel Syntax next 5 insns */
121 {"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
122 {"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
123 {"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
124 {"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} },
125 {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
126
127 /* Move with zero extend. */
128 {"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
129 {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
130 /* These instructions are not particulary usefull, since the zero extend
131 32->64 is implicit, but we can encode them. */
132 {"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
133 {"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
134 /* Intel Syntax next 4 insns */
135 {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
136 {"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
137 /* These instructions are not particulary usefull, since the zero extend
138 32->64 is implicit, but we can encode them. */
139 {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
140 {"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} },
141
142 /* Push instructions. */
143 {"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
144 {"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
145 {"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
146 {"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
147 {"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
148 {"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
149 /* In 64bit mode, the operand size is implicitly 64bit. */
150 {"push", 1, 0x50, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } },
151 {"push", 1, 0xff, 6, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } },
152 {"push", 1, 0x6a, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
153 {"push", 1, 0x68, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm32S, 0, 0} },
154 {"push", 1, 0x06, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
155 {"push", 1, 0x0fa0, X, Cpu386|Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
156
157 {"pusha", 0, 0x60, X, Cpu186|Cpu64, wl_Suf|DefaultSize, { 0, 0, 0 } },
158
159 /* Pop instructions. */
160 {"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
161 {"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
162 #define POP_SEG_SHORT 0x07
163 {"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
164 {"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
165 /* In 64bit mode, the operand size is implicitly 64bit. */
166 {"pop", 1, 0x58, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } },
167 {"pop", 1, 0x8f, 0, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } },
168 {"pop", 1, 0x07, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
169 {"pop", 1, 0x0fa1, X, Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
170
171 {"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
172
173 /* Exchange instructions.
174 xchg commutes: we allow both operand orders.
175
176 In the 64bit code, xchg eax, eax is reused for new nop instruction.
177 */
178 {"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
179 {"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
180 {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
181 {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
182
183 /* In/out from ports. */
184 {"in", 2, 0xe4, X, 0, bwlq_Suf|W, { Imm8, Acc, 0 } },
185 {"in", 2, 0xec, X, 0, bwlq_Suf|W, { InOutPortReg, Acc, 0 } },
186 {"in", 1, 0xe4, X, 0, bwlq_Suf|W, { Imm8, 0, 0 } },
187 {"in", 1, 0xec, X, 0, bwlq_Suf|W, { InOutPortReg, 0, 0 } },
188 {"out", 2, 0xe6, X, 0, bwlq_Suf|W, { Acc, Imm8, 0 } },
189 {"out", 2, 0xee, X, 0, bwlq_Suf|W, { Acc, InOutPortReg, 0 } },
190 {"out", 1, 0xe6, X, 0, bwlq_Suf|W, { Imm8, 0, 0 } },
191 {"out", 1, 0xee, X, 0, bwlq_Suf|W, { InOutPortReg, 0, 0 } },
192
193 /* Load effective address. */
194 {"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } },
195
196 /* Load segment registers from memory. */
197 {"lds", 2, 0xc5, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
198 {"les", 2, 0xc4, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
199 {"lfs", 2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
200 {"lgs", 2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
201 {"lss", 2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
202
203 /* Flags register instructions. */
204 {"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} },
205 {"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} },
206 {"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} },
207 {"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} },
208 {"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} },
209 {"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} },
210 {"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} },
211 {"pushf", 0, 0x9c, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
212 {"popf", 0, 0x9d, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
213 {"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} },
214 {"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} },
215 {"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} },
216
217 /* Arithmetic. */
218 {"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
219 {"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
220 {"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
221 {"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
222
223 {"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} },
224 {"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
225
226 {"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
227 {"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
228 {"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
229 {"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
230
231 {"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} },
232 {"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
233
234 {"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
235 {"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
236 {"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
237 {"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
238
239 {"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
240 {"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
241 {"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
242 {"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
243
244 {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
245 {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
246 {"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
247 {"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
248
249 {"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
250 {"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
251 {"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
252 {"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
253
254 {"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
255 {"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
256 {"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
257 {"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
258
259 {"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
260 {"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
261 {"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
262 {"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
263
264 /* clr with 1 operand is really xor with 2 operands. */
265 {"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
266
267 {"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
268 {"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
269 {"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
270 {"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
271
272 {"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
273 {"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
274
275 {"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} },
276 {"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} },
277 {"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} },
278 {"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} },
279 {"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} },
280 {"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} },
281 {"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} },
282 {"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} },
283
284 /* Conversion insns. */
285 /* Intel naming */
286 {"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
287 {"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
288 {"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
289 {"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
290 {"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
291 {"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
292 /* AT&T naming */
293 {"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
294 {"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
295 {"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
296 {"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
297 {"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
298 {"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
299
300 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
301 expanding 64-bit multiplies, and *cannot* be selected to accomplish
302 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
303 These multiplies can only be selected with single operand forms. */
304 {"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
305 {"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
306 {"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
307 {"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
308 {"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} },
309 /* imul with 2 operands mimics imul with 3 by putting the register in
310 both i.rm.reg & i.rm.regmem fields. regKludge enables this
311 transformation. */
312 {"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
313 {"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
314
315 {"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
316 {"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
317 {"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
318 {"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
319
320 {"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
321 {"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
322 {"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
323 {"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
324
325 {"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
326 {"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
327 {"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
328 {"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
329
330 {"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
331 {"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
332 {"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
333 {"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
334
335 {"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
336 {"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
337 {"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
338 {"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
339
340 {"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
341 {"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
342 {"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
343 {"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
344
345 {"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
346 {"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
347 {"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
348 {"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
349
350 {"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
351 {"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
352 {"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
353 {"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
354
355 {"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
356 {"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
357 {"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
358 {"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
359
360 {"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
361 {"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
362 {"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
363
364 {"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
365 {"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
366 {"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
367
368 /* Control transfer instructions. */
369 {"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
370 {"call", 1, 0xff, 2, 0, wlq_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
371 /* Intel Syntax */
372 {"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
373 /* Intel Syntax */
374 {"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
375 {"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
376 {"lcall", 1, 0xff, 3, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} },
377 {"lcall", 1, 0xff, 3, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} },
378
379 #define JUMP_PC_RELATIVE 0xeb
380 {"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} },
381 {"jmp", 1, 0xff, 4, 0, wlq_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
382 /* Intel Syntax */
383 {"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
384 /* Intel Syntax */
385 {"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} },
386 {"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
387 {"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
388 {"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} },
389
390 {"ret", 0, 0xc3, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
391 {"ret", 1, 0xc2, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} },
392 {"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
393 {"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} },
394 {"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} },
395 {"leave", 0, 0xc9, X, Cpu186, wlq_Suf|DefaultSize, { 0, 0, 0} },
396
397 /* Conditional jumps. */
398 {"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} },
399 {"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} },
400 {"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
401 {"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
402 {"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
403 {"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
404 {"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
405 {"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
406 {"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
407 {"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
408 {"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
409 {"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
410 {"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
411 {"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
412 {"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
413 {"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
414 {"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} },
415 {"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} },
416 {"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
417 {"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
418 {"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
419 {"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
420 {"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
421 {"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
422 {"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
423 {"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
424 {"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
425 {"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
426 {"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
427 {"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
428
429 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
430 {"jcxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
431 {"jecxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
432
433 /* The loop instructions also use the address size prefix to select
434 %cx rather than %ecx for the loop count, so the `w' form of these
435 instructions emit an address size prefix rather than a data size
436 prefix. */
437 {"loop", 1, 0xe2, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} },
438 {"loopz", 1, 0xe1, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} },
439 {"loope", 1, 0xe1, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} },
440 {"loopnz", 1, 0xe0, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} },
441 {"loopne", 1, 0xe0, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} },
442
443 /* Set byte on flag instructions. */
444 {"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
445 {"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
446 {"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
447 {"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
448 {"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
449 {"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
450 {"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
451 {"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
452 {"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
453 {"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
454 {"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
455 {"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
456 {"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
457 {"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
458 {"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
459 {"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
460 {"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
461 {"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
462 {"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
463 {"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
464 {"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
465 {"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
466 {"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
467 {"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
468 {"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
469 {"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
470 {"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
471 {"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
472 {"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
473 {"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
474
475 /* String manipulation. */
476 {"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
477 {"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
478 {"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
479 {"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
480 {"ins", 0, 0x6c, X, Cpu186, bwlq_Suf|W|IsString, { 0, 0, 0} },
481 {"ins", 2, 0x6c, X, Cpu186, bwlq_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
482 {"outs", 0, 0x6e, X, Cpu186, bwlq_Suf|W|IsString, { 0, 0, 0} },
483 {"outs", 2, 0x6e, X, Cpu186, bwlq_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
484 {"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
485 {"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} },
486 {"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} },
487 {"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
488 {"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} },
489 {"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} },
490 {"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
491 {"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
492 {"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
493 {"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
494 {"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
495 {"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
496 {"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
497 {"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
498 {"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
499 {"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
500 {"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
501 {"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
502 {"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
503 {"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
504 {"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
505 {"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
506 {"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} },
507 {"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} },
508
509 /* Bit manipulation. */
510 {"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
511 {"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
512 {"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
513 {"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
514 {"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
515 {"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
516 {"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
517 {"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
518 {"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
519 {"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
520
521 /* Interrupts & op. sys insns. */
522 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
523 int 3 insn. */
524 #define INT_OPCODE 0xcd
525 #define INT3_OPCODE 0xcc
526 {"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} },
527 {"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} },
528 {"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} },
529 {"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
530 /* i386sl, i486sl, later 486, and Pentium. */
531 {"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} },
532
533 {"bound", 2, 0x62, X, Cpu186, wlq_Suf|Modrm, { WordReg, WordMem, 0} },
534
535 {"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} },
536 /* nop is actually 'xchgl %eax, %eax'. */
537 {"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} },
538
539 /* Protection control. */
540 {"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
541 {"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
542 {"lgdt", 1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
543 {"lidt", 1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
544 {"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
545 {"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
546 {"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
547 {"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
548
549 {"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
550 {"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
551 {"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} },
552 {"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} },
553 {"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
554
555 {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
556 {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
557
558 /* Floating point instructions. */
559
560 /* load */
561 {"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
562 {"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
563 {"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
564 /* Intel Syntax */
565 {"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} },
566 {"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
567 /* Intel Syntax */
568 {"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
569 {"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
570 {"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
571 {"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
572 {"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} },
573
574 /* store (no pop) */
575 {"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
576 {"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
577 {"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
578 {"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
579
580 /* store (with pop) */
581 {"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
582 {"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
583 {"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
584 /* Intel Syntax */
585 {"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} },
586 {"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
587 /* Intel Syntax */
588 {"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
589 {"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
590 {"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
591 {"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
592 {"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} },
593
594 /* exchange %st<n> with %st0 */
595 {"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
596 /* alias for fxch %st(1) */
597 {"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} },
598
599 /* comparison (without pop) */
600 {"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
601 /* alias for fcom %st(1) */
602 {"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} },
603 {"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
604 {"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
605 {"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
606
607 /* comparison (with pop) */
608 {"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
609 /* alias for fcomp %st(1) */
610 {"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} },
611 {"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
612 {"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
613 {"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
614 {"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} },
615
616 /* unordered comparison (with pop) */
617 {"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
618 /* alias for fucom %st(1) */
619 {"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} },
620 {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
621 /* alias for fucomp %st(1) */
622 {"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} },
623 {"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} },
624
625 {"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} },
626 {"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} },
627
628 /* load constants into %st0 */
629 {"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} },
630 {"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} },
631 {"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} },
632 {"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} },
633 {"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} },
634 {"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} },
635 {"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} },
636
637 /* arithmetic */
638
639 /* add */
640 {"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
641 /* alias for fadd %st(i), %st */
642 {"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
643 #if SYSV386_COMPAT
644 /* alias for faddp */
645 {"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
646 #endif
647 {"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
648 {"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
649
650 {"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
651 {"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
652 /* alias for faddp %st, %st(1) */
653 {"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} },
654 {"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
655
656 /* subtract */
657 {"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
658 {"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
659 #if SYSV386_COMPAT
660 /* alias for fsubp */
661 {"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
662 #endif
663 {"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
664 {"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
665
666 #if SYSV386_COMPAT
667 {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
668 {"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
669 {"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
670 #if OLDGCC_COMPAT
671 {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
672 #endif
673 #else
674 {"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
675 {"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
676 {"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
677 #endif
678
679 /* subtract reverse */
680 {"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
681 {"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
682 #if SYSV386_COMPAT
683 /* alias for fsubrp */
684 {"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
685 #endif
686 {"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
687 {"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
688
689 #if SYSV386_COMPAT
690 {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
691 {"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
692 {"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
693 #if OLDGCC_COMPAT
694 {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
695 #endif
696 #else
697 {"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
698 {"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
699 {"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
700 #endif
701
702 /* multiply */
703 {"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
704 {"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
705 #if SYSV386_COMPAT
706 /* alias for fmulp */
707 {"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
708 #endif
709 {"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
710 {"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
711
712 {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
713 {"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
714 {"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} },
715 {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
716
717 /* divide */
718 {"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
719 {"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
720 #if SYSV386_COMPAT
721 /* alias for fdivp */
722 {"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
723 #endif
724 {"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
725 {"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
726
727 #if SYSV386_COMPAT
728 {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
729 {"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
730 {"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
731 #if OLDGCC_COMPAT
732 {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
733 #endif
734 #else
735 {"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
736 {"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
737 {"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
738 #endif
739
740 /* divide reverse */
741 {"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
742 {"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
743 #if SYSV386_COMPAT
744 /* alias for fdivrp */
745 {"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
746 #endif
747 {"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
748 {"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
749
750 #if SYSV386_COMPAT
751 {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
752 {"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
753 {"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
754 #if OLDGCC_COMPAT
755 {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
756 #endif
757 #else
758 {"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
759 {"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
760 {"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
761 #endif
762
763 {"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },
764 {"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },
765 {"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} },
766 {"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} },
767 {"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} },
768 {"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} },
769 {"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} },
770 {"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} },
771 {"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} },
772 {"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} },
773 {"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} },
774 {"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} },
775 {"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} },
776 {"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} },
777 {"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} },
778 {"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} },
779 {"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} },
780 {"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} },
781
782 /* processor control */
783 {"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },
784 {"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },
785 {"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} },
786 {"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
787 {"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
788 {"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} },
789 {"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
790 {"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },
791 {"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} },
792 {"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
793 {"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },
794 {"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },
795 {"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },
796 /* Short forms of fldenv, fstenv use data size prefix. */
797 {"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
798 {"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
799 {"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
800 {"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
801 {"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
802 {"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
803
804 {"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
805 /* P6:free st(i), pop st */
806 {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
807 {"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} },
808 #define FWAIT_OPCODE 0x9b
809 {"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} },
810
811 /* Opcode prefixes; we allow them as separate insns too. */
812
813 #define ADDR_PREFIX_OPCODE 0x67
814 {"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
815 {"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
816 {"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
817 {"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
818 #define DATA_PREFIX_OPCODE 0x66
819 {"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
820 {"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
821 {"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
822 {"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
823 #define LOCK_PREFIX_OPCODE 0xf0
824 {"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
825 {"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
826 #define CS_PREFIX_OPCODE 0x2e
827 {"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
828 #define DS_PREFIX_OPCODE 0x3e
829 {"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
830 #define ES_PREFIX_OPCODE 0x26
831 {"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
832 #define FS_PREFIX_OPCODE 0x64
833 {"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
834 #define GS_PREFIX_OPCODE 0x65
835 {"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
836 #define SS_PREFIX_OPCODE 0x36
837 {"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
838 #define REPNE_PREFIX_OPCODE 0xf2
839 #define REPE_PREFIX_OPCODE 0xf3
840 {"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
841 {"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
842 {"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
843 {"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
844 {"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
845 {"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
846 {"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
847 {"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
848 {"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
849 {"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
850 {"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
851 {"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
852 {"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
853 {"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
854 {"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
855 {"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
856 {"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
857 {"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
858 {"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
859 {"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
860 {"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
861
862 /* 486 extensions. */
863
864 {"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } },
865 {"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
866 {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
867 {"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} },
868 {"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} },
869 {"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} },
870
871 /* 586 and late 486 extensions. */
872 {"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} },
873
874 /* Pentium extensions. */
875 {"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} },
876 {"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} },
877 {"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} },
878 {"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} },
879
880 /* Pentium II/Pentium Pro extensions. */
881 {"sysenter",0, 0x0f34, X, Cpu686|CpuNo64, NoSuf, { 0, 0, 0} },
882 {"sysexit", 0, 0x0f35, X, Cpu686|CpuNo64, NoSuf, { 0, 0, 0} },
883 {"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
884 {"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
885 {"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },
886 /* official undefined instr. */
887 {"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
888 /* alias for ud2 */
889 {"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
890 /* 2nd. official undefined instr. */
891 {"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} },
892
893 {"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
894 {"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
895 {"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
896 {"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
897 {"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
898 {"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
899 {"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
900 {"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
901 {"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
902 {"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
903 {"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
904 {"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
905 {"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
906 {"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
907 {"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
908 {"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
909 {"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
910 {"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
911 {"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
912 {"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
913 {"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
914 {"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
915 {"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
916 {"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
917 {"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
918 {"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
919 {"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
920 {"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
921
922 {"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
923 {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
924 {"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
925 {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
926 {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
927 {"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
928 {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
929 {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
930 {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
931 {"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
932 {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
933 {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
934
935 {"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
936 {"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
937 {"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
938 {"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
939 {"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
940 {"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
941 {"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
942 {"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
943 {"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
944 {"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
945 {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
946 {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
947 {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
948 {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
949
950 /* MMX instructions. */
951
952 {"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } },
953 {"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } },
954 {"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } },
955 /* Real MMX instructions. */
956 {"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
957 {"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
958 /* In the 64bit mode the short form mov immediate is redefined to have
959 64bit displacement value. */
960 {"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
961 {"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } },
962 {"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
963 /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit
964 mode they are 64bit.*/
965 {"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
966 {"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
967 {"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
968 {"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
969 {"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
970 {"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
971 {"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
972 {"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
973 {"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
974 {"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
975 {"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
976 {"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
977 {"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
978 {"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
979 {"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
980 {"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
981 {"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
982 {"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
983 {"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
984 {"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
985 {"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
986 {"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
987 {"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
988 {"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
989 {"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
990 {"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
991 {"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
992 {"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
993 {"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
994 {"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
995 {"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
996 {"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
997 {"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
998 {"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
999 {"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1000 {"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
1001 {"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1002 {"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
1003 {"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1004 {"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
1005 {"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1006 {"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1007 {"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1008 {"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1009 {"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1010 {"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1011 {"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1012 {"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1013 {"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1014 {"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1015 {"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1016 {"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1017 {"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1018 {"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1019
1020
1021 /* PIII Katmai New Instructions / SIMD instructions. */
1022
1023 {"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1024 {"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1025 {"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1026 {"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1027 {"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1028 {"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1029 {"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1030 {"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1031 {"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1032 {"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1033 {"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1034 {"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1035 {"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1036 {"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1037 {"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1038 {"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1039 {"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1040 {"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1041 {"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1042 {"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1043 {"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1044 {"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
1045 {"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1046 {"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
1047 {"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1048 {"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } },
1049 {"cvtss2si", 2, 0xf30f2d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
1050 {"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1051 {"cvttss2si", 2, 0xf30f2c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
1052 {"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1053 {"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1054 {"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
1055 {"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
1056 {"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1057 {"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1058 {"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1059 {"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1060 {"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1061 {"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1062 {"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1063 {"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
1064 {"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
1065 {"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1066 {"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
1067 {"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
1068 {"movmskps", 2, 0x0f50, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } },
1069 {"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
1070 {"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } },
1071 {"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1072 {"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
1073 {"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1074 {"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1075 {"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1076 {"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1077 {"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1078 {"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1079 {"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1080 {"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } },
1081 {"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } },
1082 {"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1083 {"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1084 {"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1085 {"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1086 {"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } },
1087 {"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1088 {"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1089 {"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1090 {"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1091 {"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1092 {"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1093 {"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
1094 {"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1095 {"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1096 {"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1097 {"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1098 {"sfence", 0, 0x0faef8, X, CpuSSE, FP, { 0, 0, 0 } },
1099 {"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1100 {"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1101 {"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1102 {"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
1103 {"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1104 {"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1105 {"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1106 {"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1107 {"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1108 {"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1109
1110 /* AMD 3DNow! instructions. */
1111
1112 {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1113 {"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1114 {"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } },
1115 {"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1116 {"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1117 {"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1118 {"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1119 {"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1120 {"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1121 {"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1122 {"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1123 {"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1124 {"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1125 {"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1126 {"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1127 {"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1128 {"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1129 {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1130 {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1131 {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1132 {"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1133 {"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1134 {"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1135 {"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1136 {"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1137 {"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1138 {"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1139
1140 /* AMD extensions. */
1141 {"syscall", 0,0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} },
1142 {"sysret", 0,0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} },
1143 {"swapgs", 0,0x0f01, 7, Cpu64, NoSuf, { 0, 0, 0} },
1144
1145 /* sentinel */
1146 {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
1147 };
1148 #undef X
1149 #undef NoSuf
1150 #undef b_Suf
1151 #undef w_Suf
1152 #undef l_Suf
1153 #undef q_Suf
1154 #undef x_Suf
1155 #undef bw_Suf
1156 #undef bl_Suf
1157 #undef wl_Suf
1158 #undef wlq_Suf
1159 #undef sl_Suf
1160 #undef bwl_Suf
1161 #undef bwlq_Suf
1162 #undef FP
1163 #undef l_FP
1164 #undef x_FP
1165 #undef sl_FP
1166
1167 #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
1168
1169
1170 /* 386 register table. */
1171
1172 static const reg_entry i386_regtab[] = {
1173 /* make %st first as we test for it */
1174 {"st", FloatReg|FloatAcc, 0, 0},
1175 /* 8 bit regs */
1176 {"al", Reg8|Acc, 0, 0},
1177 {"cl", Reg8|ShiftCount, 0, 1},
1178 {"dl", Reg8, 0, 2},
1179 {"bl", Reg8, 0, 3},
1180 {"ah", Reg8, 0, 4},
1181 {"ch", Reg8, 0, 5},
1182 {"dh", Reg8, 0, 6},
1183 {"bh", Reg8, 0, 7},
1184 {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */
1185 {"cxl", Reg8, RegRex64, 1},
1186 {"dxl", Reg8, RegRex64, 2},
1187 {"bxl", Reg8, RegRex64, 3},
1188 {"spl", Reg8, RegRex64, 4},
1189 {"bpl", Reg8, RegRex64, 5},
1190 {"sil", Reg8, RegRex64, 6},
1191 {"dil", Reg8, RegRex64, 7},
1192 {"r8b", Reg8, RegRex64|RegRex, 0},
1193 {"r9b", Reg8, RegRex64|RegRex, 1},
1194 {"r10b", Reg8, RegRex64|RegRex, 2},
1195 {"r11b", Reg8, RegRex64|RegRex, 3},
1196 {"r12b", Reg8, RegRex64|RegRex, 4},
1197 {"r13b", Reg8, RegRex64|RegRex, 5},
1198 {"r14b", Reg8, RegRex64|RegRex, 6},
1199 {"r15b", Reg8, RegRex64|RegRex, 7},
1200 /* 16 bit regs */
1201 {"ax", Reg16|Acc, 0, 0},
1202 {"cx", Reg16, 0, 1},
1203 {"dx", Reg16|InOutPortReg, 0, 2},
1204 {"bx", Reg16|BaseIndex, 0, 3},
1205 {"sp", Reg16, 0, 4},
1206 {"bp", Reg16|BaseIndex, 0, 5},
1207 {"si", Reg16|BaseIndex, 0, 6},
1208 {"di", Reg16|BaseIndex, 0, 7},
1209 {"r8w", Reg16, RegRex, 0},
1210 {"r9w", Reg16, RegRex, 1},
1211 {"r10w", Reg16, RegRex, 2},
1212 {"r11w", Reg16, RegRex, 3},
1213 {"r12w", Reg16, RegRex, 4},
1214 {"r13w", Reg16, RegRex, 5},
1215 {"r14w", Reg16, RegRex, 6},
1216 {"r15w", Reg16, RegRex, 7},
1217 /* 32 bit regs */
1218 {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot */
1219 {"ecx", Reg32|BaseIndex, 0, 1},
1220 {"edx", Reg32|BaseIndex, 0, 2},
1221 {"ebx", Reg32|BaseIndex, 0, 3},
1222 {"esp", Reg32, 0, 4},
1223 {"ebp", Reg32|BaseIndex, 0, 5},
1224 {"esi", Reg32|BaseIndex, 0, 6},
1225 {"edi", Reg32|BaseIndex, 0, 7},
1226 {"r8d", Reg32|BaseIndex, RegRex, 0},
1227 {"r9d", Reg32|BaseIndex, RegRex, 1},
1228 {"r10d", Reg32|BaseIndex, RegRex, 2},
1229 {"r11d", Reg32|BaseIndex, RegRex, 3},
1230 {"r12d", Reg32|BaseIndex, RegRex, 4},
1231 {"r13d", Reg32|BaseIndex, RegRex, 5},
1232 {"r14d", Reg32|BaseIndex, RegRex, 6},
1233 {"r15d", Reg32|BaseIndex, RegRex, 7},
1234 {"rax", Reg64|BaseIndex|Acc, 0, 0},
1235 {"rcx", Reg64|BaseIndex, 0, 1},
1236 {"rdx", Reg64|BaseIndex, 0, 2},
1237 {"rbx", Reg64|BaseIndex, 0, 3},
1238 {"rsp", Reg64, 0, 4},
1239 {"rbp", Reg64|BaseIndex, 0, 5},
1240 {"rsi", Reg64|BaseIndex, 0, 6},
1241 {"rdi", Reg64|BaseIndex, 0, 7},
1242 {"r8", Reg64|BaseIndex, RegRex, 0},
1243 {"r9", Reg64|BaseIndex, RegRex, 1},
1244 {"r10", Reg64|BaseIndex, RegRex, 2},
1245 {"r11", Reg64|BaseIndex, RegRex, 3},
1246 {"r12", Reg64|BaseIndex, RegRex, 4},
1247 {"r13", Reg64|BaseIndex, RegRex, 5},
1248 {"r14", Reg64|BaseIndex, RegRex, 6},
1249 {"r15", Reg64|BaseIndex, RegRex, 7},
1250 /* segment registers */
1251 {"es", SReg2, 0, 0},
1252 {"cs", SReg2, 0, 1},
1253 {"ss", SReg2, 0, 2},
1254 {"ds", SReg2, 0, 3},
1255 {"fs", SReg3, 0, 4},
1256 {"gs", SReg3, 0, 5},
1257 /* control registers */
1258 {"cr0", Control, 0, 0},
1259 {"cr1", Control, 0, 1},
1260 {"cr2", Control, 0, 2},
1261 {"cr3", Control, 0, 3},
1262 {"cr4", Control, 0, 4},
1263 {"cr5", Control, 0, 5},
1264 {"cr6", Control, 0, 6},
1265 {"cr7", Control, 0, 7},
1266 {"cr8", Control, RegRex, 0},
1267 {"cr9", Control, RegRex, 1},
1268 {"cr10", Control, RegRex, 2},
1269 {"cr11", Control, RegRex, 3},
1270 {"cr12", Control, RegRex, 4},
1271 {"cr13", Control, RegRex, 5},
1272 {"cr14", Control, RegRex, 6},
1273 {"cr15", Control, RegRex, 7},
1274 /* debug registers */
1275 {"db0", Debug, 0, 0},
1276 {"db1", Debug, 0, 1},
1277 {"db2", Debug, 0, 2},
1278 {"db3", Debug, 0, 3},
1279 {"db4", Debug, 0, 4},
1280 {"db5", Debug, 0, 5},
1281 {"db6", Debug, 0, 6},
1282 {"db7", Debug, 0, 7},
1283 {"db8", Debug, RegRex, 0},
1284 {"db9", Debug, RegRex, 1},
1285 {"db10", Debug, RegRex, 2},
1286 {"db11", Debug, RegRex, 3},
1287 {"db12", Debug, RegRex, 4},
1288 {"db13", Debug, RegRex, 5},
1289 {"db14", Debug, RegRex, 6},
1290 {"db15", Debug, RegRex, 7},
1291 {"dr0", Debug, 0, 0},
1292 {"dr1", Debug, 0, 1},
1293 {"dr2", Debug, 0, 2},
1294 {"dr3", Debug, 0, 3},
1295 {"dr4", Debug, 0, 4},
1296 {"dr5", Debug, 0, 5},
1297 {"dr6", Debug, 0, 6},
1298 {"dr7", Debug, 0, 7},
1299 {"dr8", Debug, RegRex, 0},
1300 {"dr9", Debug, RegRex, 1},
1301 {"dr10", Debug, RegRex, 2},
1302 {"dr11", Debug, RegRex, 3},
1303 {"dr12", Debug, RegRex, 4},
1304 {"dr13", Debug, RegRex, 5},
1305 {"dr14", Debug, RegRex, 6},
1306 {"dr15", Debug, RegRex, 7},
1307 /* test registers */
1308 {"tr0", Test, 0, 0},
1309 {"tr1", Test, 0, 1},
1310 {"tr2", Test, 0, 2},
1311 {"tr3", Test, 0, 3},
1312 {"tr4", Test, 0, 4},
1313 {"tr5", Test, 0, 5},
1314 {"tr6", Test, 0, 6},
1315 {"tr7", Test, 0, 7},
1316 /* mmx and simd registers */
1317 {"mm0", RegMMX, 0, 0},
1318 {"mm1", RegMMX, 0, 1},
1319 {"mm2", RegMMX, 0, 2},
1320 {"mm3", RegMMX, 0, 3},
1321 {"mm4", RegMMX, 0, 4},
1322 {"mm5", RegMMX, 0, 5},
1323 {"mm6", RegMMX, 0, 6},
1324 {"mm7", RegMMX, 0, 7},
1325 {"xmm0", RegXMM, 0, 0},
1326 {"xmm1", RegXMM, 0, 1},
1327 {"xmm2", RegXMM, 0, 2},
1328 {"xmm3", RegXMM, 0, 3},
1329 {"xmm4", RegXMM, 0, 4},
1330 {"xmm5", RegXMM, 0, 5},
1331 {"xmm6", RegXMM, 0, 6},
1332 {"xmm7", RegXMM, 0, 7},
1333 {"xmm8", RegXMM, RegRex, 0},
1334 {"xmm9", RegXMM, RegRex, 1},
1335 {"xmm10", RegXMM, RegRex, 2},
1336 {"xmm11", RegXMM, RegRex, 3},
1337 {"xmm12", RegXMM, RegRex, 4},
1338 {"xmm13", RegXMM, RegRex, 5},
1339 {"xmm14", RegXMM, RegRex, 6},
1340 {"xmm15", RegXMM, RegRex, 7},
1341 /* no type will make this register rejected for all purposes except
1342 for addressing. This saves creating one extra type for RIP. */
1343 {"rip", BaseIndex, 0, 0}
1344 };
1345
1346 static const reg_entry i386_float_regtab[] = {
1347 {"st(0)", FloatReg|FloatAcc, 0, 0},
1348 {"st(1)", FloatReg, 0, 1},
1349 {"st(2)", FloatReg, 0, 2},
1350 {"st(3)", FloatReg, 0, 3},
1351 {"st(4)", FloatReg, 0, 4},
1352 {"st(5)", FloatReg, 0, 5},
1353 {"st(6)", FloatReg, 0, 6},
1354 {"st(7)", FloatReg, 0, 7}
1355 };
1356
1357 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
1358
1359 /* segment stuff */
1360 static const seg_entry cs = { "cs", 0x2e };
1361 static const seg_entry ds = { "ds", 0x3e };
1362 static const seg_entry ss = { "ss", 0x36 };
1363 static const seg_entry es = { "es", 0x26 };
1364 static const seg_entry fs = { "fs", 0x64 };
1365 static const seg_entry gs = { "gs", 0x65 };
1366
1367 /* end of opcode/i386.h */
GDB Binutils - Deliverables
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