include/opcode/m68k.h

   1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
   3    2003, 2004, 2006 Free Software Foundation, Inc.
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    1, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 /* These are used as bit flags for the arch field in the m68k_opcode
  23    structure.  */
  24 #define _m68k_undef  0
  25 #define m68000   0x001
  26 #define m68010   0x002
  27 #define m68020   0x004
  28 #define m68030   0x008
  29 #define m68040   0x010
  30 #define m68060   0x020
  31 #define m68881   0x040
  32 #define m68851   0x080
  33 #define cpu32    0x100          /* e.g., 68332 */
  34 #define fido_a   0x200
  35 #define m68k_mask  0x3ff
  36
  37 #define mcfmac   0x400          /* ColdFire MAC. */
  38 #define mcfemac  0x800          /* ColdFire EMAC. */
  39 #define cfloat   0x1000         /* ColdFire FPU.  */
  40 #define mcfhwdiv 0x2000         /* ColdFire hardware divide.  */
  41
  42 #define mcfisa_a 0x4000         /* ColdFire ISA_A.  */
  43 #define mcfisa_aa 0x8000        /* ColdFire ISA_A+.  */
  44 #define mcfisa_b 0x10000        /* ColdFire ISA_B.  */
  45 #define mcfisa_c 0x20000        /* ColdFire ISA_C.  */
  46 #define mcfusp   0x40000        /* ColdFire USP instructions.  */
  47 #define mcf_mask 0x7e400
  48
  49 /* Handy aliases.  */
  50 #define m68040up   (m68040 | m68060)
  51 #define m68030up   (m68030 | m68040up)
  52 #define m68020up   (m68020 | m68030up)
  53 #define m68010up   (m68010 | cpu32 | fido_a | m68020up)
  54 #define m68000up   (m68000 | m68010up)
  55
  56 #define mfloat  (m68881 | m68040 | m68060)
  57 #define mmmu    (m68851 | m68030 | m68040 | m68060)
  58
  59 /* The structure used to hold information for an opcode.  */
  60
  61 struct m68k_opcode
  62 {
  63   /* The opcode name.  */
  64   const char *name;
  65   /* The pseudo-size of the instruction(in bytes).  Used to determine
  66      number of bytes necessary to disassemble the instruction.  */
  67   unsigned int size;
  68   /* The opcode itself.  */
  69   unsigned long opcode;
  70   /* The mask used by the disassembler.  */
  71   unsigned long match;
  72   /* The arguments.  */
  73   const char *args;
  74   /* The architectures which support this opcode.  */
  75   unsigned int arch;
  76 };
  77
  78 /* The structure used to hold information for an opcode alias.  */
  79
  80 struct m68k_opcode_alias
  81 {
  82   /* The alias name.  */
  83   const char *alias;
  84   /* The instruction for which this is an alias.  */
  85   const char *primary;
  86 };
  87
  88 /* We store four bytes of opcode for all opcodes because that is the
  89    most any of them need.  The actual length of an instruction is
  90    always at least 2 bytes, and is as much longer as necessary to hold
  91    the operands it has.
  92
  93    The match field is a mask saying which bits must match particular
  94    opcode in order for an instruction to be an instance of that
  95    opcode.
  96
  97    The args field is a string containing two characters for each
  98    operand of the instruction.  The first specifies the kind of
  99    operand; the second, the place it is stored.  */
 100
 101 /* Kinds of operands:
 102    Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
 103
 104    D  data register only.  Stored as 3 bits.
 105    A  address register only.  Stored as 3 bits.
 106    a  address register indirect only.  Stored as 3 bits.
 107    R  either kind of register.  Stored as 4 bits.
 108    r  either kind of register indirect only.  Stored as 4 bits.
 109       At the moment, used only for cas2 instruction.
 110    F  floating point coprocessor register only.   Stored as 3 bits.
 111    O  an offset (or width): immediate data 0-31 or data register.
 112       Stored as 6 bits in special format for BF... insns.
 113    +  autoincrement only.  Stored as 3 bits (number of the address register).
 114    -  autodecrement only.  Stored as 3 bits (number of the address register).
 115    Q  quick immediate data.  Stored as 3 bits.
 116       This matches an immediate operand only when value is in range 1 .. 8.
 117    M  moveq immediate data.  Stored as 8 bits.
 118       This matches an immediate operand only when value is in range -128..127
 119    T  trap vector immediate data.  Stored as 4 bits.
 120
 121    k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
 122       a three bit register offset, depending on the field type.
 123
 124    #  immediate data.  Stored in special places (b, w or l)
 125       which say how many bits to store.
 126    ^  immediate data for floating point instructions.   Special places
 127       are offset by 2 bytes from '#'...
 128    B  pc-relative address, converted to an offset
 129       that is treated as immediate data.
 130    d  displacement and register.  Stores the register as 3 bits
 131       and stores the displacement in the entire second word.
 132
 133    C  the CCR.  No need to store it; this is just for filtering validity.
 134    S  the SR.  No need to store, just as with CCR.
 135    U  the USP.  No need to store, just as with CCR.
 136    E  the MAC ACC.  No need to store, just as with CCR.
 137    e  the EMAC ACC[0123].
 138    G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
 139    g  the EMAC ACCEXT{01,23}.
 140    H  the MASK.  No need to store, just as with CCR.
 141    i  the MAC/EMAC scale factor.
 142
 143    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
 144       extracted from the 'd' field of word one, which means that an extended
 145       coprocessor opcode can be skipped using the 'i' place, if needed.
 146
 147    s  System Control register for the floating point coprocessor.
 148
 149    J  Misc register for movec instruction, stored in 'j' format.
 150         Possible values:
 151         0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
 152         0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
 153         0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
 154         0x003   TC      MMU Translation Control         [60, 40]
 155         0x004   ITT0    Instruction Transparent
 156                                 Translation reg 0       [60, 40]
 157         0x005   ITT1    Instruction Transparent
 158                                 Translation reg 1       [60, 40]
 159         0x006   DTT0    Data Transparent
 160                                 Translation reg 0       [60, 40]
 161         0x007   DTT1    Data Transparent
 162                                 Translation reg 1       [60, 40]
 163         0x008   BUSCR   Bus Control Register            [60]
 164         0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
 165         0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
 166         0x802   CAAR    Cache Address Register          [        30, 20]
 167         0x803   MSP     Master Stack Pointer            [    40, 30, 20]
 168         0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
 169         0x805   MMUSR   MMU Status reg                  [    40]
 170         0x806   URP     User Root Pointer               [60, 40]
 171         0x807   SRP     Supervisor Root Pointer         [60, 40]
 172         0x808   PCR     Processor Configuration reg     [60]
 173         0xC00   ROMBAR  ROM Base Address Register       [520X]
 174         0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
 175         0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
 176         0xC0F   MBAR0   RAM Base Address Register 0     [520X]
 177         0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
 178         0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
 179
 180     L  Register list of the type d0-d7/a0-a7 etc.
 181        (New!  Improved!  Can also hold fp0-fp7, as well!)
 182        The assembler tries to see if the registers match the insn by
 183        looking at where the insn wants them stored.
 184
 185     l  Register list like L, but with all the bits reversed.
 186        Used for going the other way. . .
 187
 188     c  cache identifier which may be "nc" for no cache, "ic"
 189        for instruction cache, "dc" for data cache, or "bc"
 190        for both caches.  Used in cinv and cpush.  Always
 191        stored in position "d".
 192
 193     u  Any register, with ``upper'' or ``lower'' specification.  Used
 194        in the mac instructions with size word.
 195
 196  The remainder are all stored as 6 bits using an address mode and a
 197  register number; they differ in which addressing modes they match.
 198
 199    *  all                                       (modes 0-6,7.0-4)
 200    ~  alterable memory                          (modes 2-6,7.0,7.1)
 201                                                 (not 0,1,7.2-4)
 202    %  alterable                                 (modes 0-6,7.0,7.1)
 203                                                 (not 7.2-4)
 204    ;  data                                      (modes 0,2-6,7.0-4)
 205                                                 (not 1)
 206    @  data, but not immediate                   (modes 0,2-6,7.0-3)
 207                                                 (not 1,7.4)
 208    !  control                                   (modes 2,5,6,7.0-3)
 209                                                 (not 0,1,3,4,7.4)
 210    &  alterable control                         (modes 2,5,6,7.0,7.1)
 211                                                 (not 0,1,3,4,7.2-4)
 212    $  alterable data                            (modes 0,2-6,7.0,7.1)
 213                                                 (not 1,7.2-4)
 214    ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
 215                                                 (not 1,3,4,7.2-4)
 216    /  control, or data register                 (modes 0,2,5,6,7.0-3)
 217                                                 (not 1,3,4,7.4)
 218    >  *save operands                            (modes 2,4,5,6,7.0,7.1)
 219                                                 (not 0,1,3,7.2-4)
 220    <  *restore operands                         (modes 2,3,5,6,7.0-3)
 221                                                 (not 0,1,4,7.4)
 222
 223    coldfire move operands:
 224    m                                            (modes 0-4)
 225    n                                            (modes 5,7.2)
 226    o                                            (modes 6,7.0,7.1,7.3,7.4)
 227    p                                            (modes 0-5)
 228
 229    coldfire bset/bclr/btst/mulsl/mulul operands:
 230    q                                            (modes 0,2-5)
 231    v                                            (modes 0,2-5,7.0,7.1)
 232    b                                            (modes 0,2-5,7.2)
 233    w                                            (modes 2-5,7.2)
 234    y                                            (modes 2,5)
 235    z                                            (modes 2,5,7.2)
 236    x  mov3q immediate operand.
 237    4                                            (modes 2,3,4,5)
 238   */
 239
 240 /* For the 68851:  */
 241 /* I didn't use much imagination in choosing the
 242    following codes, so many of them aren't very
 243    mnemonic. -rab
 244
 245    0  32 bit pmmu register
 246         Possible values:
 247         000     TC      Translation Control Register (68030, 68851)
 248
 249    1  16 bit pmmu register
 250         111     AC      Access Control (68851)
 251
 252    2  8 bit pmmu register
 253         100     CAL     Current Access Level (68851)
 254         101     VAL     Validate Access Level (68851)
 255         110     SCC     Stack Change Control (68851)
 256
 257    3  68030-only pmmu registers (32 bit)
 258         010     TT0     Transparent Translation reg 0
 259                         (aka Access Control reg 0 -- AC0 -- on 68ec030)
 260         011     TT1     Transparent Translation reg 1
 261                         (aka Access Control reg 1 -- AC1 -- on 68ec030)
 262
 263    W  wide pmmu registers
 264         Possible values:
 265         001     DRP     Dma Root Pointer (68851)
 266         010     SRP     Supervisor Root Pointer (68030, 68851)
 267         011     CRP     Cpu Root Pointer (68030, 68851)
 268
 269    f    function code register (68030, 68851)
 270         0       SFC
 271         1       DFC
 272
 273    V    VAL register only (68851)
 274
 275    X    BADx, BACx (16 bit)
 276         100     BAD     Breakpoint Acknowledge Data (68851)
 277         101     BAC     Breakpoint Acknowledge Control (68851)
 278
 279    Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
 280    Z    PCSR (68851)
 281
 282    |    memory          (modes 2-6, 7.*)
 283
 284    t  address test level (68030 only)
 285       Stored as 3 bits, range 0-7.
 286       Also used for breakpoint instruction now.
 287
 288 */
 289
 290 /* Places to put an operand, for non-general operands:
 291    Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
 292
 293    s  source, low bits of first word.
 294    d  dest, shifted 9 in first word
 295    1  second word, shifted 12
 296    2  second word, shifted 6
 297    3  second word, shifted 0
 298    4  third word, shifted 12
 299    5  third word, shifted 6
 300    6  third word, shifted 0
 301    7  second word, shifted 7
 302    8  second word, shifted 10
 303    9  second word, shifted 5
 304    D  store in both place 1 and place 3; for divul and divsl.
 305    B  first word, low byte, for branch displacements
 306    W  second word (entire), for branch displacements
 307    L  second and third words (entire), for branch displacements
 308       (also overloaded for move16)
 309    b  second word, low byte
 310    w  second word (entire) [variable word/long branch offset for dbra]
 311    W  second word (entire) (must be signed 16 bit value)
 312    l  second and third word (entire)
 313    g  variable branch offset for bra and similar instructions.
 314       The place to store depends on the magnitude of offset.
 315    t  store in both place 7 and place 8; for floating point operations
 316    c  branch offset for cpBcc operations.
 317       The place to store is word two if bit six of word one is zero,
 318       and words two and three if bit six of word one is one.
 319    i  Increment by two, to skip over coprocessor extended operands.   Only
 320       works with the 'I' format.
 321    k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
 322       Also used for dynamic fmovem instruction.
 323    C  floating point coprocessor constant - 7 bits.  Also used for static
 324       K-factors...
 325    j  Movec register #, stored in 12 low bits of second word.
 326    m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
 327       and remaining 3 bits of register shifted 9 bits in first word.
 328       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 329       Use with `R' or `u' format.
 330    n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
 331       with MSB shifted 6 bits in first word and remaining 3 bits of
 332       register shifted 9 bits in first word.  No upper/lower
 333       indication is done.)  Use with `R' or `u' format.
 334    o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
 335       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 336       Use with `R' or `u' format.
 337    M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
 338       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 339       `R' or `u' format.
 340    N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
 341       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 342       `R' or `u' format.
 343    h  shift indicator (scale factor), 1 bit shifted 10 in second word
 344
 345  Places to put operand, for general operands:
 346    d  destination, shifted 6 bits in first word
 347    b  source, at low bit of first word, and immediate uses one byte
 348    w  source, at low bit of first word, and immediate uses two bytes
 349    l  source, at low bit of first word, and immediate uses four bytes
 350    s  source, at low bit of first word.
 351       Used sometimes in contexts where immediate is not allowed anyway.
 352    f  single precision float, low bit of 1st word, immediate uses 4 bytes
 353    F  double precision float, low bit of 1st word, immediate uses 8 bytes
 354    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
 355    p  packed float, low bit of 1st word, immediate uses 12 bytes
 356    G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
 357    H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
 358    F  EMAC ACCx
 359    f  EMAC ACCy
 360    I  MAC/EMAC scale factor
 361    /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
 362    ]  first word, bit 10
 363 */
 364
 365 extern const struct m68k_opcode m68k_opcodes[];
 366 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
 367
 368 extern const int m68k_numopcodes, m68k_numaliases;
 369
 370 /* end of m68k-opcode.h */