1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
8 This file is part of GDB, GAS, and the GNU binutils.
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version 3,
13 or (at your option) any later version.
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING3. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
28 /* These are bit masks and shift counts to use to access the various
29 fields of an instruction. To retrieve the X field of an
30 instruction, use the expression
31 (i >> OP_SH_X) & OP_MASK_X
32 To set the same field (to j), use
33 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
35 Make sure you use fields that are appropriate for the instruction,
38 The 'i' format uses OP, RS, RT and IMMEDIATE.
40 The 'j' format uses OP and TARGET.
42 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
44 The 'b' format uses OP, RS, RT and DELTA.
46 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
48 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
50 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
51 breakpoint instruction are not defined; Kane says the breakpoint
52 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
53 only use ten bits). An optional two-operand form of break/sdbbp
54 allows the lower ten bits to be set too, and MIPS32 and later
55 architectures allow 20 bits to be set with a signal operand
58 The syscall instruction uses CODE20.
60 The general coprocessor instructions use COPZ. */
62 #define OP_MASK_OP 0x3f
64 #define OP_MASK_RS 0x1f
66 #define OP_MASK_FR 0x1f
68 #define OP_MASK_FMT 0x1f
70 #define OP_MASK_BCC 0x7
72 #define OP_MASK_CODE 0x3ff
74 #define OP_MASK_CODE2 0x3ff
76 #define OP_MASK_RT 0x1f
78 #define OP_MASK_FT 0x1f
80 #define OP_MASK_CACHE 0x1f
81 #define OP_SH_CACHE 16
82 #define OP_MASK_RD 0x1f
84 #define OP_MASK_FS 0x1f
86 #define OP_MASK_PREFX 0x1f
87 #define OP_SH_PREFX 11
88 #define OP_MASK_CCC 0x7
90 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
91 #define OP_SH_CODE20 6
92 #define OP_MASK_SHAMT 0x1f
94 #define OP_MASK_EXTLSB OP_MASK_SHAMT
95 #define OP_SH_EXTLSB OP_SH_SHAMT
96 #define OP_MASK_STYPE OP_MASK_SHAMT
97 #define OP_SH_STYPE OP_SH_SHAMT
98 #define OP_MASK_FD 0x1f
100 #define OP_MASK_TARGET 0x3ffffff
101 #define OP_SH_TARGET 0
102 #define OP_MASK_COPZ 0x1ffffff
104 #define OP_MASK_IMMEDIATE 0xffff
105 #define OP_SH_IMMEDIATE 0
106 #define OP_MASK_DELTA 0xffff
107 #define OP_SH_DELTA 0
108 #define OP_MASK_FUNCT 0x3f
109 #define OP_SH_FUNCT 0
110 #define OP_MASK_SPEC 0x3f
112 #define OP_SH_LOCC 8 /* FP condition code. */
113 #define OP_SH_HICC 18 /* FP condition code. */
114 #define OP_MASK_CC 0x7
115 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
116 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
117 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
118 #define OP_MASK_COP1SPEC 0xf
119 #define OP_MASK_COP1SCLR 0x4
120 #define OP_MASK_COP1CMP 0x3
121 #define OP_SH_COP1CMP 4
122 #define OP_SH_FORMAT 21 /* FP short format field. */
123 #define OP_MASK_FORMAT 0x7
124 #define OP_SH_TRUE 16
125 #define OP_MASK_TRUE 0x1
127 #define OP_MASK_GE 0x01
128 #define OP_SH_UNSIGNED 16
129 #define OP_MASK_UNSIGNED 0x1
130 #define OP_SH_HINT 16
131 #define OP_MASK_HINT 0x1f
132 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
133 #define OP_MASK_MMI 0x3f
134 #define OP_SH_MMISUB 6
135 #define OP_MASK_MMISUB 0x1f
136 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
137 #define OP_SH_PERFREG 1
138 #define OP_SH_SEL 0 /* Coprocessor select field. */
139 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
140 #define OP_SH_CODE19 6 /* 19 bit wait code. */
141 #define OP_MASK_CODE19 0x7ffff
143 #define OP_MASK_ALN 0x7
144 #define OP_SH_VSEL 21
145 #define OP_MASK_VSEL 0x1f
146 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
147 but 0x8-0xf don't select bytes. */
148 #define OP_SH_VECBYTE 22
149 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
150 #define OP_SH_VECALIGN 21
151 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
152 #define OP_SH_INSMSB 11
153 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
154 #define OP_SH_EXTMSBD 11
157 #define OP_SH_DSPACC 11
158 #define OP_MASK_DSPACC 0x3
159 #define OP_SH_DSPACC_S 21
160 #define OP_MASK_DSPACC_S 0x3
161 #define OP_SH_DSPSFT 20
162 #define OP_MASK_DSPSFT 0x3f
163 #define OP_SH_DSPSFT_7 19
164 #define OP_MASK_DSPSFT_7 0x7f
166 #define OP_MASK_SA3 0x7
168 #define OP_MASK_SA4 0xf
169 #define OP_SH_IMM8 16
170 #define OP_MASK_IMM8 0xff
171 #define OP_SH_IMM10 16
172 #define OP_MASK_IMM10 0x3ff
173 #define OP_SH_WRDSP 11
174 #define OP_MASK_WRDSP 0x3f
175 #define OP_SH_RDDSP 16
176 #define OP_MASK_RDDSP 0x3f
178 #define OP_MASK_BP 0x3
182 #define OP_MASK_MT_U 0x1
184 #define OP_MASK_MT_H 0x1
185 #define OP_SH_MTACC_T 18
186 #define OP_MASK_MTACC_T 0x3
187 #define OP_SH_MTACC_D 13
188 #define OP_MASK_MTACC_D 0x3
190 #define OP_OP_COP0 0x10
191 #define OP_OP_COP1 0x11
192 #define OP_OP_COP2 0x12
193 #define OP_OP_COP3 0x13
194 #define OP_OP_LWC1 0x31
195 #define OP_OP_LWC2 0x32
196 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
197 #define OP_OP_LDC1 0x35
198 #define OP_OP_LDC2 0x36
199 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
200 #define OP_OP_SWC1 0x39
201 #define OP_OP_SWC2 0x3a
202 #define OP_OP_SWC3 0x3b
203 #define OP_OP_SDC1 0x3d
204 #define OP_OP_SDC2 0x3e
205 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
207 /* Values in the 'VSEL' field. */
208 #define MDMX_FMTSEL_IMM_QH 0x1d
209 #define MDMX_FMTSEL_IMM_OB 0x1e
210 #define MDMX_FMTSEL_VEC_QH 0x15
211 #define MDMX_FMTSEL_VEC_OB 0x16
215 #define OP_MASK_UDI1 0x1f
217 #define OP_MASK_UDI2 0x3ff
219 #define OP_MASK_UDI3 0x7fff
221 #define OP_MASK_UDI4 0xfffff
224 #define OP_SH_BBITIND 16
225 #define OP_MASK_BBITIND 0x1f
226 #define OP_SH_CINSPOS 6
227 #define OP_MASK_CINSPOS 0x1f
228 #define OP_SH_CINSLM1 11
229 #define OP_MASK_CINSLM1 0x1f
231 #define OP_MASK_SEQI 0x3ff
234 #define OP_SH_OFFSET_A 6
235 #define OP_MASK_OFFSET_A 0xff
236 #define OP_SH_OFFSET_B 3
237 #define OP_MASK_OFFSET_B 0xff
238 #define OP_SH_OFFSET_C 6
239 #define OP_MASK_OFFSET_C 0x1ff
241 #define OP_MASK_RZ 0x1f
243 #define OP_MASK_FZ 0x1f
245 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
246 definition, and vice versa. This simplifies various parts
247 of the operand handling in GAS. The fields below only exist
248 in the microMIPS encoding, so define each one to have an empty
250 #define OP_MASK_CODE10 0
251 #define OP_SH_CODE10 0
252 #define OP_MASK_TRAP 0
254 #define OP_MASK_OFFSET12 0
255 #define OP_SH_OFFSET12 0
256 #define OP_MASK_OFFSET10 0
257 #define OP_SH_OFFSET10 0
258 #define OP_MASK_RS3 0
288 #define OP_MASK_IMMA 0
290 #define OP_MASK_IMMB 0
292 #define OP_MASK_IMMC 0
294 #define OP_MASK_IMMF 0
296 #define OP_MASK_IMMG 0
298 #define OP_MASK_IMMH 0
300 #define OP_MASK_IMMI 0
302 #define OP_MASK_IMMJ 0
304 #define OP_MASK_IMML 0
306 #define OP_MASK_IMMM 0
308 #define OP_MASK_IMMN 0
310 #define OP_MASK_IMMO 0
312 #define OP_MASK_IMMP 0
314 #define OP_MASK_IMMQ 0
316 #define OP_MASK_IMMU 0
318 #define OP_MASK_IMMW 0
320 #define OP_MASK_IMMX 0
322 #define OP_MASK_IMMY 0
325 /* This structure holds information for a particular instruction. */
329 /* The name of the instruction. */
331 /* A string describing the arguments for this instruction. */
333 /* The basic opcode for the instruction. When assembling, this
334 opcode is modified by the arguments to produce the actual opcode
335 that is used. If pinfo is INSN_MACRO, then this is 0. */
337 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
338 relevant portions of the opcode when disassembling. If the
339 actual opcode anded with the match field equals the opcode field,
340 then we have found the correct instruction. If pinfo is
341 INSN_MACRO, then this field is the macro identifier. */
343 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
344 of bits describing the instruction, notably any relevant hazard
347 /* A collection of additional bits describing the instruction. */
348 unsigned long pinfo2
;
349 /* A collection of bits describing the instruction sets of which this
350 instruction or macro is a member. */
351 unsigned long membership
;
354 /* These are the characters which may appear in the args field of an
355 instruction. They appear in the order in which the fields appear
356 when the instruction is used. Commas and parentheses in the args
357 string are ignored when assembling, and written into the output
360 Each of these characters corresponds to a mask field defined above.
362 "1" 5 bit sync type (OP_*_SHAMT)
363 "<" 5 bit shift amount (OP_*_SHAMT)
364 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
365 "a" 26 bit target address (OP_*_TARGET)
366 "b" 5 bit base register (OP_*_RS)
367 "c" 10 bit breakpoint code (OP_*_CODE)
368 "d" 5 bit destination register specifier (OP_*_RD)
369 "h" 5 bit prefx hint (OP_*_PREFX)
370 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
371 "j" 16 bit signed immediate (OP_*_DELTA)
372 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
373 Also used for immediate operands in vr5400 vector insns.
374 "o" 16 bit signed offset (OP_*_DELTA)
375 "p" 16 bit PC relative branch target address (OP_*_DELTA)
376 "q" 10 bit extra breakpoint code (OP_*_CODE2)
377 "r" 5 bit same register used as both source and target (OP_*_RS)
378 "s" 5 bit source register specifier (OP_*_RS)
379 "t" 5 bit target register (OP_*_RT)
380 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
381 "v" 5 bit same register used as both source and destination (OP_*_RS)
382 "w" 5 bit same register used as both target and destination (OP_*_RT)
383 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
384 (used by clo and clz)
385 "C" 25 bit coprocessor function code (OP_*_COPZ)
386 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
387 "J" 19 bit wait function code (OP_*_CODE19)
388 "x" accept and ignore register name
389 "z" must be zero register
390 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
391 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
392 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
393 microMIPS compatibility).
394 Enforces: 0 <= pos < 32.
395 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
396 Requires that "+A" or "+E" occur first to set position.
397 Enforces: 0 < (pos+size) <= 32.
398 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
399 Requires that "+A" or "+E" occur first to set position.
400 Enforces: 0 < (pos+size) <= 32.
401 (Also used by "dext" w/ different limits, but limits for
402 that are checked by the M_DEXT macro.)
403 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
404 Enforces: 32 <= pos < 64.
405 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
406 Requires that "+A" or "+E" occur first to set position.
407 Enforces: 32 < (pos+size) <= 64.
408 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
409 Requires that "+A" or "+E" occur first to set position.
410 Enforces: 32 < (pos+size) <= 64.
411 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
412 Requires that "+A" or "+E" occur first to set position.
413 Enforces: 32 < (pos+size) <= 64.
415 Floating point instructions:
416 "D" 5 bit destination register (OP_*_FD)
417 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
418 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
419 "S" 5 bit fs source 1 register (OP_*_FS)
420 "T" 5 bit ft source 2 register (OP_*_FT)
421 "R" 5 bit fr source 3 register (OP_*_FR)
422 "V" 5 bit same register used as floating source and destination (OP_*_FS)
423 "W" 5 bit same register used as floating target and destination (OP_*_FT)
425 Coprocessor instructions:
426 "E" 5 bit target register (OP_*_RT)
427 "G" 5 bit destination register (OP_*_RD)
428 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
429 "P" 5 bit performance-monitor register (OP_*_PERFREG)
430 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
431 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
433 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
434 for pretty-printing in disassembly only.
437 "A" General 32 bit expression
438 "I" 32 bit immediate (value placed in imm_expr).
439 "+I" 32 bit immediate (value placed in imm2_expr).
440 "F" 64 bit floating point constant in .rdata
441 "L" 64 bit floating point constant in .lit8
442 "f" 32 bit floating point constant
443 "l" 32 bit floating point constant in .lit4
445 MDMX instruction operands (note that while these use the FP register
446 fields, they accept both $fN and $vN names for the registers):
447 "O" MDMX alignment offset (OP_*_ALN)
448 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
449 "X" MDMX destination register (OP_*_FD)
450 "Y" MDMX source register (OP_*_FS)
451 "Z" MDMX source register (OP_*_FT)
454 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
455 "3" 3 bit unsigned immediate (OP_*_SA3)
456 "4" 4 bit unsigned immediate (OP_*_SA4)
457 "5" 8 bit unsigned immediate (OP_*_IMM8)
458 "6" 5 bit unsigned immediate (OP_*_RS)
459 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
460 "8" 6 bit unsigned immediate (OP_*_WRDSP)
461 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
462 "0" 6 bit signed immediate (OP_*_DSPSFT)
463 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
464 "'" 6 bit unsigned immediate (OP_*_RDDSP)
465 "@" 10 bit signed immediate (OP_*_IMM10)
468 "!" 1 bit usermode flag (OP_*_MT_U)
469 "$" 1 bit load high flag (OP_*_MT_H)
470 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
471 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
472 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
473 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
474 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
477 "+1" UDI immediate bits 6-10
478 "+2" UDI immediate bits 6-15
479 "+3" UDI immediate bits 6-20
480 "+4" UDI immediate bits 6-25
483 "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
484 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
485 otherwise skips to next candidate.
486 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
487 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
488 32 <= pos < 64, otherwise skips to next candidate.
489 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
490 "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
491 "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
492 cint32/exts32. Enforces non-negative value and that
493 pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
494 position field is "+p" or "+P".
497 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
498 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
499 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
500 "+z" 5-bit rz register (OP_*_RZ)
501 "+Z" 5-bit fz register (OP_*_FZ)
504 "()" parens surrounding optional value
505 "," separates operands
506 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
507 "+" Start of extension sequence.
509 Characters used so far, for quick reference when adding more:
512 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
513 "abcdefghijklopqrstuvwxz"
515 Extension character sequences used so far ("+" followed by the
516 following), for quick reference when adding more:
522 /* These are the bits which may be set in the pinfo field of an
523 instructions, if it is not equal to INSN_MACRO. */
525 /* Modifies the general purpose register in OP_*_RD. */
526 #define INSN_WRITE_GPR_D 0x00000001
527 /* Modifies the general purpose register in OP_*_RT. */
528 #define INSN_WRITE_GPR_T 0x00000002
529 /* Modifies general purpose register 31. */
530 #define INSN_WRITE_GPR_31 0x00000004
531 /* Modifies the floating point register in OP_*_FD. */
532 #define INSN_WRITE_FPR_D 0x00000008
533 /* Modifies the floating point register in OP_*_FS. */
534 #define INSN_WRITE_FPR_S 0x00000010
535 /* Modifies the floating point register in OP_*_FT. */
536 #define INSN_WRITE_FPR_T 0x00000020
537 /* Reads the general purpose register in OP_*_RS. */
538 #define INSN_READ_GPR_S 0x00000040
539 /* Reads the general purpose register in OP_*_RT. */
540 #define INSN_READ_GPR_T 0x00000080
541 /* Reads the floating point register in OP_*_FS. */
542 #define INSN_READ_FPR_S 0x00000100
543 /* Reads the floating point register in OP_*_FT. */
544 #define INSN_READ_FPR_T 0x00000200
545 /* Reads the floating point register in OP_*_FR. */
546 #define INSN_READ_FPR_R 0x00000400
547 /* Modifies coprocessor condition code. */
548 #define INSN_WRITE_COND_CODE 0x00000800
549 /* Reads coprocessor condition code. */
550 #define INSN_READ_COND_CODE 0x00001000
552 #define INSN_TLB 0x00002000
553 /* Reads coprocessor register other than floating point register. */
554 #define INSN_COP 0x00004000
555 /* Instruction loads value from memory, requiring delay. */
556 #define INSN_LOAD_MEMORY_DELAY 0x00008000
557 /* Instruction loads value from coprocessor, requiring delay. */
558 #define INSN_LOAD_COPROC_DELAY 0x00010000
559 /* Instruction has unconditional branch delay slot. */
560 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
561 /* Instruction has conditional branch delay slot. */
562 #define INSN_COND_BRANCH_DELAY 0x00040000
563 /* Conditional branch likely: if branch not taken, insn nullified. */
564 #define INSN_COND_BRANCH_LIKELY 0x00080000
565 /* Moves to coprocessor register, requiring delay. */
566 #define INSN_COPROC_MOVE_DELAY 0x00100000
567 /* Loads coprocessor register from memory, requiring delay. */
568 #define INSN_COPROC_MEMORY_DELAY 0x00200000
569 /* Reads the HI register. */
570 #define INSN_READ_HI 0x00400000
571 /* Reads the LO register. */
572 #define INSN_READ_LO 0x00800000
573 /* Modifies the HI register. */
574 #define INSN_WRITE_HI 0x01000000
575 /* Modifies the LO register. */
576 #define INSN_WRITE_LO 0x02000000
577 /* Not to be placed in a branch delay slot, either architecturally
578 or for ease of handling (such as with instructions that take a trap). */
579 #define INSN_NO_DELAY_SLOT 0x04000000
580 /* Instruction stores value into memory. */
581 #define INSN_STORE_MEMORY 0x08000000
582 /* Instruction uses single precision floating point. */
583 #define FP_S 0x10000000
584 /* Instruction uses double precision floating point. */
585 #define FP_D 0x20000000
586 /* Instruction is part of the tx39's integer multiply family. */
587 #define INSN_MULT 0x40000000
588 /* Instruction is actually a macro. It should be ignored by the
589 disassembler, and requires special treatment by the assembler. */
590 #define INSN_MACRO 0xffffffff
592 /* These are the bits which may be set in the pinfo2 field of an
595 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
596 #define INSN2_ALIAS 0x00000001
597 /* Instruction reads MDMX accumulator. */
598 #define INSN2_READ_MDMX_ACC 0x00000002
599 /* Instruction writes MDMX accumulator. */
600 #define INSN2_WRITE_MDMX_ACC 0x00000004
601 /* Macro uses single-precision floating-point instructions. This should
602 only be set for macros. For instructions, FP_S in pinfo carries the
604 #define INSN2_M_FP_S 0x00000008
605 /* Macro uses double-precision floating-point instructions. This should
606 only be set for macros. For instructions, FP_D in pinfo carries the
608 #define INSN2_M_FP_D 0x00000010
609 /* Modifies the general purpose register in OP_*_RZ. */
610 #define INSN2_WRITE_GPR_Z 0x00000020
611 /* Modifies the floating point register in OP_*_FZ. */
612 #define INSN2_WRITE_FPR_Z 0x00000040
613 /* Reads the general purpose register in OP_*_RZ. */
614 #define INSN2_READ_GPR_Z 0x00000080
615 /* Reads the floating point register in OP_*_FZ. */
616 #define INSN2_READ_FPR_Z 0x00000100
617 /* Reads the general purpose register in OP_*_RD. */
618 #define INSN2_READ_GPR_D 0x00000200
621 /* Instruction has a branch delay slot that requires a 16-bit instruction. */
622 #define INSN2_BRANCH_DELAY_16BIT 0x00000400
623 /* Instruction has a branch delay slot that requires a 32-bit instruction. */
624 #define INSN2_BRANCH_DELAY_32BIT 0x00000800
625 /* Modifies the general purpose register in MICROMIPSOP_*_RS. */
626 #define INSN2_WRITE_GPR_S 0x00001000
627 /* Reads the floating point register in MICROMIPSOP_*_FD. */
628 #define INSN2_READ_FPR_D 0x00002000
629 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MB. */
630 #define INSN2_MOD_GPR_MB 0x00004000
631 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MC. */
632 #define INSN2_MOD_GPR_MC 0x00008000
633 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MD. */
634 #define INSN2_MOD_GPR_MD 0x00010000
635 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_ME. */
636 #define INSN2_MOD_GPR_ME 0x00020000
637 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MF. */
638 #define INSN2_MOD_GPR_MF 0x00040000
639 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MG. */
640 #define INSN2_MOD_GPR_MG 0x00080000
641 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MJ. */
642 #define INSN2_MOD_GPR_MJ 0x00100000
643 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MP. */
644 #define INSN2_MOD_GPR_MP 0x00200000
645 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MQ. */
646 #define INSN2_MOD_GPR_MQ 0x00400000
647 /* Reads/Writes the stack pointer ($29). */
648 #define INSN2_MOD_SP 0x00800000
649 /* Reads the RA ($31) register. */
650 #define INSN2_READ_GPR_31 0x01000000
651 /* Reads the global pointer ($28). */
652 #define INSN2_READ_GP 0x02000000
653 /* Reads the program counter ($pc). */
654 #define INSN2_READ_PC 0x04000000
655 /* Is an unconditional branch insn. */
656 #define INSN2_UNCOND_BRANCH 0x08000000
657 /* Is a conditional branch insn. */
658 #define INSN2_COND_BRANCH 0x10000000
659 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MH/I. */
660 #define INSN2_MOD_GPR_MHI 0x20000000
661 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MM. */
662 #define INSN2_MOD_GPR_MM 0x40000000
663 /* Reads/Writes the general purpose registers in MICROMIPSOP_*_MN. */
664 #define INSN2_MOD_GPR_MN 0x80000000
666 /* Masks used to mark instructions to indicate which MIPS ISA level
667 they were introduced in. INSN_ISA_MASK masks an enumeration that
668 specifies the base ISA level(s). The remainder of a 32-bit
669 word constructed using these macros is a bitmask of the remaining
670 INSN_* values below. */
672 #define INSN_ISA_MASK 0x0000000ful
674 /* We cannot start at zero due to ISA_UNKNOWN below. */
681 #define INSN_ISA32R2 7
683 #define INSN_ISA64R2 9
684 /* Below this point the INSN_* values correspond to combinations of ISAs.
685 They are only for use in the opcodes table to indicate membership of
686 a combination of ISAs that cannot be expressed using the usual inclusion
687 ordering on the above INSN_* values. */
688 #define INSN_ISA3_32 10
689 #define INSN_ISA3_32R2 11
690 #define INSN_ISA4_32 12
691 #define INSN_ISA4_32R2 13
692 #define INSN_ISA5_32R2 14
694 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
695 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
696 this table describes whether at least one of the ISAs described by X
697 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
698 a particular core and X as the ISA level(s) at which a certain instruction
699 is defined.) The ISA(s) described by X is/are implemented by Y iff
700 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
702 static const unsigned int mips_isa_table
[] =
703 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
705 /* Masks used for Chip specific instructions. */
706 #define INSN_CHIP_MASK 0xc3ff0c20
708 /* Cavium Networks Octeon instructions. */
709 #define INSN_OCTEON 0x00000800
711 /* Masks used for MIPS-defined ASEs. */
712 #define INSN_ASE_MASK 0x3c00f000
715 #define INSN_DSP 0x00001000
716 #define INSN_DSP64 0x00002000
718 /* 0x00004000 is unused. */
721 #define INSN_MIPS3D 0x00008000
723 /* MIPS R4650 instruction. */
724 #define INSN_4650 0x00010000
725 /* LSI R4010 instruction. */
726 #define INSN_4010 0x00020000
727 /* NEC VR4100 instruction. */
728 #define INSN_4100 0x00040000
729 /* Toshiba R3900 instruction. */
730 #define INSN_3900 0x00080000
731 /* MIPS R10000 instruction. */
732 #define INSN_10000 0x00100000
733 /* Broadcom SB-1 instruction. */
734 #define INSN_SB1 0x00200000
735 /* NEC VR4111/VR4181 instruction. */
736 #define INSN_4111 0x00400000
737 /* NEC VR4120 instruction. */
738 #define INSN_4120 0x00800000
739 /* NEC VR5400 instruction. */
740 #define INSN_5400 0x01000000
741 /* NEC VR5500 instruction. */
742 #define INSN_5500 0x02000000
745 #define INSN_MDMX 0x04000000
747 #define INSN_MT 0x08000000
749 #define INSN_SMARTMIPS 0x10000000
751 #define INSN_DSPR2 0x20000000
752 /* ST Microelectronics Loongson 2E. */
753 #define INSN_LOONGSON_2E 0x40000000
754 /* ST Microelectronics Loongson 2F. */
755 #define INSN_LOONGSON_2F 0x80000000
757 #define INSN_LOONGSON_3A 0x00000400
758 /* RMI Xlr instruction */
759 #define INSN_XLR 0x00000020
761 /* MIPS ISA defines, use instead of hardcoding ISA level. */
763 #define ISA_UNKNOWN 0 /* Gas internal use. */
764 #define ISA_MIPS1 INSN_ISA1
765 #define ISA_MIPS2 INSN_ISA2
766 #define ISA_MIPS3 INSN_ISA3
767 #define ISA_MIPS4 INSN_ISA4
768 #define ISA_MIPS5 INSN_ISA5
770 #define ISA_MIPS32 INSN_ISA32
771 #define ISA_MIPS64 INSN_ISA64
773 #define ISA_MIPS32R2 INSN_ISA32R2
774 #define ISA_MIPS64R2 INSN_ISA64R2
777 /* CPU defines, use instead of hardcoding processor number. Keep this
778 in sync with bfd/archures.c in order for machine selection to work. */
779 #define CPU_UNKNOWN 0 /* Gas internal use. */
780 #define CPU_R3000 3000
781 #define CPU_R3900 3900
782 #define CPU_R4000 4000
783 #define CPU_R4010 4010
784 #define CPU_VR4100 4100
785 #define CPU_R4111 4111
786 #define CPU_VR4120 4120
787 #define CPU_R4300 4300
788 #define CPU_R4400 4400
789 #define CPU_R4600 4600
790 #define CPU_R4650 4650
791 #define CPU_R5000 5000
792 #define CPU_VR5400 5400
793 #define CPU_VR5500 5500
794 #define CPU_R6000 6000
795 #define CPU_RM7000 7000
796 #define CPU_R8000 8000
797 #define CPU_RM9000 9000
798 #define CPU_R10000 10000
799 #define CPU_R12000 12000
800 #define CPU_R14000 14000
801 #define CPU_R16000 16000
802 #define CPU_MIPS16 16
803 #define CPU_MIPS32 32
804 #define CPU_MIPS32R2 33
806 #define CPU_MIPS64 64
807 #define CPU_MIPS64R2 65
808 #define CPU_SB1 12310201 /* octal 'SB', 01. */
809 #define CPU_LOONGSON_2E 3001
810 #define CPU_LOONGSON_2F 3002
811 #define CPU_LOONGSON_3A 3003
812 #define CPU_OCTEON 6501
813 #define CPU_XLR 887682 /* decimal 'XLR' */
815 /* Test for membership in an ISA including chip specific ISAs. INSN
816 is pointer to an element of the opcode table; ISA is the specified
817 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
818 test, or zero if no CPU specific ISA test is desired. */
820 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
821 (((isa & INSN_ISA_MASK) != 0 \
822 && ((insn)->membership & INSN_ISA_MASK) != 0 \
823 && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
824 (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
825 || ((isa & ~INSN_ISA_MASK) \
826 & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
827 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
828 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
829 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
830 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
831 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
832 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
833 || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
834 || cpu == CPU_R16000) \
835 && ((insn)->membership & INSN_10000) != 0) \
836 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
837 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
838 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
839 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
840 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
841 || (cpu == CPU_LOONGSON_2E \
842 && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
843 || (cpu == CPU_LOONGSON_2F \
844 && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
845 || (cpu == CPU_LOONGSON_3A \
846 && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
847 || (cpu == CPU_OCTEON \
848 && ((insn)->membership & INSN_OCTEON) != 0) \
849 || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
850 || 0) /* Please keep this term for easier source merging. */
852 /* This is a list of macro expanded instructions.
854 _I appended means immediate
855 _A appended means address
856 _AB appended means address with base register
857 _D appended means 64 bit floating point constant
858 _S appended means 32 bit floating point constant. */
1147 /* The order of overloaded instructions matters. Label arguments and
1148 register arguments look the same. Instructions that can have either
1149 for arguments must apear in the correct order in this table for the
1150 assembler to pick the right one. In other words, entries with
1151 immediate operands must apear after the same instruction with
1154 Many instructions are short hand for other instructions (i.e., The
1155 jal <register> instruction is short for jalr <register>). */
1157 extern const struct mips_opcode mips_builtin_opcodes
[];
1158 extern const int bfd_mips_num_builtin_opcodes
;
1159 extern struct mips_opcode
*mips_opcodes
;
1160 extern int bfd_mips_num_opcodes
;
1161 #define NUMOPCODES bfd_mips_num_opcodes
1164 /* The rest of this file adds definitions for the mips16 TinyRISC
1167 /* These are the bitmasks and shift counts used for the different
1168 fields in the instruction formats. Other than OP, no masks are
1169 provided for the fixed portions of an instruction, since they are
1172 The I format uses IMM11.
1174 The RI format uses RX and IMM8.
1176 The RR format uses RX, and RY.
1178 The RRI format uses RX, RY, and IMM5.
1180 The RRR format uses RX, RY, and RZ.
1182 The RRI_A format uses RX, RY, and IMM4.
1184 The SHIFT format uses RX, RY, and SHAMT.
1186 The I8 format uses IMM8.
1188 The I8_MOVR32 format uses RY and REGR32.
1190 The IR_MOV32R format uses REG32R and MOV32Z.
1192 The I64 format uses IMM8.
1194 The RI64 format uses RY and IMM5.
1197 #define MIPS16OP_MASK_OP 0x1f
1198 #define MIPS16OP_SH_OP 11
1199 #define MIPS16OP_MASK_IMM11 0x7ff
1200 #define MIPS16OP_SH_IMM11 0
1201 #define MIPS16OP_MASK_RX 0x7
1202 #define MIPS16OP_SH_RX 8
1203 #define MIPS16OP_MASK_IMM8 0xff
1204 #define MIPS16OP_SH_IMM8 0
1205 #define MIPS16OP_MASK_RY 0x7
1206 #define MIPS16OP_SH_RY 5
1207 #define MIPS16OP_MASK_IMM5 0x1f
1208 #define MIPS16OP_SH_IMM5 0
1209 #define MIPS16OP_MASK_RZ 0x7
1210 #define MIPS16OP_SH_RZ 2
1211 #define MIPS16OP_MASK_IMM4 0xf
1212 #define MIPS16OP_SH_IMM4 0
1213 #define MIPS16OP_MASK_REGR32 0x1f
1214 #define MIPS16OP_SH_REGR32 0
1215 #define MIPS16OP_MASK_REG32R 0x1f
1216 #define MIPS16OP_SH_REG32R 3
1217 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1218 #define MIPS16OP_MASK_MOVE32Z 0x7
1219 #define MIPS16OP_SH_MOVE32Z 0
1220 #define MIPS16OP_MASK_IMM6 0x3f
1221 #define MIPS16OP_SH_IMM6 5
1223 /* These are the characters which may appears in the args field of a MIPS16
1224 instruction. They appear in the order in which the fields appear when the
1225 instruction is used. Commas and parentheses in the args string are ignored
1226 when assembling, and written into the output when disassembling.
1228 "y" 3 bit register (MIPS16OP_*_RY)
1229 "x" 3 bit register (MIPS16OP_*_RX)
1230 "z" 3 bit register (MIPS16OP_*_RZ)
1231 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1232 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1233 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1234 "0" zero register ($0)
1235 "S" stack pointer ($sp or $29)
1237 "R" return address register ($ra or $31)
1238 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1239 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1240 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1241 "a" 26 bit jump address
1242 "e" 11 bit extension value
1243 "l" register list for entry instruction
1244 "L" register list for exit instruction
1246 The remaining codes may be extended. Except as otherwise noted,
1247 the full extended operand is a 16 bit signed value.
1248 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1249 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1250 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1251 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1252 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1253 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1254 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1255 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1256 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1257 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1258 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1259 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1260 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1261 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1262 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1263 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1264 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1265 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1266 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1267 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1268 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1269 "m" 7 bit register list for save instruction (18 bit extended)
1270 "M" 7 bit register list for restore instruction (18 bit extended)
1273 /* Save/restore encoding for the args field when all 4 registers are
1274 either saved as arguments or saved/restored as statics. */
1275 #define MIPS16_ALL_ARGS 0xe
1276 #define MIPS16_ALL_STATICS 0xb
1278 /* For the mips16, we use the same opcode table format and a few of
1279 the same flags. However, most of the flags are different. */
1281 /* Modifies the register in MIPS16OP_*_RX. */
1282 #define MIPS16_INSN_WRITE_X 0x00000001
1283 /* Modifies the register in MIPS16OP_*_RY. */
1284 #define MIPS16_INSN_WRITE_Y 0x00000002
1285 /* Modifies the register in MIPS16OP_*_RZ. */
1286 #define MIPS16_INSN_WRITE_Z 0x00000004
1287 /* Modifies the T ($24) register. */
1288 #define MIPS16_INSN_WRITE_T 0x00000008
1289 /* Modifies the SP ($29) register. */
1290 #define MIPS16_INSN_WRITE_SP 0x00000010
1291 /* Modifies the RA ($31) register. */
1292 #define MIPS16_INSN_WRITE_31 0x00000020
1293 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1294 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1295 /* Reads the register in MIPS16OP_*_RX. */
1296 #define MIPS16_INSN_READ_X 0x00000080
1297 /* Reads the register in MIPS16OP_*_RY. */
1298 #define MIPS16_INSN_READ_Y 0x00000100
1299 /* Reads the register in MIPS16OP_*_MOVE32Z. */
1300 #define MIPS16_INSN_READ_Z 0x00000200
1301 /* Reads the T ($24) register. */
1302 #define MIPS16_INSN_READ_T 0x00000400
1303 /* Reads the SP ($29) register. */
1304 #define MIPS16_INSN_READ_SP 0x00000800
1305 /* Reads the RA ($31) register. */
1306 #define MIPS16_INSN_READ_31 0x00001000
1307 /* Reads the program counter. */
1308 #define MIPS16_INSN_READ_PC 0x00002000
1309 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
1310 #define MIPS16_INSN_READ_GPR_X 0x00004000
1311 /* Is an unconditional branch insn. */
1312 #define MIPS16_INSN_UNCOND_BRANCH 0x00008000
1313 /* Is a conditional branch insn. */
1314 #define MIPS16_INSN_COND_BRANCH 0x00010000
1316 /* The following flags have the same value for the mips16 opcode
1318 INSN_UNCOND_BRANCH_DELAY
1319 INSN_COND_BRANCH_DELAY
1320 INSN_COND_BRANCH_LIKELY (never used)
1329 extern const struct mips_opcode mips16_opcodes
[];
1330 extern const int bfd_mips16_num_opcodes
;
1332 /* These are the bitmasks and shift counts used for the different
1333 fields in the instruction formats. Other than MAJOR, no masks are
1334 provided for the fixed portions of an instruction, since they are
1337 #define MICROMIPSOP_MASK_MAJOR 0x3f
1338 #define MICROMIPSOP_SH_MAJOR 26
1339 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff
1340 #define MICROMIPSOP_SH_IMMEDIATE 0
1341 #define MICROMIPSOP_MASK_DELTA 0xffff
1342 #define MICROMIPSOP_SH_DELTA 0
1343 #define MICROMIPSOP_MASK_CODE10 0x3ff
1344 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
1345 #define MICROMIPSOP_MASK_TRAP 0xf
1346 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
1347 #define MICROMIPSOP_MASK_SHAMT 0x1f
1348 #define MICROMIPSOP_SH_SHAMT 11
1349 #define MICROMIPSOP_MASK_TARGET 0x3ffffff
1350 #define MICROMIPSOP_SH_TARGET 0
1351 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
1352 #define MICROMIPSOP_SH_EXTLSB 6
1353 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
1354 #define MICROMIPSOP_SH_EXTMSBD 11
1355 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
1356 #define MICROMIPSOP_SH_INSMSB 11
1357 #define MICROMIPSOP_MASK_CODE 0x3ff
1358 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
1359 #define MICROMIPSOP_MASK_CODE2 0x3ff
1360 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
1361 #define MICROMIPSOP_MASK_CACHE 0x1f
1362 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
1363 #define MICROMIPSOP_MASK_SEL 0x7
1364 #define MICROMIPSOP_SH_SEL 11
1365 #define MICROMIPSOP_MASK_OFFSET12 0xfff
1366 #define MICROMIPSOP_SH_OFFSET12 0
1367 #define MICROMIPSOP_MASK_STYPE 0x1f
1368 #define MICROMIPSOP_SH_STYPE 16
1369 #define MICROMIPSOP_MASK_OFFSET10 0x3ff
1370 #define MICROMIPSOP_SH_OFFSET10 6
1371 #define MICROMIPSOP_MASK_RS 0x1f
1372 #define MICROMIPSOP_SH_RS 16
1373 #define MICROMIPSOP_MASK_RT 0x1f
1374 #define MICROMIPSOP_SH_RT 21
1375 #define MICROMIPSOP_MASK_RD 0x1f
1376 #define MICROMIPSOP_SH_RD 11
1377 #define MICROMIPSOP_MASK_FS 0x1f
1378 #define MICROMIPSOP_SH_FS 16
1379 #define MICROMIPSOP_MASK_FT 0x1f
1380 #define MICROMIPSOP_SH_FT 21
1381 #define MICROMIPSOP_MASK_FD 0x1f
1382 #define MICROMIPSOP_SH_FD 11
1383 #define MICROMIPSOP_MASK_FR 0x1f
1384 #define MICROMIPSOP_SH_FR 6
1385 #define MICROMIPSOP_MASK_RS3 0x1f
1386 #define MICROMIPSOP_SH_RS3 6
1387 #define MICROMIPSOP_MASK_PREFX 0x1f
1388 #define MICROMIPSOP_SH_PREFX 11
1389 #define MICROMIPSOP_MASK_BCC 0x7
1390 #define MICROMIPSOP_SH_BCC 18
1391 #define MICROMIPSOP_MASK_CCC 0x7
1392 #define MICROMIPSOP_SH_CCC 13
1393 #define MICROMIPSOP_MASK_COPZ 0x7fffff
1394 #define MICROMIPSOP_SH_COPZ 3
1396 #define MICROMIPSOP_MASK_MB 0x7
1397 #define MICROMIPSOP_SH_MB 23
1398 #define MICROMIPSOP_MASK_MC 0x7
1399 #define MICROMIPSOP_SH_MC 4
1400 #define MICROMIPSOP_MASK_MD 0x7
1401 #define MICROMIPSOP_SH_MD 7
1402 #define MICROMIPSOP_MASK_ME 0x7
1403 #define MICROMIPSOP_SH_ME 1
1404 #define MICROMIPSOP_MASK_MF 0x7
1405 #define MICROMIPSOP_SH_MF 3
1406 #define MICROMIPSOP_MASK_MG 0x7
1407 #define MICROMIPSOP_SH_MG 0
1408 #define MICROMIPSOP_MASK_MH 0x7
1409 #define MICROMIPSOP_SH_MH 7
1410 #define MICROMIPSOP_MASK_MI 0x7
1411 #define MICROMIPSOP_SH_MI 7
1412 #define MICROMIPSOP_MASK_MJ 0x1f
1413 #define MICROMIPSOP_SH_MJ 0
1414 #define MICROMIPSOP_MASK_ML 0x7
1415 #define MICROMIPSOP_SH_ML 4
1416 #define MICROMIPSOP_MASK_MM 0x7
1417 #define MICROMIPSOP_SH_MM 1
1418 #define MICROMIPSOP_MASK_MN 0x7
1419 #define MICROMIPSOP_SH_MN 4
1420 #define MICROMIPSOP_MASK_MP 0x1f
1421 #define MICROMIPSOP_SH_MP 5
1422 #define MICROMIPSOP_MASK_MQ 0x7
1423 #define MICROMIPSOP_SH_MQ 7
1425 #define MICROMIPSOP_MASK_IMMA 0x7f
1426 #define MICROMIPSOP_SH_IMMA 0
1427 #define MICROMIPSOP_MASK_IMMB 0x7
1428 #define MICROMIPSOP_SH_IMMB 1
1429 #define MICROMIPSOP_MASK_IMMC 0xf
1430 #define MICROMIPSOP_SH_IMMC 0
1431 #define MICROMIPSOP_MASK_IMMD 0x3ff
1432 #define MICROMIPSOP_SH_IMMD 0
1433 #define MICROMIPSOP_MASK_IMME 0x7f
1434 #define MICROMIPSOP_SH_IMME 0
1435 #define MICROMIPSOP_MASK_IMMF 0xf
1436 #define MICROMIPSOP_SH_IMMF 0
1437 #define MICROMIPSOP_MASK_IMMG 0xf
1438 #define MICROMIPSOP_SH_IMMG 0
1439 #define MICROMIPSOP_MASK_IMMH 0xf
1440 #define MICROMIPSOP_SH_IMMH 0
1441 #define MICROMIPSOP_MASK_IMMI 0x7f
1442 #define MICROMIPSOP_SH_IMMI 0
1443 #define MICROMIPSOP_MASK_IMMJ 0xf
1444 #define MICROMIPSOP_SH_IMMJ 0
1445 #define MICROMIPSOP_MASK_IMML 0xf
1446 #define MICROMIPSOP_SH_IMML 0
1447 #define MICROMIPSOP_MASK_IMMM 0x7
1448 #define MICROMIPSOP_SH_IMMM 1
1449 #define MICROMIPSOP_MASK_IMMN 0x3
1450 #define MICROMIPSOP_SH_IMMN 4
1451 #define MICROMIPSOP_MASK_IMMO 0xf
1452 #define MICROMIPSOP_SH_IMMO 0
1453 #define MICROMIPSOP_MASK_IMMP 0x1f
1454 #define MICROMIPSOP_SH_IMMP 0
1455 #define MICROMIPSOP_MASK_IMMQ 0x7fffff
1456 #define MICROMIPSOP_SH_IMMQ 0
1457 #define MICROMIPSOP_MASK_IMMU 0x1f
1458 #define MICROMIPSOP_SH_IMMU 0
1459 #define MICROMIPSOP_MASK_IMMW 0x3f
1460 #define MICROMIPSOP_SH_IMMW 1
1461 #define MICROMIPSOP_MASK_IMMX 0xf
1462 #define MICROMIPSOP_SH_IMMX 1
1463 #define MICROMIPSOP_MASK_IMMY 0x1ff
1464 #define MICROMIPSOP_SH_IMMY 1
1466 /* Placeholders for fields that only exist in the traditional 32-bit
1467 instruction encoding; see the comment above for details. */
1468 #define MICROMIPSOP_MASK_CODE20 0
1469 #define MICROMIPSOP_SH_CODE20 0
1470 #define MICROMIPSOP_MASK_PERFREG 0
1471 #define MICROMIPSOP_SH_PERFREG 0
1472 #define MICROMIPSOP_MASK_CODE19 0
1473 #define MICROMIPSOP_SH_CODE19 0
1474 #define MICROMIPSOP_MASK_ALN 0
1475 #define MICROMIPSOP_SH_ALN 0
1476 #define MICROMIPSOP_MASK_VECBYTE 0
1477 #define MICROMIPSOP_SH_VECBYTE 0
1478 #define MICROMIPSOP_MASK_VECALIGN 0
1479 #define MICROMIPSOP_SH_VECALIGN 0
1480 #define MICROMIPSOP_MASK_DSPACC 0
1481 #define MICROMIPSOP_SH_DSPACC 0
1482 #define MICROMIPSOP_MASK_DSPACC_S 0
1483 #define MICROMIPSOP_SH_DSPACC_S 0
1484 #define MICROMIPSOP_MASK_DSPSFT 0
1485 #define MICROMIPSOP_SH_DSPSFT 0
1486 #define MICROMIPSOP_MASK_DSPSFT_7 0
1487 #define MICROMIPSOP_SH_DSPSFT_7 0
1488 #define MICROMIPSOP_MASK_SA3 0
1489 #define MICROMIPSOP_SH_SA3 0
1490 #define MICROMIPSOP_MASK_SA4 0
1491 #define MICROMIPSOP_SH_SA4 0
1492 #define MICROMIPSOP_MASK_IMM8 0
1493 #define MICROMIPSOP_SH_IMM8 0
1494 #define MICROMIPSOP_MASK_IMM10 0
1495 #define MICROMIPSOP_SH_IMM10 0
1496 #define MICROMIPSOP_MASK_WRDSP 0
1497 #define MICROMIPSOP_SH_WRDSP 0
1498 #define MICROMIPSOP_MASK_RDDSP 0
1499 #define MICROMIPSOP_SH_RDDSP 0
1500 #define MICROMIPSOP_MASK_BP 0
1501 #define MICROMIPSOP_SH_BP 0
1502 #define MICROMIPSOP_MASK_MT_U 0
1503 #define MICROMIPSOP_SH_MT_U 0
1504 #define MICROMIPSOP_MASK_MT_H 0
1505 #define MICROMIPSOP_SH_MT_H 0
1506 #define MICROMIPSOP_MASK_MTACC_T 0
1507 #define MICROMIPSOP_SH_MTACC_T 0
1508 #define MICROMIPSOP_MASK_MTACC_D 0
1509 #define MICROMIPSOP_SH_MTACC_D 0
1510 #define MICROMIPSOP_MASK_BBITIND 0
1511 #define MICROMIPSOP_SH_BBITIND 0
1512 #define MICROMIPSOP_MASK_CINSPOS 0
1513 #define MICROMIPSOP_SH_CINSPOS 0
1514 #define MICROMIPSOP_MASK_CINSLM1 0
1515 #define MICROMIPSOP_SH_CINSLM1 0
1516 #define MICROMIPSOP_MASK_SEQI 0
1517 #define MICROMIPSOP_SH_SEQI 0
1518 #define MICROMIPSOP_SH_OFFSET_A 0
1519 #define MICROMIPSOP_MASK_OFFSET_A 0
1520 #define MICROMIPSOP_SH_OFFSET_B 0
1521 #define MICROMIPSOP_MASK_OFFSET_B 0
1522 #define MICROMIPSOP_SH_OFFSET_C 0
1523 #define MICROMIPSOP_MASK_OFFSET_C 0
1524 #define MICROMIPSOP_SH_RZ 0
1525 #define MICROMIPSOP_MASK_RZ 0
1526 #define MICROMIPSOP_SH_FZ 0
1527 #define MICROMIPSOP_MASK_FZ 0
1529 /* These are the characters which may appears in the args field of a microMIPS
1530 instruction. They appear in the order in which the fields appear
1531 when the instruction is used. Commas and parentheses in the args
1532 string are ignored when assembling, and written into the output
1535 The followings are for 16-bit microMIPS instructions.
1538 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1539 The same register used as both source and target.
1540 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1541 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1542 The same register used as both source and target.
1543 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1544 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1545 "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
1546 "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
1547 ("mh" and "mi" form a valid 3-bit register pair)
1548 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1549 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1550 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1551 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1552 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1553 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1554 "mr" must be program counter
1556 "mt" must be the same as the previous register
1557 "mx" must be the same as the destination register
1561 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1562 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1563 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1564 32768, 65535) (MICROMIPSOP_*_IMMC)
1565 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1566 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1567 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
1568 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1569 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1570 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1571 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1572 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1573 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1574 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1575 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1576 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1577 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1578 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1579 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1580 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1583 In most cases 32-bit microMIPS instructions use the same characters
1584 as MIPS (with ADDIUPC being a notable exception, but there are some
1587 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1588 "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
1589 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1590 ">" shift amount between 32 and 63, stored after subtracting 32
1591 (MICROMIPSOP_*_SHAMT)
1592 "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1593 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1594 "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1595 "b" 5-bit base register (MICROMIPSOP_*_RS)
1596 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1597 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1598 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1599 "i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1600 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1601 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1602 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1603 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1604 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1605 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1606 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1607 "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1608 "t" 5-bit target register (MICROMIPSOP_*_RT)
1609 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1610 "v" 5-bit same register used as both source and destination
1612 "w" 5-bit same register used as both target and destination
1614 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1615 "z" must be zero register
1616 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1617 "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1618 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1620 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1621 LSB (MICROMIPSOP_*_EXTLSB).
1622 Enforces: 0 <= pos < 32.
1623 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1624 Requires that "+A" or "+E" occur first to set position.
1625 Enforces: 0 < (pos+size) <= 32.
1626 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1627 Requires that "+A" or "+E" occur first to set position.
1628 Enforces: 0 < (pos+size) <= 32.
1629 (Also used by DEXT w/ different limits, but limits for
1630 that are checked by the M_DEXT macro.)
1631 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1632 Enforces: 32 <= pos < 64.
1633 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1634 Requires that "+A" or "+E" occur first to set position.
1635 Enforces: 32 < (pos+size) <= 64.
1636 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1637 Requires that "+A" or "+E" occur first to set position.
1638 Enforces: 32 < (pos+size) <= 64.
1639 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1640 Requires that "+A" or "+E" occur first to set position.
1641 Enforces: 32 < (pos+size) <= 64.
1643 PC-relative addition (ADDIUPC) instruction:
1644 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1645 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1647 Floating point instructions:
1648 "D" 5-bit destination register (MICROMIPSOP_*_FD)
1649 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1650 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1651 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1652 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1653 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1654 "V" 5-bit same register used as floating source and destination or target
1657 Coprocessor instructions:
1658 "E" 5-bit target register (MICROMIPSOP_*_RT)
1659 "G" 5-bit destination register (MICROMIPSOP_*_RD)
1660 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1661 "+D" combined destination register ("G") and sel ("H") for CP0 ops,
1662 for pretty-printing in disassembly only
1665 "A" general 32 bit expression
1666 "I" 32-bit immediate (value placed in imm_expr).
1667 "+I" 32-bit immediate (value placed in imm2_expr).
1668 "F" 64-bit floating point constant in .rdata
1669 "L" 64-bit floating point constant in .lit8
1670 "f" 32-bit floating point constant
1671 "l" 32-bit floating point constant in .lit4
1674 "()" parens surrounding optional value
1675 "," separates operands
1676 "+" start of extension sequence
1677 "m" start of microMIPS extension sequence
1679 Characters used so far, for quick reference when adding more:
1682 "ABCDEFGHI KLMN RST V "
1683 "abcd f hijklmnopqrstuvw yz"
1685 Extension character sequences used so far ("+" followed by the
1686 following), for quick reference when adding more:
1692 Extension character sequences used so far ("m" followed by the
1693 following), for quick reference when adding more:
1696 " BCDEFGHIJ LMNOPQ U WXYZ"
1697 " bcdefghij lmn pq st xyz"
1700 extern const struct mips_opcode micromips_opcodes
[];
1701 extern const int bfd_micromips_num_opcodes
;
1703 /* A NOP insn impemented as "or at,at,zero".
1704 Used to implement -mfix-loongson2f. */
1705 #define LOONGSON2F_NOP_INSN 0x00200825
1707 #endif /* _MIPS_H_ */
projects / deliverable / binutils-gdb.git / blob