1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2008, 2009, 2010, 2013
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
8 This file is part of GDB, GAS, and the GNU binutils.
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version 3,
13 or (at your option) any later version.
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING3. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
30 /* These are bit masks and shift counts to use to access the various
31 fields of an instruction. To retrieve the X field of an
32 instruction, use the expression
33 (i >> OP_SH_X) & OP_MASK_X
34 To set the same field (to j), use
35 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
37 Make sure you use fields that are appropriate for the instruction,
40 The 'i' format uses OP, RS, RT and IMMEDIATE.
42 The 'j' format uses OP and TARGET.
44 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
46 The 'b' format uses OP, RS, RT and DELTA.
48 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
50 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
52 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
53 breakpoint instruction are not defined; Kane says the breakpoint
54 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
55 only use ten bits). An optional two-operand form of break/sdbbp
56 allows the lower ten bits to be set too, and MIPS32 and later
57 architectures allow 20 bits to be set with a signal operand
60 The syscall instruction uses CODE20.
62 The general coprocessor instructions use COPZ. */
64 #define OP_MASK_OP 0x3f
66 #define OP_MASK_RS 0x1f
68 #define OP_MASK_FR 0x1f
70 #define OP_MASK_FMT 0x1f
72 #define OP_MASK_BCC 0x7
74 #define OP_MASK_CODE 0x3ff
76 #define OP_MASK_CODE2 0x3ff
78 #define OP_MASK_RT 0x1f
80 #define OP_MASK_FT 0x1f
82 #define OP_MASK_CACHE 0x1f
83 #define OP_SH_CACHE 16
84 #define OP_MASK_RD 0x1f
86 #define OP_MASK_FS 0x1f
88 #define OP_MASK_PREFX 0x1f
89 #define OP_SH_PREFX 11
90 #define OP_MASK_CCC 0x7
92 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
93 #define OP_SH_CODE20 6
94 #define OP_MASK_SHAMT 0x1f
96 #define OP_MASK_EXTLSB OP_MASK_SHAMT
97 #define OP_SH_EXTLSB OP_SH_SHAMT
98 #define OP_MASK_STYPE OP_MASK_SHAMT
99 #define OP_SH_STYPE OP_SH_SHAMT
100 #define OP_MASK_FD 0x1f
102 #define OP_MASK_TARGET 0x3ffffff
103 #define OP_SH_TARGET 0
104 #define OP_MASK_COPZ 0x1ffffff
106 #define OP_MASK_IMMEDIATE 0xffff
107 #define OP_SH_IMMEDIATE 0
108 #define OP_MASK_DELTA 0xffff
109 #define OP_SH_DELTA 0
110 #define OP_MASK_FUNCT 0x3f
111 #define OP_SH_FUNCT 0
112 #define OP_MASK_SPEC 0x3f
114 #define OP_SH_LOCC 8 /* FP condition code. */
115 #define OP_SH_HICC 18 /* FP condition code. */
116 #define OP_MASK_CC 0x7
117 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
118 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
119 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
120 #define OP_MASK_COP1SPEC 0xf
121 #define OP_MASK_COP1SCLR 0x4
122 #define OP_MASK_COP1CMP 0x3
123 #define OP_SH_COP1CMP 4
124 #define OP_SH_FORMAT 21 /* FP short format field. */
125 #define OP_MASK_FORMAT 0x7
126 #define OP_SH_TRUE 16
127 #define OP_MASK_TRUE 0x1
129 #define OP_MASK_GE 0x01
130 #define OP_SH_UNSIGNED 16
131 #define OP_MASK_UNSIGNED 0x1
132 #define OP_SH_HINT 16
133 #define OP_MASK_HINT 0x1f
134 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
135 #define OP_MASK_MMI 0x3f
136 #define OP_SH_MMISUB 6
137 #define OP_MASK_MMISUB 0x1f
138 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
139 #define OP_SH_PERFREG 1
140 #define OP_SH_SEL 0 /* Coprocessor select field. */
141 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
142 #define OP_SH_CODE19 6 /* 19 bit wait code. */
143 #define OP_MASK_CODE19 0x7ffff
145 #define OP_MASK_ALN 0x7
146 #define OP_SH_VSEL 21
147 #define OP_MASK_VSEL 0x1f
148 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
149 but 0x8-0xf don't select bytes. */
150 #define OP_SH_VECBYTE 22
151 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
152 #define OP_SH_VECALIGN 21
153 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
154 #define OP_SH_INSMSB 11
155 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
156 #define OP_SH_EXTMSBD 11
159 #define OP_SH_DSPACC 11
160 #define OP_MASK_DSPACC 0x3
161 #define OP_SH_DSPACC_S 21
162 #define OP_MASK_DSPACC_S 0x3
163 #define OP_SH_DSPSFT 20
164 #define OP_MASK_DSPSFT 0x3f
165 #define OP_SH_DSPSFT_7 19
166 #define OP_MASK_DSPSFT_7 0x7f
168 #define OP_MASK_SA3 0x7
170 #define OP_MASK_SA4 0xf
171 #define OP_SH_IMM8 16
172 #define OP_MASK_IMM8 0xff
173 #define OP_SH_IMM10 16
174 #define OP_MASK_IMM10 0x3ff
175 #define OP_SH_WRDSP 11
176 #define OP_MASK_WRDSP 0x3f
177 #define OP_SH_RDDSP 16
178 #define OP_MASK_RDDSP 0x3f
180 #define OP_MASK_BP 0x3
184 #define OP_MASK_MT_U 0x1
186 #define OP_MASK_MT_H 0x1
187 #define OP_SH_MTACC_T 18
188 #define OP_MASK_MTACC_T 0x3
189 #define OP_SH_MTACC_D 13
190 #define OP_MASK_MTACC_D 0x3
193 #define OP_MASK_3BITPOS 0x7
194 #define OP_SH_3BITPOS 12
195 #define OP_MASK_OFFSET12 0xfff
196 #define OP_SH_OFFSET12 0
198 #define OP_OP_COP0 0x10
199 #define OP_OP_COP1 0x11
200 #define OP_OP_COP2 0x12
201 #define OP_OP_COP3 0x13
202 #define OP_OP_LWC1 0x31
203 #define OP_OP_LWC2 0x32
204 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
205 #define OP_OP_LDC1 0x35
206 #define OP_OP_LDC2 0x36
207 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
208 #define OP_OP_SWC1 0x39
209 #define OP_OP_SWC2 0x3a
210 #define OP_OP_SWC3 0x3b
211 #define OP_OP_SDC1 0x3d
212 #define OP_OP_SDC2 0x3e
213 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
216 #define OP_MASK_CODE10 0x3ff
217 #define OP_SH_CODE10 11
219 /* Values in the 'VSEL' field. */
220 #define MDMX_FMTSEL_IMM_QH 0x1d
221 #define MDMX_FMTSEL_IMM_OB 0x1e
222 #define MDMX_FMTSEL_VEC_QH 0x15
223 #define MDMX_FMTSEL_VEC_OB 0x16
227 #define OP_MASK_UDI1 0x1f
229 #define OP_MASK_UDI2 0x3ff
231 #define OP_MASK_UDI3 0x7fff
233 #define OP_MASK_UDI4 0xfffff
236 #define OP_SH_BBITIND 16
237 #define OP_MASK_BBITIND 0x1f
238 #define OP_SH_CINSPOS 6
239 #define OP_MASK_CINSPOS 0x1f
240 #define OP_SH_CINSLM1 11
241 #define OP_MASK_CINSLM1 0x1f
243 #define OP_MASK_SEQI 0x3ff
246 #define OP_SH_OFFSET_A 6
247 #define OP_MASK_OFFSET_A 0xff
248 #define OP_SH_OFFSET_B 3
249 #define OP_MASK_OFFSET_B 0xff
250 #define OP_SH_OFFSET_C 6
251 #define OP_MASK_OFFSET_C 0x1ff
253 #define OP_MASK_RZ 0x1f
255 #define OP_MASK_FZ 0x1f
257 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
258 definition, and vice versa. This simplifies various parts
259 of the operand handling in GAS. The fields below only exist
260 in the microMIPS encoding, so define each one to have an empty
262 #define OP_MASK_TRAP 0
264 #define OP_MASK_OFFSET10 0
265 #define OP_SH_OFFSET10 0
266 #define OP_MASK_RS3 0
294 #define OP_MASK_IMMA 0
296 #define OP_MASK_IMMB 0
298 #define OP_MASK_IMMC 0
300 #define OP_MASK_IMMF 0
302 #define OP_MASK_IMMG 0
304 #define OP_MASK_IMMH 0
306 #define OP_MASK_IMMI 0
308 #define OP_MASK_IMMJ 0
310 #define OP_MASK_IMML 0
312 #define OP_MASK_IMMM 0
314 #define OP_MASK_IMMN 0
316 #define OP_MASK_IMMO 0
318 #define OP_MASK_IMMP 0
320 #define OP_MASK_IMMQ 0
322 #define OP_MASK_IMMU 0
324 #define OP_MASK_IMMW 0
326 #define OP_MASK_IMMX 0
328 #define OP_MASK_IMMY 0
331 /* Enhanced VA Scheme */
332 #define OP_SH_EVAOFFSET 7
333 #define OP_MASK_EVAOFFSET 0x1ff
335 /* Enumerates the various types of MIPS operand. */
336 enum mips_operand_type
{
337 /* Described by mips_int_operand. */
340 /* Described by mips_mapped_int_operand. */
343 /* Described by mips_msb_operand. */
346 /* Described by mips_reg_operand. */
349 /* Described by mips_reg_pair_operand. */
352 /* Described by mips_pcrel_operand. */
355 /* A performance register. The field is 5 bits in size, but the supported
356 values are much more restricted. */
359 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
360 as a normal 9-bit signed offset that is multiplied by four, but there
361 are four special cases:
369 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
370 5-bit register fields, both of which must be set to the destination
374 /* A register list for a microMIPS LWM or SWM instruction. The operand
375 size determines whether the 16-bit or 32-bit encoding is required. */
378 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */
381 /* The register list and frame size for a MIPS16 SAVE or RESTORE
383 OP_SAVE_RESTORE_LIST
,
385 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
389 0EEE0 8 copies of $vN[E], OB format
390 0EE01 4 copies of $vN[E], QH format
391 10110 all 8 elements of $vN, OB format
392 10101 all 4 elements of $vN, QH format
393 11110 8 copies of immediate N, OB format
394 11101 4 copies of immediate N, QH format. */
397 /* A register operand that must match the destination register. */
400 /* A register operand that must match the previous register. */
403 /* $pc, which has no encoding in the architectural instruction. */
407 /* Enumerates the types of MIPS register. */
408 enum mips_reg_operand_type
{
409 /* General registers $0-$31. Software names like $at can also be used. */
412 /* Floating-point registers $f0-$f31. */
415 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
416 can also be written $fcc0-$fcc7. */
419 /* FPRs used in a vector capacity. They can be written $f0-$f31
420 or $v0-$v31, although the latter form is not used for the VR5400
421 vector instructions. */
424 /* DSP accumulator registers $ac0-$ac3. */
427 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
428 also be used in some contexts. */
431 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
432 also be used in some contexts. */
436 /* Base class for all operands. */
439 /* The type of the operand. */
440 enum mips_operand_type type
;
442 /* The operand occupies SIZE bits of the instruction, starting at LSB. */
447 /* Describes an integer operand with a regular encoding pattern. */
448 struct mips_int_operand
450 struct mips_operand root
;
452 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
453 The cyclically previous field value encodes 1 << SHIFT less than that,
456 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
459 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
460 shifted left two places.
462 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
465 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
466 unsigned int max_val
;
470 /* True if the operand should be printed as hex rather than decimal. */
471 bfd_boolean print_hex
;
474 /* Uses a lookup table to describe a small integer operand. */
475 struct mips_mapped_int_operand
477 struct mips_operand root
;
479 /* Maps each encoding value to the integer that it represents. */
482 /* True if the operand should be printed as hex rather than decimal. */
483 bfd_boolean print_hex
;
486 /* An operand that encodes the most significant bit position of a bitfield.
487 Given a bitfield that spans bits [MSB, LSB], some operands of this type
488 encode MSB directly while others encode MSB - LSB. Each operand of this
489 type is preceded by an integer operand that specifies LSB.
491 The assembly form varies between instructions. For some instructions,
492 such as EXT, the operand is written as the bitfield size. For others,
493 such as EXTS, it is written in raw MSB - LSB form. */
494 struct mips_msb_operand
496 struct mips_operand root
;
498 /* The assembly-level operand encoded by a field value of 0. */
501 /* True if the operand encodes MSB directly, false if it encodes
505 /* The maximum value of MSB + 1. */
509 /* Describes a single register operand. */
510 struct mips_reg_operand
512 struct mips_operand root
;
514 /* The type of register. */
515 enum mips_reg_operand_type reg_type
;
517 /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
518 otherwise the encoding is the same as the register number. */
519 const unsigned char *reg_map
;
522 /* Describes an operand that encodes a pair of registers. */
523 struct mips_reg_pair_operand
525 struct mips_operand root
;
527 /* The type of register. */
528 enum mips_reg_operand_type reg_type
;
530 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
531 unsigned char *reg1_map
;
532 unsigned char *reg2_map
;
535 /* Describes an operand that is calculated relative to a base PC.
536 The base PC is usually the address of the following instruction,
537 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
538 struct mips_pcrel_operand
540 /* Encodes the offset. */
541 struct mips_int_operand root
;
543 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
544 which is then added to the offset encoded by ROOT. */
545 unsigned int align_log2
: 8;
547 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
548 reinstated. This is true for jumps and branches and false for
549 PC-relative data instructions. */
550 unsigned int include_isa_bit
: 1;
552 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
553 This is true for JALX and false otherwise. */
554 unsigned int flip_isa_bit
: 1;
557 /* Return a version of INSN in which the field specified by OPERAND
560 static inline unsigned int
561 mips_insert_operand (const struct mips_operand
*operand
, unsigned int insn
,
566 mask
= (1 << operand
->size
) - 1;
567 insn
&= ~(mask
<< operand
->lsb
);
568 insn
|= (uval
& mask
) << operand
->lsb
;
572 /* Extract OPERAND from instruction INSN. */
574 static inline unsigned int
575 mips_extract_operand (const struct mips_operand
*operand
, unsigned int insn
)
577 return (insn
>> operand
->lsb
) & ((1 << operand
->size
) - 1);
580 /* UVAL is the value encoded by OPERAND. Return it in signed form. */
583 mips_signed_operand (const struct mips_operand
*operand
, unsigned int uval
)
585 unsigned int sign_bit
, mask
;
587 mask
= (1 << operand
->size
) - 1;
588 sign_bit
= 1 << (operand
->size
- 1);
589 return ((uval
+ sign_bit
) & mask
) - sign_bit
;
592 /* Return the integer that OPERAND encodes as UVAL. */
595 mips_decode_int_operand (const struct mips_int_operand
*operand
,
598 uval
|= (operand
->max_val
- uval
) & -(1 << operand
->root
.size
);
599 uval
+= operand
->bias
;
600 uval
<<= operand
->shift
;
604 /* Return the maximum value that can be encoded by OPERAND. */
607 mips_int_operand_max (const struct mips_int_operand
*operand
)
609 return (operand
->max_val
+ operand
->bias
) << operand
->shift
;
612 /* Return the minimum value that can be encoded by OPERAND. */
615 mips_int_operand_min (const struct mips_int_operand
*operand
)
619 mask
= (1 << operand
->root
.size
) - 1;
620 return mips_int_operand_max (operand
) - (mask
<< operand
->shift
);
623 /* Return the register that OPERAND encodes as UVAL. */
626 mips_decode_reg_operand (const struct mips_reg_operand
*operand
,
629 if (operand
->reg_map
)
630 uval
= operand
->reg_map
[uval
];
634 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
635 Return the address that it encodes. */
637 static inline bfd_vma
638 mips_decode_pcrel_operand (const struct mips_pcrel_operand
*operand
,
639 bfd_vma base_pc
, unsigned int uval
)
643 addr
= base_pc
& -(1 << operand
->align_log2
);
644 addr
+= mips_decode_int_operand (&operand
->root
, uval
);
645 if (operand
->include_isa_bit
)
647 if (operand
->flip_isa_bit
)
652 /* This structure holds information for a particular instruction. */
656 /* The name of the instruction. */
658 /* A string describing the arguments for this instruction. */
660 /* The basic opcode for the instruction. When assembling, this
661 opcode is modified by the arguments to produce the actual opcode
662 that is used. If pinfo is INSN_MACRO, then this is 0. */
664 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
665 relevant portions of the opcode when disassembling. If the
666 actual opcode anded with the match field equals the opcode field,
667 then we have found the correct instruction. If pinfo is
668 INSN_MACRO, then this field is the macro identifier. */
670 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
671 of bits describing the instruction, notably any relevant hazard
674 /* A collection of additional bits describing the instruction. */
675 unsigned long pinfo2
;
676 /* A collection of bits describing the instruction sets of which this
677 instruction or macro is a member. */
678 unsigned long membership
;
679 /* A collection of bits describing the ASE of which this instruction
680 or macro is a member. */
682 /* A collection of bits describing the instruction sets of which this
683 instruction or macro is not a member. */
684 unsigned long exclusions
;
687 /* These are the characters which may appear in the args field of an
688 instruction. They appear in the order in which the fields appear
689 when the instruction is used. Commas and parentheses in the args
690 string are ignored when assembling, and written into the output
693 Each of these characters corresponds to a mask field defined above.
695 "1" 5 bit sync type (OP_*_STYPE)
696 "<" 5 bit shift amount (OP_*_SHAMT)
697 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
698 "a" 26 bit target address (OP_*_TARGET)
699 "+i" likewise, but flips bit 0
700 "b" 5 bit base register (OP_*_RS)
701 "c" 10 bit breakpoint code (OP_*_CODE)
702 "d" 5 bit destination register specifier (OP_*_RD)
703 "h" 5 bit prefx hint (OP_*_PREFX)
704 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
705 "j" 16 bit signed immediate (OP_*_DELTA)
706 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
707 "o" 16 bit signed offset (OP_*_DELTA)
708 "p" 16 bit PC relative branch target address (OP_*_DELTA)
709 "q" 10 bit extra breakpoint code (OP_*_CODE2)
710 "r" 5 bit same register used as both source and target (OP_*_RS)
711 "s" 5 bit source register specifier (OP_*_RS)
712 "t" 5 bit target register (OP_*_RT)
713 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
714 "v" 5 bit same register used as both source and destination (OP_*_RS)
715 "w" 5 bit same register used as both target and destination (OP_*_RT)
716 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
717 (used by clo and clz)
718 "C" 25 bit coprocessor function code (OP_*_COPZ)
719 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
720 "J" 19 bit wait function code (OP_*_CODE19)
721 "x" accept and ignore register name
722 "z" must be zero register
723 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
724 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
725 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
726 microMIPS compatibility).
727 Enforces: 0 <= pos < 32.
728 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
729 Requires that "+A" or "+E" occur first to set position.
730 Enforces: 0 < (pos+size) <= 32.
731 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
732 Requires that "+A" or "+E" occur first to set position.
733 Enforces: 0 < (pos+size) <= 32.
734 (Also used by "dext" w/ different limits, but limits for
735 that are checked by the M_DEXT macro.)
736 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
737 Enforces: 32 <= pos < 64.
738 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
739 Requires that "+A" or "+E" occur first to set position.
740 Enforces: 32 < (pos+size) <= 64.
741 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
742 Requires that "+A" or "+E" occur first to set position.
743 Enforces: 32 < (pos+size) <= 64.
744 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
745 Requires that "+A" or "+E" occur first to set position.
746 Enforces: 32 < (pos+size) <= 64.
748 Floating point instructions:
749 "D" 5 bit destination register (OP_*_FD)
750 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
751 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
752 "S" 5 bit fs source 1 register (OP_*_FS)
753 "T" 5 bit ft source 2 register (OP_*_FT)
754 "R" 5 bit fr source 3 register (OP_*_FR)
755 "V" 5 bit same register used as floating source and destination (OP_*_FS)
756 "W" 5 bit same register used as floating target and destination (OP_*_FT)
758 Coprocessor instructions:
759 "E" 5 bit target register (OP_*_RT)
760 "G" 5 bit destination register (OP_*_RD)
761 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
762 "P" 5 bit performance-monitor register (OP_*_PERFREG)
763 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
764 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
767 "A" General 32 bit expression
768 "I" 32 bit immediate (value placed in imm_expr).
769 "+I" 32 bit immediate (value placed in imm2_expr).
770 "F" 64 bit floating point constant in .rdata
771 "L" 64 bit floating point constant in .lit8
772 "f" 32 bit floating point constant
773 "l" 32 bit floating point constant in .lit4
775 MDMX and VR5400 instruction operands (note that while these use the
776 FP register fields, the MDMX instructions accept both $fN and $vN names
778 "O" alignment offset (OP_*_ALN)
779 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
780 "X" destination register (OP_*_FD)
781 "Y" source register (OP_*_FS)
782 "Z" source register (OP_*_FT)
785 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
786 "3" 3 bit unsigned immediate (OP_*_SA3)
787 "4" 4 bit unsigned immediate (OP_*_SA4)
788 "5" 8 bit unsigned immediate (OP_*_IMM8)
789 "6" 5 bit unsigned immediate (OP_*_RS)
790 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
791 "8" 6 bit unsigned immediate (OP_*_WRDSP)
792 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
793 "0" 6 bit signed immediate (OP_*_DSPSFT)
794 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
795 "'" 6 bit unsigned immediate (OP_*_RDDSP)
796 "@" 10 bit signed immediate (OP_*_IMM10)
799 "!" 1 bit usermode flag (OP_*_MT_U)
800 "$" 1 bit load high flag (OP_*_MT_H)
801 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
802 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
803 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
804 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
807 "~" 12 bit offset (OP_*_OFFSET12)
808 "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
811 "+J" 10-bit hypcall code (OP_*CODE10)
814 "+1" UDI immediate bits 6-10
815 "+2" UDI immediate bits 6-15
816 "+3" UDI immediate bits 6-20
817 "+4" UDI immediate bits 6-25
820 "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
821 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
822 otherwise skips to next candidate.
823 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
824 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
825 32 <= pos < 64, otherwise skips to next candidate.
826 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
827 "+s" Length-minus-one field of cins32/exts32. Requires msb position
828 of the field to be <= 31.
829 "+S" Length-minus-one field of cins/exts. Requires msb position
830 of the field to be <= 63.
833 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
834 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
835 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
836 "+z" 5-bit rz register (OP_*_RZ)
837 "+Z" 5-bit fz register (OP_*_FZ)
840 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
843 "()" parens surrounding optional value
844 "," separates operands
845 "+" Start of extension sequence.
847 Characters used so far, for quick reference when adding more:
850 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
851 "abcdefghijklopqrstuvwxz"
853 Extension character sequences used so far ("+" followed by the
854 following), for quick reference when adding more:
860 /* These are the bits which may be set in the pinfo field of an
861 instructions, if it is not equal to INSN_MACRO. */
863 /* Writes to operand number N. */
864 #define INSN_WRITE_SHIFT 0
865 #define INSN_WRITE_1 0x00000001
866 #define INSN_WRITE_2 0x00000002
867 #define INSN_WRITE_ALL 0x00000003
868 /* Reads from operand number N. */
869 #define INSN_READ_SHIFT 2
870 #define INSN_READ_1 0x00000004
871 #define INSN_READ_2 0x00000008
872 #define INSN_READ_3 0x00000010
873 #define INSN_READ_4 0x00000020
874 #define INSN_READ_ALL 0x0000003c
875 /* Modifies general purpose register 31. */
876 #define INSN_WRITE_GPR_31 0x00000040
877 /* Modifies coprocessor condition code. */
878 #define INSN_WRITE_COND_CODE 0x00000080
879 /* Reads coprocessor condition code. */
880 #define INSN_READ_COND_CODE 0x00000100
882 #define INSN_TLB 0x00000200
883 /* Reads coprocessor register other than floating point register. */
884 #define INSN_COP 0x00000400
885 /* Instruction loads value from memory, requiring delay. */
886 #define INSN_LOAD_MEMORY_DELAY 0x00000800
887 /* Instruction loads value from coprocessor, requiring delay. */
888 #define INSN_LOAD_COPROC_DELAY 0x00001000
889 /* Instruction has unconditional branch delay slot. */
890 #define INSN_UNCOND_BRANCH_DELAY 0x00002000
891 /* Instruction has conditional branch delay slot. */
892 #define INSN_COND_BRANCH_DELAY 0x00004000
893 /* Conditional branch likely: if branch not taken, insn nullified. */
894 #define INSN_COND_BRANCH_LIKELY 0x00008000
895 /* Moves to coprocessor register, requiring delay. */
896 #define INSN_COPROC_MOVE_DELAY 0x00010000
897 /* Loads coprocessor register from memory, requiring delay. */
898 #define INSN_COPROC_MEMORY_DELAY 0x00020000
899 /* Reads the HI register. */
900 #define INSN_READ_HI 0x00040000
901 /* Reads the LO register. */
902 #define INSN_READ_LO 0x00080000
903 /* Modifies the HI register. */
904 #define INSN_WRITE_HI 0x00100000
905 /* Modifies the LO register. */
906 #define INSN_WRITE_LO 0x00200000
907 /* Not to be placed in a branch delay slot, either architecturally
908 or for ease of handling (such as with instructions that take a trap). */
909 #define INSN_NO_DELAY_SLOT 0x00400000
910 /* Instruction stores value into memory. */
911 #define INSN_STORE_MEMORY 0x00800000
912 /* Instruction uses single precision floating point. */
913 #define FP_S 0x01000000
914 /* Instruction uses double precision floating point. */
915 #define FP_D 0x02000000
916 /* Instruction is part of the tx39's integer multiply family. */
917 #define INSN_MULT 0x04000000
918 /* Reads general purpose register 24. */
919 #define INSN_READ_GPR_24 0x08000000
920 /* Writes to general purpose register 24. */
921 #define INSN_WRITE_GPR_24 0x10000000
922 /* A user-defined instruction. */
923 #define INSN_UDI 0x20000000
924 /* Instruction is actually a macro. It should be ignored by the
925 disassembler, and requires special treatment by the assembler. */
926 #define INSN_MACRO 0xffffffff
928 /* These are the bits which may be set in the pinfo2 field of an
931 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
932 #define INSN2_ALIAS 0x00000001
933 /* Instruction reads MDMX accumulator. */
934 #define INSN2_READ_MDMX_ACC 0x00000002
935 /* Instruction writes MDMX accumulator. */
936 #define INSN2_WRITE_MDMX_ACC 0x00000004
937 /* Macro uses single-precision floating-point instructions. This should
938 only be set for macros. For instructions, FP_S in pinfo carries the
940 #define INSN2_M_FP_S 0x00000008
941 /* Macro uses double-precision floating-point instructions. This should
942 only be set for macros. For instructions, FP_D in pinfo carries the
944 #define INSN2_M_FP_D 0x00000010
945 /* Instruction has a branch delay slot that requires a 16-bit instruction. */
946 #define INSN2_BRANCH_DELAY_16BIT 0x00000020
947 /* Instruction has a branch delay slot that requires a 32-bit instruction. */
948 #define INSN2_BRANCH_DELAY_32BIT 0x00000040
949 /* Writes to the stack pointer ($29). */
950 #define INSN2_WRITE_SP 0x00000080
951 /* Reads from the stack pointer ($29). */
952 #define INSN2_READ_SP 0x00000100
953 /* Reads the RA ($31) register. */
954 #define INSN2_READ_GPR_31 0x00000200
955 /* Reads the program counter ($pc). */
956 #define INSN2_READ_PC 0x00000400
957 /* Is an unconditional branch insn. */
958 #define INSN2_UNCOND_BRANCH 0x00000800
959 /* Is a conditional branch insn. */
960 #define INSN2_COND_BRANCH 0x00001000
961 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */
962 #define INSN2_READ_GPR_16 0x00002000
964 /* Masks used to mark instructions to indicate which MIPS ISA level
965 they were introduced in. INSN_ISA_MASK masks an enumeration that
966 specifies the base ISA level(s). The remainder of a 32-bit
967 word constructed using these macros is a bitmask of the remaining
968 INSN_* values below. */
970 #define INSN_ISA_MASK 0x0000000ful
972 /* We cannot start at zero due to ISA_UNKNOWN below. */
979 #define INSN_ISA32R2 7
981 #define INSN_ISA64R2 9
982 /* Below this point the INSN_* values correspond to combinations of ISAs.
983 They are only for use in the opcodes table to indicate membership of
984 a combination of ISAs that cannot be expressed using the usual inclusion
985 ordering on the above INSN_* values. */
986 #define INSN_ISA3_32 10
987 #define INSN_ISA3_32R2 11
988 #define INSN_ISA4_32 12
989 #define INSN_ISA4_32R2 13
990 #define INSN_ISA5_32R2 14
992 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
993 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
994 this table describes whether at least one of the ISAs described by X
995 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
996 a particular core and X as the ISA level(s) at which a certain instruction
997 is defined.) The ISA(s) described by X is/are implemented by Y iff
998 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
1000 static const unsigned int mips_isa_table
[] =
1001 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
1003 /* Masks used for Chip specific instructions. */
1004 #define INSN_CHIP_MASK 0xc3ff0f20
1006 /* Cavium Networks Octeon instructions. */
1007 #define INSN_OCTEON 0x00000800
1008 #define INSN_OCTEONP 0x00000200
1009 #define INSN_OCTEON2 0x00000100
1011 /* MIPS R5900 instruction */
1012 #define INSN_5900 0x00004000
1014 /* MIPS R4650 instruction. */
1015 #define INSN_4650 0x00010000
1016 /* LSI R4010 instruction. */
1017 #define INSN_4010 0x00020000
1018 /* NEC VR4100 instruction. */
1019 #define INSN_4100 0x00040000
1020 /* Toshiba R3900 instruction. */
1021 #define INSN_3900 0x00080000
1022 /* MIPS R10000 instruction. */
1023 #define INSN_10000 0x00100000
1024 /* Broadcom SB-1 instruction. */
1025 #define INSN_SB1 0x00200000
1026 /* NEC VR4111/VR4181 instruction. */
1027 #define INSN_4111 0x00400000
1028 /* NEC VR4120 instruction. */
1029 #define INSN_4120 0x00800000
1030 /* NEC VR5400 instruction. */
1031 #define INSN_5400 0x01000000
1032 /* NEC VR5500 instruction. */
1033 #define INSN_5500 0x02000000
1035 /* ST Microelectronics Loongson 2E. */
1036 #define INSN_LOONGSON_2E 0x40000000
1037 /* ST Microelectronics Loongson 2F. */
1038 #define INSN_LOONGSON_2F 0x80000000
1040 #define INSN_LOONGSON_3A 0x00000400
1041 /* RMI Xlr instruction */
1042 #define INSN_XLR 0x00000020
1045 #define ASE_DSP 0x00000001
1046 #define ASE_DSP64 0x00000002
1048 #define ASE_DSPR2 0x00000004
1049 /* Enhanced VA Scheme */
1050 #define ASE_EVA 0x00000008
1051 /* MCU (MicroController) ASE */
1052 #define ASE_MCU 0x00000010
1054 #define ASE_MDMX 0x00000020
1056 #define ASE_MIPS3D 0x00000040
1058 #define ASE_MT 0x00000080
1060 #define ASE_SMARTMIPS 0x00000100
1061 /* Virtualization ASE */
1062 #define ASE_VIRT 0x00000200
1063 #define ASE_VIRT64 0x00000400
1065 /* MIPS ISA defines, use instead of hardcoding ISA level. */
1067 #define ISA_UNKNOWN 0 /* Gas internal use. */
1068 #define ISA_MIPS1 INSN_ISA1
1069 #define ISA_MIPS2 INSN_ISA2
1070 #define ISA_MIPS3 INSN_ISA3
1071 #define ISA_MIPS4 INSN_ISA4
1072 #define ISA_MIPS5 INSN_ISA5
1074 #define ISA_MIPS32 INSN_ISA32
1075 #define ISA_MIPS64 INSN_ISA64
1077 #define ISA_MIPS32R2 INSN_ISA32R2
1078 #define ISA_MIPS64R2 INSN_ISA64R2
1081 /* CPU defines, use instead of hardcoding processor number. Keep this
1082 in sync with bfd/archures.c in order for machine selection to work. */
1083 #define CPU_UNKNOWN 0 /* Gas internal use. */
1084 #define CPU_R3000 3000
1085 #define CPU_R3900 3900
1086 #define CPU_R4000 4000
1087 #define CPU_R4010 4010
1088 #define CPU_VR4100 4100
1089 #define CPU_R4111 4111
1090 #define CPU_VR4120 4120
1091 #define CPU_R4300 4300
1092 #define CPU_R4400 4400
1093 #define CPU_R4600 4600
1094 #define CPU_R4650 4650
1095 #define CPU_R5000 5000
1096 #define CPU_VR5400 5400
1097 #define CPU_VR5500 5500
1098 #define CPU_R5900 5900
1099 #define CPU_R6000 6000
1100 #define CPU_RM7000 7000
1101 #define CPU_R8000 8000
1102 #define CPU_RM9000 9000
1103 #define CPU_R10000 10000
1104 #define CPU_R12000 12000
1105 #define CPU_R14000 14000
1106 #define CPU_R16000 16000
1107 #define CPU_MIPS16 16
1108 #define CPU_MIPS32 32
1109 #define CPU_MIPS32R2 33
1111 #define CPU_MIPS64 64
1112 #define CPU_MIPS64R2 65
1113 #define CPU_SB1 12310201 /* octal 'SB', 01. */
1114 #define CPU_LOONGSON_2E 3001
1115 #define CPU_LOONGSON_2F 3002
1116 #define CPU_LOONGSON_3A 3003
1117 #define CPU_OCTEON 6501
1118 #define CPU_OCTEONP 6601
1119 #define CPU_OCTEON2 6502
1120 #define CPU_XLR 887682 /* decimal 'XLR' */
1122 /* Return true if the given CPU is included in INSN_* mask MASK. */
1124 static inline bfd_boolean
1125 cpu_is_member (int cpu
, unsigned int mask
)
1132 return (mask
& INSN_4650
) != 0;
1135 return (mask
& INSN_4010
) != 0;
1138 return (mask
& INSN_4100
) != 0;
1141 return (mask
& INSN_3900
) != 0;
1147 return (mask
& INSN_10000
) != 0;
1150 return (mask
& INSN_SB1
) != 0;
1153 return (mask
& INSN_4111
) != 0;
1156 return (mask
& INSN_4120
) != 0;
1159 return (mask
& INSN_5400
) != 0;
1162 return (mask
& INSN_5500
) != 0;
1165 return (mask
& INSN_5900
) != 0;
1167 case CPU_LOONGSON_2E
:
1168 return (mask
& INSN_LOONGSON_2E
) != 0;
1170 case CPU_LOONGSON_2F
:
1171 return (mask
& INSN_LOONGSON_2F
) != 0;
1173 case CPU_LOONGSON_3A
:
1174 return (mask
& INSN_LOONGSON_3A
) != 0;
1177 return (mask
& INSN_OCTEON
) != 0;
1180 return (mask
& INSN_OCTEONP
) != 0;
1183 return (mask
& INSN_OCTEON2
) != 0;
1186 return (mask
& INSN_XLR
) != 0;
1193 /* Test for membership in an ISA including chip specific ISAs. INSN
1194 is pointer to an element of the opcode table; ISA is the specified
1195 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
1196 test, or zero if no CPU specific ISA test is desired. Return true
1197 if instruction INSN is available to the given ISA and CPU. */
1199 static inline bfd_boolean
1200 opcode_is_member (const struct mips_opcode
*insn
, int isa
, int ase
, int cpu
)
1202 if (!cpu_is_member (cpu
, insn
->exclusions
))
1204 /* Test for ISA level compatibility. */
1205 if ((isa
& INSN_ISA_MASK
) != 0
1206 && (insn
->membership
& INSN_ISA_MASK
) != 0
1207 && ((mips_isa_table
[(isa
& INSN_ISA_MASK
) - 1]
1208 >> ((insn
->membership
& INSN_ISA_MASK
) - 1)) & 1) != 0)
1211 /* Test for ASE compatibility. */
1212 if ((ase
& insn
->ase
) != 0)
1215 /* Test for processor-specific extensions. */
1216 if (cpu_is_member (cpu
, insn
->membership
))
1222 /* This is a list of macro expanded instructions.
1224 _I appended means immediate
1225 _A appended means target address of a jump
1226 _AB appended means address with (possibly zero) base register
1227 _D appended means 64 bit floating point constant
1228 _S appended means 32 bit floating point constant. */
1483 /* The order of overloaded instructions matters. Label arguments and
1484 register arguments look the same. Instructions that can have either
1485 for arguments must apear in the correct order in this table for the
1486 assembler to pick the right one. In other words, entries with
1487 immediate operands must apear after the same instruction with
1490 Many instructions are short hand for other instructions (i.e., The
1491 jal <register> instruction is short for jalr <register>). */
1493 extern const struct mips_operand
*decode_mips_operand (const char *);
1494 extern const struct mips_opcode mips_builtin_opcodes
[];
1495 extern const int bfd_mips_num_builtin_opcodes
;
1496 extern struct mips_opcode
*mips_opcodes
;
1497 extern int bfd_mips_num_opcodes
;
1498 #define NUMOPCODES bfd_mips_num_opcodes
1501 /* The rest of this file adds definitions for the mips16 TinyRISC
1504 /* These are the bitmasks and shift counts used for the different
1505 fields in the instruction formats. Other than OP, no masks are
1506 provided for the fixed portions of an instruction, since they are
1509 The I format uses IMM11.
1511 The RI format uses RX and IMM8.
1513 The RR format uses RX, and RY.
1515 The RRI format uses RX, RY, and IMM5.
1517 The RRR format uses RX, RY, and RZ.
1519 The RRI_A format uses RX, RY, and IMM4.
1521 The SHIFT format uses RX, RY, and SHAMT.
1523 The I8 format uses IMM8.
1525 The I8_MOVR32 format uses RY and REGR32.
1527 The IR_MOV32R format uses REG32R and MOV32Z.
1529 The I64 format uses IMM8.
1531 The RI64 format uses RY and IMM5.
1534 #define MIPS16OP_MASK_OP 0x1f
1535 #define MIPS16OP_SH_OP 11
1536 #define MIPS16OP_MASK_IMM11 0x7ff
1537 #define MIPS16OP_SH_IMM11 0
1538 #define MIPS16OP_MASK_RX 0x7
1539 #define MIPS16OP_SH_RX 8
1540 #define MIPS16OP_MASK_IMM8 0xff
1541 #define MIPS16OP_SH_IMM8 0
1542 #define MIPS16OP_MASK_RY 0x7
1543 #define MIPS16OP_SH_RY 5
1544 #define MIPS16OP_MASK_IMM5 0x1f
1545 #define MIPS16OP_SH_IMM5 0
1546 #define MIPS16OP_MASK_RZ 0x7
1547 #define MIPS16OP_SH_RZ 2
1548 #define MIPS16OP_MASK_IMM4 0xf
1549 #define MIPS16OP_SH_IMM4 0
1550 #define MIPS16OP_MASK_REGR32 0x1f
1551 #define MIPS16OP_SH_REGR32 0
1552 #define MIPS16OP_MASK_REG32R 0x1f
1553 #define MIPS16OP_SH_REG32R 3
1554 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1555 #define MIPS16OP_MASK_MOVE32Z 0x7
1556 #define MIPS16OP_SH_MOVE32Z 0
1557 #define MIPS16OP_MASK_IMM6 0x3f
1558 #define MIPS16OP_SH_IMM6 5
1560 /* These are the characters which may appears in the args field of a MIPS16
1561 instruction. They appear in the order in which the fields appear when the
1562 instruction is used. Commas and parentheses in the args string are ignored
1563 when assembling, and written into the output when disassembling.
1565 "y" 3 bit register (MIPS16OP_*_RY)
1566 "x" 3 bit register (MIPS16OP_*_RX)
1567 "z" 3 bit register (MIPS16OP_*_RZ)
1568 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1569 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1570 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1571 "0" zero register ($0)
1572 "S" stack pointer ($sp or $29)
1574 "R" return address register ($ra or $31)
1575 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1576 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1577 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1578 "a" 26 bit jump address
1579 "i" likewise, but flips bit 0
1580 "e" 11 bit extension value
1581 "l" register list for entry instruction
1582 "L" register list for exit instruction
1584 "I" an immediate value used for macros
1586 The remaining codes may be extended. Except as otherwise noted,
1587 the full extended operand is a 16 bit signed value.
1588 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1589 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1590 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1591 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1592 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1593 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1594 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1595 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1596 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1597 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1598 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1599 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1600 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1601 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1602 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1603 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1604 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1605 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1606 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1607 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1608 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1609 "m" 7 bit register list for save instruction (18 bit extended)
1610 "M" 7 bit register list for restore instruction (18 bit extended)
1613 /* Save/restore encoding for the args field when all 4 registers are
1614 either saved as arguments or saved/restored as statics. */
1615 #define MIPS16_ALL_ARGS 0xe
1616 #define MIPS16_ALL_STATICS 0xb
1618 /* The following flags have the same value for the mips16 opcode
1623 INSN_UNCOND_BRANCH_DELAY
1624 INSN_COND_BRANCH_DELAY
1625 INSN_COND_BRANCH_LIKELY (never used)
1634 extern const struct mips_operand
*decode_mips16_operand (char, bfd_boolean
);
1635 extern const struct mips_opcode mips16_opcodes
[];
1636 extern const int bfd_mips16_num_opcodes
;
1638 /* These are the bit masks and shift counts used for the different fields
1639 in the microMIPS instruction formats. No masks are provided for the
1640 fixed portions of an instruction, since they are not needed. */
1642 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff
1643 #define MICROMIPSOP_SH_IMMEDIATE 0
1644 #define MICROMIPSOP_MASK_DELTA 0xffff
1645 #define MICROMIPSOP_SH_DELTA 0
1646 #define MICROMIPSOP_MASK_CODE10 0x3ff
1647 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
1648 #define MICROMIPSOP_MASK_TRAP 0xf
1649 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
1650 #define MICROMIPSOP_MASK_SHAMT 0x1f
1651 #define MICROMIPSOP_SH_SHAMT 11
1652 #define MICROMIPSOP_MASK_TARGET 0x3ffffff
1653 #define MICROMIPSOP_SH_TARGET 0
1654 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
1655 #define MICROMIPSOP_SH_EXTLSB 6
1656 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
1657 #define MICROMIPSOP_SH_EXTMSBD 11
1658 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
1659 #define MICROMIPSOP_SH_INSMSB 11
1660 #define MICROMIPSOP_MASK_CODE 0x3ff
1661 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
1662 #define MICROMIPSOP_MASK_CODE2 0x3ff
1663 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
1664 #define MICROMIPSOP_MASK_CACHE 0x1f
1665 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
1666 #define MICROMIPSOP_MASK_SEL 0x7
1667 #define MICROMIPSOP_SH_SEL 11
1668 #define MICROMIPSOP_MASK_OFFSET12 0xfff
1669 #define MICROMIPSOP_SH_OFFSET12 0
1670 #define MICROMIPSOP_MASK_3BITPOS 0x7
1671 #define MICROMIPSOP_SH_3BITPOS 21
1672 #define MICROMIPSOP_MASK_STYPE 0x1f
1673 #define MICROMIPSOP_SH_STYPE 16
1674 #define MICROMIPSOP_MASK_OFFSET10 0x3ff
1675 #define MICROMIPSOP_SH_OFFSET10 6
1676 #define MICROMIPSOP_MASK_RS 0x1f
1677 #define MICROMIPSOP_SH_RS 16
1678 #define MICROMIPSOP_MASK_RT 0x1f
1679 #define MICROMIPSOP_SH_RT 21
1680 #define MICROMIPSOP_MASK_RD 0x1f
1681 #define MICROMIPSOP_SH_RD 11
1682 #define MICROMIPSOP_MASK_FS 0x1f
1683 #define MICROMIPSOP_SH_FS 16
1684 #define MICROMIPSOP_MASK_FT 0x1f
1685 #define MICROMIPSOP_SH_FT 21
1686 #define MICROMIPSOP_MASK_FD 0x1f
1687 #define MICROMIPSOP_SH_FD 11
1688 #define MICROMIPSOP_MASK_FR 0x1f
1689 #define MICROMIPSOP_SH_FR 6
1690 #define MICROMIPSOP_MASK_RS3 0x1f
1691 #define MICROMIPSOP_SH_RS3 6
1692 #define MICROMIPSOP_MASK_PREFX 0x1f
1693 #define MICROMIPSOP_SH_PREFX 11
1694 #define MICROMIPSOP_MASK_BCC 0x7
1695 #define MICROMIPSOP_SH_BCC 18
1696 #define MICROMIPSOP_MASK_CCC 0x7
1697 #define MICROMIPSOP_SH_CCC 13
1698 #define MICROMIPSOP_MASK_COPZ 0x7fffff
1699 #define MICROMIPSOP_SH_COPZ 3
1701 #define MICROMIPSOP_MASK_MB 0x7
1702 #define MICROMIPSOP_SH_MB 23
1703 #define MICROMIPSOP_MASK_MC 0x7
1704 #define MICROMIPSOP_SH_MC 4
1705 #define MICROMIPSOP_MASK_MD 0x7
1706 #define MICROMIPSOP_SH_MD 7
1707 #define MICROMIPSOP_MASK_ME 0x7
1708 #define MICROMIPSOP_SH_ME 1
1709 #define MICROMIPSOP_MASK_MF 0x7
1710 #define MICROMIPSOP_SH_MF 3
1711 #define MICROMIPSOP_MASK_MG 0x7
1712 #define MICROMIPSOP_SH_MG 0
1713 #define MICROMIPSOP_MASK_MH 0x7
1714 #define MICROMIPSOP_SH_MH 7
1715 #define MICROMIPSOP_MASK_MJ 0x1f
1716 #define MICROMIPSOP_SH_MJ 0
1717 #define MICROMIPSOP_MASK_ML 0x7
1718 #define MICROMIPSOP_SH_ML 4
1719 #define MICROMIPSOP_MASK_MM 0x7
1720 #define MICROMIPSOP_SH_MM 1
1721 #define MICROMIPSOP_MASK_MN 0x7
1722 #define MICROMIPSOP_SH_MN 4
1723 #define MICROMIPSOP_MASK_MP 0x1f
1724 #define MICROMIPSOP_SH_MP 5
1725 #define MICROMIPSOP_MASK_MQ 0x7
1726 #define MICROMIPSOP_SH_MQ 7
1728 #define MICROMIPSOP_MASK_IMMA 0x7f
1729 #define MICROMIPSOP_SH_IMMA 0
1730 #define MICROMIPSOP_MASK_IMMB 0x7
1731 #define MICROMIPSOP_SH_IMMB 1
1732 #define MICROMIPSOP_MASK_IMMC 0xf
1733 #define MICROMIPSOP_SH_IMMC 0
1734 #define MICROMIPSOP_MASK_IMMD 0x3ff
1735 #define MICROMIPSOP_SH_IMMD 0
1736 #define MICROMIPSOP_MASK_IMME 0x7f
1737 #define MICROMIPSOP_SH_IMME 0
1738 #define MICROMIPSOP_MASK_IMMF 0xf
1739 #define MICROMIPSOP_SH_IMMF 0
1740 #define MICROMIPSOP_MASK_IMMG 0xf
1741 #define MICROMIPSOP_SH_IMMG 0
1742 #define MICROMIPSOP_MASK_IMMH 0xf
1743 #define MICROMIPSOP_SH_IMMH 0
1744 #define MICROMIPSOP_MASK_IMMI 0x7f
1745 #define MICROMIPSOP_SH_IMMI 0
1746 #define MICROMIPSOP_MASK_IMMJ 0xf
1747 #define MICROMIPSOP_SH_IMMJ 0
1748 #define MICROMIPSOP_MASK_IMML 0xf
1749 #define MICROMIPSOP_SH_IMML 0
1750 #define MICROMIPSOP_MASK_IMMM 0x7
1751 #define MICROMIPSOP_SH_IMMM 1
1752 #define MICROMIPSOP_MASK_IMMN 0x3
1753 #define MICROMIPSOP_SH_IMMN 4
1754 #define MICROMIPSOP_MASK_IMMO 0xf
1755 #define MICROMIPSOP_SH_IMMO 0
1756 #define MICROMIPSOP_MASK_IMMP 0x1f
1757 #define MICROMIPSOP_SH_IMMP 0
1758 #define MICROMIPSOP_MASK_IMMQ 0x7fffff
1759 #define MICROMIPSOP_SH_IMMQ 0
1760 #define MICROMIPSOP_MASK_IMMU 0x1f
1761 #define MICROMIPSOP_SH_IMMU 0
1762 #define MICROMIPSOP_MASK_IMMW 0x3f
1763 #define MICROMIPSOP_SH_IMMW 1
1764 #define MICROMIPSOP_MASK_IMMX 0xf
1765 #define MICROMIPSOP_SH_IMMX 1
1766 #define MICROMIPSOP_MASK_IMMY 0x1ff
1767 #define MICROMIPSOP_SH_IMMY 1
1770 #define MICROMIPSOP_MASK_DSPACC 0x3
1771 #define MICROMIPSOP_SH_DSPACC 14
1772 #define MICROMIPSOP_MASK_DSPSFT 0x3f
1773 #define MICROMIPSOP_SH_DSPSFT 16
1774 #define MICROMIPSOP_MASK_SA3 0x7
1775 #define MICROMIPSOP_SH_SA3 13
1776 #define MICROMIPSOP_MASK_SA4 0xf
1777 #define MICROMIPSOP_SH_SA4 12
1778 #define MICROMIPSOP_MASK_IMM8 0xff
1779 #define MICROMIPSOP_SH_IMM8 13
1780 #define MICROMIPSOP_MASK_IMM10 0x3ff
1781 #define MICROMIPSOP_SH_IMM10 16
1782 #define MICROMIPSOP_MASK_WRDSP 0x3f
1783 #define MICROMIPSOP_SH_WRDSP 14
1784 #define MICROMIPSOP_MASK_BP 0x3
1785 #define MICROMIPSOP_SH_BP 14
1787 /* Placeholders for fields that only exist in the traditional 32-bit
1788 instruction encoding; see the comment above for details. */
1789 #define MICROMIPSOP_MASK_CODE20 0
1790 #define MICROMIPSOP_SH_CODE20 0
1791 #define MICROMIPSOP_MASK_PERFREG 0
1792 #define MICROMIPSOP_SH_PERFREG 0
1793 #define MICROMIPSOP_MASK_CODE19 0
1794 #define MICROMIPSOP_SH_CODE19 0
1795 #define MICROMIPSOP_MASK_ALN 0
1796 #define MICROMIPSOP_SH_ALN 0
1797 #define MICROMIPSOP_MASK_VECBYTE 0
1798 #define MICROMIPSOP_SH_VECBYTE 0
1799 #define MICROMIPSOP_MASK_VECALIGN 0
1800 #define MICROMIPSOP_SH_VECALIGN 0
1801 #define MICROMIPSOP_MASK_DSPACC_S 0
1802 #define MICROMIPSOP_SH_DSPACC_S 0
1803 #define MICROMIPSOP_MASK_DSPSFT_7 0
1804 #define MICROMIPSOP_SH_DSPSFT_7 0
1805 #define MICROMIPSOP_MASK_RDDSP 0
1806 #define MICROMIPSOP_SH_RDDSP 0
1807 #define MICROMIPSOP_MASK_MT_U 0
1808 #define MICROMIPSOP_SH_MT_U 0
1809 #define MICROMIPSOP_MASK_MT_H 0
1810 #define MICROMIPSOP_SH_MT_H 0
1811 #define MICROMIPSOP_MASK_MTACC_T 0
1812 #define MICROMIPSOP_SH_MTACC_T 0
1813 #define MICROMIPSOP_MASK_MTACC_D 0
1814 #define MICROMIPSOP_SH_MTACC_D 0
1815 #define MICROMIPSOP_MASK_BBITIND 0
1816 #define MICROMIPSOP_SH_BBITIND 0
1817 #define MICROMIPSOP_MASK_CINSPOS 0
1818 #define MICROMIPSOP_SH_CINSPOS 0
1819 #define MICROMIPSOP_MASK_CINSLM1 0
1820 #define MICROMIPSOP_SH_CINSLM1 0
1821 #define MICROMIPSOP_MASK_SEQI 0
1822 #define MICROMIPSOP_SH_SEQI 0
1823 #define MICROMIPSOP_SH_OFFSET_A 0
1824 #define MICROMIPSOP_MASK_OFFSET_A 0
1825 #define MICROMIPSOP_SH_OFFSET_B 0
1826 #define MICROMIPSOP_MASK_OFFSET_B 0
1827 #define MICROMIPSOP_SH_OFFSET_C 0
1828 #define MICROMIPSOP_MASK_OFFSET_C 0
1829 #define MICROMIPSOP_SH_RZ 0
1830 #define MICROMIPSOP_MASK_RZ 0
1831 #define MICROMIPSOP_SH_FZ 0
1832 #define MICROMIPSOP_MASK_FZ 0
1834 /* microMIPS Enhanced VA Scheme */
1835 #define MICROMIPSOP_SH_EVAOFFSET 0
1836 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
1838 /* These are the characters which may appears in the args field of a microMIPS
1839 instruction. They appear in the order in which the fields appear
1840 when the instruction is used. Commas and parentheses in the args
1841 string are ignored when assembling, and written into the output
1844 The followings are for 16-bit microMIPS instructions.
1847 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1848 The same register used as both source and target.
1849 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1850 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1851 The same register used as both source and target.
1852 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1853 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1854 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
1855 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1856 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1857 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1858 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1859 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1860 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1861 "mr" must be program counter
1863 "mt" must be the same as the previous register
1864 "mx" must be the same as the destination register
1868 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1869 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1870 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1871 32768, 65535) (MICROMIPSOP_*_IMMC)
1872 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1873 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1874 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
1875 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1876 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1877 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1878 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1879 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1880 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1881 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1882 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1883 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1884 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1885 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1886 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1887 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1890 In most cases 32-bit microMIPS instructions use the same characters
1891 as MIPS (with ADDIUPC being a notable exception, but there are some
1894 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1895 "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
1896 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1897 ">" shift amount between 32 and 63, stored after subtracting 32
1898 (MICROMIPSOP_*_SHAMT)
1899 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1900 "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1901 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1902 "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1903 "+i" likewise, but flips bit 0
1904 "b" 5-bit base register (MICROMIPSOP_*_RS)
1905 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1906 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1907 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1908 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1909 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1910 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1911 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1912 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1913 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1914 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1915 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1916 "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1917 "t" 5-bit target register (MICROMIPSOP_*_RT)
1918 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1919 "v" 5-bit same register used as both source and destination
1921 "w" 5-bit same register used as both target and destination
1923 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1924 "z" must be zero register
1925 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1926 "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1927 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1929 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1930 LSB (MICROMIPSOP_*_EXTLSB).
1931 Enforces: 0 <= pos < 32.
1932 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1933 Requires that "+A" or "+E" occur first to set position.
1934 Enforces: 0 < (pos+size) <= 32.
1935 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1936 Requires that "+A" or "+E" occur first to set position.
1937 Enforces: 0 < (pos+size) <= 32.
1938 (Also used by DEXT w/ different limits, but limits for
1939 that are checked by the M_DEXT macro.)
1940 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1941 Enforces: 32 <= pos < 64.
1942 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1943 Requires that "+A" or "+E" occur first to set position.
1944 Enforces: 32 < (pos+size) <= 64.
1945 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1946 Requires that "+A" or "+E" occur first to set position.
1947 Enforces: 32 < (pos+size) <= 64.
1948 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1949 Requires that "+A" or "+E" occur first to set position.
1950 Enforces: 32 < (pos+size) <= 64.
1952 PC-relative addition (ADDIUPC) instruction:
1953 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1954 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1956 Floating point instructions:
1957 "D" 5-bit destination register (MICROMIPSOP_*_FD)
1958 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1959 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1960 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1961 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1962 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1963 "V" 5-bit same register used as floating source and destination or target
1966 Coprocessor instructions:
1967 "E" 5-bit target register (MICROMIPSOP_*_RT)
1968 "G" 5-bit source register (MICROMIPSOP_*_RS)
1969 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1972 "A" general 32 bit expression
1973 "I" 32-bit immediate (value placed in imm_expr).
1974 "+I" 32-bit immediate (value placed in imm2_expr).
1975 "F" 64-bit floating point constant in .rdata
1976 "L" 64-bit floating point constant in .lit8
1977 "f" 32-bit floating point constant
1978 "l" 32-bit floating point constant in .lit4
1981 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
1982 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
1983 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
1984 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
1985 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
1986 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
1987 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
1988 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
1989 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
1990 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
1992 microMIPS Enhanced VA Scheme:
1993 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
1996 "()" parens surrounding optional value
1997 "," separates operands
1998 "+" start of extension sequence
1999 "m" start of microMIPS extension sequence
2001 Characters used so far, for quick reference when adding more:
2004 "ABCDEFGHI KLMN RST V "
2005 "abcd f hijklmnopqrstuvw yz"
2007 Extension character sequences used so far ("+" followed by the
2008 following), for quick reference when adding more:
2014 Extension character sequences used so far ("m" followed by the
2015 following), for quick reference when adding more:
2018 " BCDEFGHIJ LMNOPQ U WXYZ"
2019 " bcdefghij lmn pq st xyz"
2022 extern const struct mips_operand
*decode_micromips_operand (const char *);
2023 extern const struct mips_opcode micromips_opcodes
[];
2024 extern const int bfd_micromips_num_opcodes
;
2026 /* A NOP insn impemented as "or at,at,zero".
2027 Used to implement -mfix-loongson2f. */
2028 #define LOONGSON2F_NOP_INSN 0x00200825
2030 #endif /* _MIPS_H_ */