include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   3    2003, 2004, 2005, 2008, 2009, 2010, 2013
   4    Free Software Foundation, Inc.
   5    Contributed by Ralph Campbell and OSF
   6    Commented and modified by Ian Lance Taylor, Cygnus Support
   7
   8    This file is part of GDB, GAS, and the GNU binutils.
   9
  10    GDB, GAS, and the GNU binutils are free software; you can redistribute
  11    them and/or modify them under the terms of the GNU General Public
  12    License as published by the Free Software Foundation; either version 3,
  13    or (at your option) any later version.
  14
  15    GDB, GAS, and the GNU binutils are distributed in the hope that they
  16    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  17    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  18    the GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this file; see the file COPYING3.  If not, write to the Free
  22    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  23    MA 02110-1301, USA.  */
  24
  25 #ifndef _MIPS_H_
  26 #define _MIPS_H_
  27
  28 #include "bfd.h"
  29
  30 /* These are bit masks and shift counts to use to access the various
  31    fields of an instruction.  To retrieve the X field of an
  32    instruction, use the expression
  33         (i >> OP_SH_X) & OP_MASK_X
  34    To set the same field (to j), use
  35         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  36
  37    Make sure you use fields that are appropriate for the instruction,
  38    of course.
  39
  40    The 'i' format uses OP, RS, RT and IMMEDIATE.
  41
  42    The 'j' format uses OP and TARGET.
  43
  44    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  45
  46    The 'b' format uses OP, RS, RT and DELTA.
  47
  48    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  49
  50    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  51
  52    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  53    breakpoint instruction are not defined; Kane says the breakpoint
  54    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  55    only use ten bits).  An optional two-operand form of break/sdbbp
  56    allows the lower ten bits to be set too, and MIPS32 and later
  57    architectures allow 20 bits to be set with a signal operand
  58    (using CODE20).
  59
  60    The syscall instruction uses CODE20.
  61
  62    The general coprocessor instructions use COPZ.  */
  63
  64 #define OP_MASK_OP              0x3f
  65 #define OP_SH_OP                26
  66 #define OP_MASK_RS              0x1f
  67 #define OP_SH_RS                21
  68 #define OP_MASK_FR              0x1f
  69 #define OP_SH_FR                21
  70 #define OP_MASK_FMT             0x1f
  71 #define OP_SH_FMT               21
  72 #define OP_MASK_BCC             0x7
  73 #define OP_SH_BCC               18
  74 #define OP_MASK_CODE            0x3ff
  75 #define OP_SH_CODE              16
  76 #define OP_MASK_CODE2           0x3ff
  77 #define OP_SH_CODE2             6
  78 #define OP_MASK_RT              0x1f
  79 #define OP_SH_RT                16
  80 #define OP_MASK_FT              0x1f
  81 #define OP_SH_FT                16
  82 #define OP_MASK_CACHE           0x1f
  83 #define OP_SH_CACHE             16
  84 #define OP_MASK_RD              0x1f
  85 #define OP_SH_RD                11
  86 #define OP_MASK_FS              0x1f
  87 #define OP_SH_FS                11
  88 #define OP_MASK_PREFX           0x1f
  89 #define OP_SH_PREFX             11
  90 #define OP_MASK_CCC             0x7
  91 #define OP_SH_CCC               8
  92 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  93 #define OP_SH_CODE20            6
  94 #define OP_MASK_SHAMT           0x1f
  95 #define OP_SH_SHAMT             6
  96 #define OP_MASK_EXTLSB          OP_MASK_SHAMT
  97 #define OP_SH_EXTLSB            OP_SH_SHAMT
  98 #define OP_MASK_STYPE           OP_MASK_SHAMT
  99 #define OP_SH_STYPE             OP_SH_SHAMT
 100 #define OP_MASK_FD              0x1f
 101 #define OP_SH_FD                6
 102 #define OP_MASK_TARGET          0x3ffffff
 103 #define OP_SH_TARGET            0
 104 #define OP_MASK_COPZ            0x1ffffff
 105 #define OP_SH_COPZ              0
 106 #define OP_MASK_IMMEDIATE       0xffff
 107 #define OP_SH_IMMEDIATE         0
 108 #define OP_MASK_DELTA           0xffff
 109 #define OP_SH_DELTA             0
 110 #define OP_MASK_FUNCT           0x3f
 111 #define OP_SH_FUNCT             0
 112 #define OP_MASK_SPEC            0x3f
 113 #define OP_SH_SPEC              0
 114 #define OP_SH_LOCC              8       /* FP condition code.  */
 115 #define OP_SH_HICC              18      /* FP condition code.  */
 116 #define OP_MASK_CC              0x7
 117 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 118 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 119 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 120 #define OP_MASK_COP1SPEC        0xf
 121 #define OP_MASK_COP1SCLR        0x4
 122 #define OP_MASK_COP1CMP         0x3
 123 #define OP_SH_COP1CMP           4
 124 #define OP_SH_FORMAT            21      /* FP short format field.  */
 125 #define OP_MASK_FORMAT          0x7
 126 #define OP_SH_TRUE              16
 127 #define OP_MASK_TRUE            0x1
 128 #define OP_SH_GE                17
 129 #define OP_MASK_GE              0x01
 130 #define OP_SH_UNSIGNED          16
 131 #define OP_MASK_UNSIGNED        0x1
 132 #define OP_SH_HINT              16
 133 #define OP_MASK_HINT            0x1f
 134 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 135 #define OP_MASK_MMI             0x3f
 136 #define OP_SH_MMISUB            6
 137 #define OP_MASK_MMISUB          0x1f
 138 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 139 #define OP_SH_PERFREG           1
 140 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 141 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 142 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 143 #define OP_MASK_CODE19          0x7ffff
 144 #define OP_SH_ALN               21
 145 #define OP_MASK_ALN             0x7
 146 #define OP_SH_VSEL              21
 147 #define OP_MASK_VSEL            0x1f
 148 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 149                                            but 0x8-0xf don't select bytes.  */
 150 #define OP_SH_VECBYTE           22
 151 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 152 #define OP_SH_VECALIGN          21
 153 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 154 #define OP_SH_INSMSB            11
 155 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 156 #define OP_SH_EXTMSBD           11
 157
 158 /* MIPS DSP ASE */
 159 #define OP_SH_DSPACC            11
 160 #define OP_MASK_DSPACC          0x3
 161 #define OP_SH_DSPACC_S          21
 162 #define OP_MASK_DSPACC_S        0x3
 163 #define OP_SH_DSPSFT            20
 164 #define OP_MASK_DSPSFT          0x3f
 165 #define OP_SH_DSPSFT_7          19
 166 #define OP_MASK_DSPSFT_7        0x7f
 167 #define OP_SH_SA3               21
 168 #define OP_MASK_SA3             0x7
 169 #define OP_SH_SA4               21
 170 #define OP_MASK_SA4             0xf
 171 #define OP_SH_IMM8              16
 172 #define OP_MASK_IMM8            0xff
 173 #define OP_SH_IMM10             16
 174 #define OP_MASK_IMM10           0x3ff
 175 #define OP_SH_WRDSP             11
 176 #define OP_MASK_WRDSP           0x3f
 177 #define OP_SH_RDDSP             16
 178 #define OP_MASK_RDDSP           0x3f
 179 #define OP_SH_BP                11
 180 #define OP_MASK_BP              0x3
 181
 182 /* MIPS MT ASE */
 183 #define OP_SH_MT_U              5
 184 #define OP_MASK_MT_U            0x1
 185 #define OP_SH_MT_H              4
 186 #define OP_MASK_MT_H            0x1
 187 #define OP_SH_MTACC_T           18
 188 #define OP_MASK_MTACC_T         0x3
 189 #define OP_SH_MTACC_D           13
 190 #define OP_MASK_MTACC_D         0x3
 191
 192 /* MIPS MCU ASE */
 193 #define OP_MASK_3BITPOS         0x7
 194 #define OP_SH_3BITPOS           12
 195 #define OP_MASK_OFFSET12        0xfff
 196 #define OP_SH_OFFSET12          0
 197
 198 #define OP_OP_COP0              0x10
 199 #define OP_OP_COP1              0x11
 200 #define OP_OP_COP2              0x12
 201 #define OP_OP_COP3              0x13
 202 #define OP_OP_LWC1              0x31
 203 #define OP_OP_LWC2              0x32
 204 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 205 #define OP_OP_LDC1              0x35
 206 #define OP_OP_LDC2              0x36
 207 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 208 #define OP_OP_SWC1              0x39
 209 #define OP_OP_SWC2              0x3a
 210 #define OP_OP_SWC3              0x3b
 211 #define OP_OP_SDC1              0x3d
 212 #define OP_OP_SDC2              0x3e
 213 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 214
 215 /* Values in the 'VSEL' field.  */
 216 #define MDMX_FMTSEL_IMM_QH      0x1d
 217 #define MDMX_FMTSEL_IMM_OB      0x1e
 218 #define MDMX_FMTSEL_VEC_QH      0x15
 219 #define MDMX_FMTSEL_VEC_OB      0x16
 220
 221 /* UDI */
 222 #define OP_SH_UDI1              6
 223 #define OP_MASK_UDI1            0x1f
 224 #define OP_SH_UDI2              6
 225 #define OP_MASK_UDI2            0x3ff
 226 #define OP_SH_UDI3              6
 227 #define OP_MASK_UDI3            0x7fff
 228 #define OP_SH_UDI4              6
 229 #define OP_MASK_UDI4            0xfffff
 230
 231 /* Octeon */
 232 #define OP_SH_BBITIND           16
 233 #define OP_MASK_BBITIND         0x1f
 234 #define OP_SH_CINSPOS           6
 235 #define OP_MASK_CINSPOS         0x1f
 236 #define OP_SH_CINSLM1           11
 237 #define OP_MASK_CINSLM1         0x1f
 238 #define OP_SH_SEQI              6
 239 #define OP_MASK_SEQI            0x3ff
 240
 241 /* Loongson */
 242 #define OP_SH_OFFSET_A          6
 243 #define OP_MASK_OFFSET_A        0xff
 244 #define OP_SH_OFFSET_B          3
 245 #define OP_MASK_OFFSET_B        0xff
 246 #define OP_SH_OFFSET_C          6
 247 #define OP_MASK_OFFSET_C        0x1ff
 248 #define OP_SH_RZ                0
 249 #define OP_MASK_RZ              0x1f
 250 #define OP_SH_FZ                0
 251 #define OP_MASK_FZ              0x1f
 252
 253 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
 254    definition, and vice versa.  This simplifies various parts
 255    of the operand handling in GAS.  The fields below only exist
 256    in the microMIPS encoding, so define each one to have an empty
 257    range.  */
 258 #define OP_MASK_CODE10          0
 259 #define OP_SH_CODE10            0
 260 #define OP_MASK_TRAP            0
 261 #define OP_SH_TRAP              0
 262 #define OP_MASK_OFFSET10        0
 263 #define OP_SH_OFFSET10          0
 264 #define OP_MASK_RS3             0
 265 #define OP_SH_RS3               0
 266 #define OP_MASK_MB              0
 267 #define OP_SH_MB                0
 268 #define OP_MASK_MC              0
 269 #define OP_SH_MC                0
 270 #define OP_MASK_MD              0
 271 #define OP_SH_MD                0
 272 #define OP_MASK_ME              0
 273 #define OP_SH_ME                0
 274 #define OP_MASK_MF              0
 275 #define OP_SH_MF                0
 276 #define OP_MASK_MG              0
 277 #define OP_SH_MG                0
 278 #define OP_MASK_MH              0
 279 #define OP_SH_MH                0
 280 #define OP_MASK_MI              0
 281 #define OP_SH_MI                0
 282 #define OP_MASK_MJ              0
 283 #define OP_SH_MJ                0
 284 #define OP_MASK_ML              0
 285 #define OP_SH_ML                0
 286 #define OP_MASK_MM              0
 287 #define OP_SH_MM                0
 288 #define OP_MASK_MN              0
 289 #define OP_SH_MN                0
 290 #define OP_MASK_MP              0
 291 #define OP_SH_MP                0
 292 #define OP_MASK_MQ              0
 293 #define OP_SH_MQ                0
 294 #define OP_MASK_IMMA            0
 295 #define OP_SH_IMMA              0
 296 #define OP_MASK_IMMB            0
 297 #define OP_SH_IMMB              0
 298 #define OP_MASK_IMMC            0
 299 #define OP_SH_IMMC              0
 300 #define OP_MASK_IMMF            0
 301 #define OP_SH_IMMF              0
 302 #define OP_MASK_IMMG            0
 303 #define OP_SH_IMMG              0
 304 #define OP_MASK_IMMH            0
 305 #define OP_SH_IMMH              0
 306 #define OP_MASK_IMMI            0
 307 #define OP_SH_IMMI              0
 308 #define OP_MASK_IMMJ            0
 309 #define OP_SH_IMMJ              0
 310 #define OP_MASK_IMML            0
 311 #define OP_SH_IMML              0
 312 #define OP_MASK_IMMM            0
 313 #define OP_SH_IMMM              0
 314 #define OP_MASK_IMMN            0
 315 #define OP_SH_IMMN              0
 316 #define OP_MASK_IMMO            0
 317 #define OP_SH_IMMO              0
 318 #define OP_MASK_IMMP            0
 319 #define OP_SH_IMMP              0
 320 #define OP_MASK_IMMQ            0
 321 #define OP_SH_IMMQ              0
 322 #define OP_MASK_IMMU            0
 323 #define OP_SH_IMMU              0
 324 #define OP_MASK_IMMW            0
 325 #define OP_SH_IMMW              0
 326 #define OP_MASK_IMMX            0
 327 #define OP_SH_IMMX              0
 328 #define OP_MASK_IMMY            0
 329 #define OP_SH_IMMY              0
 330
 331 /* This structure holds information for a particular instruction.  */
 332
 333 struct mips_opcode
 334 {
 335   /* The name of the instruction.  */
 336   const char *name;
 337   /* A string describing the arguments for this instruction.  */
 338   const char *args;
 339   /* The basic opcode for the instruction.  When assembling, this
 340      opcode is modified by the arguments to produce the actual opcode
 341      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 342   unsigned long match;
 343   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 344      relevant portions of the opcode when disassembling.  If the
 345      actual opcode anded with the match field equals the opcode field,
 346      then we have found the correct instruction.  If pinfo is
 347      INSN_MACRO, then this field is the macro identifier.  */
 348   unsigned long mask;
 349   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 350      of bits describing the instruction, notably any relevant hazard
 351      information.  */
 352   unsigned long pinfo;
 353   /* A collection of additional bits describing the instruction. */
 354   unsigned long pinfo2;
 355   /* A collection of bits describing the instruction sets of which this
 356      instruction or macro is a member. */
 357   unsigned long membership;
 358   /* A collection of bits describing the instruction sets of which this
 359      instruction or macro is not a member.  */
 360   unsigned long exclusions;
 361 };
 362
 363 /* These are the characters which may appear in the args field of an
 364    instruction.  They appear in the order in which the fields appear
 365    when the instruction is used.  Commas and parentheses in the args
 366    string are ignored when assembling, and written into the output
 367    when disassembling.
 368
 369    Each of these characters corresponds to a mask field defined above.
 370
 371    "1" 5 bit sync type (OP_*_SHAMT)
 372    "<" 5 bit shift amount (OP_*_SHAMT)
 373    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 374    "a" 26 bit target address (OP_*_TARGET)
 375    "b" 5 bit base register (OP_*_RS)
 376    "c" 10 bit breakpoint code (OP_*_CODE)
 377    "d" 5 bit destination register specifier (OP_*_RD)
 378    "h" 5 bit prefx hint (OP_*_PREFX)
 379    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 380    "j" 16 bit signed immediate (OP_*_DELTA)
 381    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 382        Also used for immediate operands in vr5400 vector insns.
 383    "o" 16 bit signed offset (OP_*_DELTA)
 384    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 385    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 386    "r" 5 bit same register used as both source and target (OP_*_RS)
 387    "s" 5 bit source register specifier (OP_*_RS)
 388    "t" 5 bit target register (OP_*_RT)
 389    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 390    "v" 5 bit same register used as both source and destination (OP_*_RS)
 391    "w" 5 bit same register used as both target and destination (OP_*_RT)
 392    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 393        (used by clo and clz)
 394    "C" 25 bit coprocessor function code (OP_*_COPZ)
 395    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 396    "J" 19 bit wait function code (OP_*_CODE19)
 397    "x" accept and ignore register name
 398    "z" must be zero register
 399    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 400    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 401         LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
 402         microMIPS compatibility).
 403         Enforces: 0 <= pos < 32.
 404    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 405         Requires that "+A" or "+E" occur first to set position.
 406         Enforces: 0 < (pos+size) <= 32.
 407    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 408         Requires that "+A" or "+E" occur first to set position.
 409         Enforces: 0 < (pos+size) <= 32.
 410         (Also used by "dext" w/ different limits, but limits for
 411         that are checked by the M_DEXT macro.)
 412    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 413         Enforces: 32 <= pos < 64.
 414    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 415         Requires that "+A" or "+E" occur first to set position.
 416         Enforces: 32 < (pos+size) <= 64.
 417    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 418         Requires that "+A" or "+E" occur first to set position.
 419         Enforces: 32 < (pos+size) <= 64.
 420    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 421         Requires that "+A" or "+E" occur first to set position.
 422         Enforces: 32 < (pos+size) <= 64.
 423
 424    Floating point instructions:
 425    "D" 5 bit destination register (OP_*_FD)
 426    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 427    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 428    "S" 5 bit fs source 1 register (OP_*_FS)
 429    "T" 5 bit ft source 2 register (OP_*_FT)
 430    "R" 5 bit fr source 3 register (OP_*_FR)
 431    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 432    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 433
 434    Coprocessor instructions:
 435    "E" 5 bit target register (OP_*_RT)
 436    "G" 5 bit destination register (OP_*_RD)
 437    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 438    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 439    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 440    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 441    see also "k" above
 442    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 443         for pretty-printing in disassembly only.
 444
 445    Macro instructions:
 446    "A" General 32 bit expression
 447    "I" 32 bit immediate (value placed in imm_expr).
 448    "+I" 32 bit immediate (value placed in imm2_expr).
 449    "F" 64 bit floating point constant in .rdata
 450    "L" 64 bit floating point constant in .lit8
 451    "f" 32 bit floating point constant
 452    "l" 32 bit floating point constant in .lit4
 453
 454    MDMX instruction operands (note that while these use the FP register
 455    fields, they accept both $fN and $vN names for the registers):
 456    "O"  MDMX alignment offset (OP_*_ALN)
 457    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 458    "X"  MDMX destination register (OP_*_FD)
 459    "Y"  MDMX source register (OP_*_FS)
 460    "Z"  MDMX source register (OP_*_FT)
 461
 462    DSP ASE usage:
 463    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 464    "3" 3 bit unsigned immediate (OP_*_SA3)
 465    "4" 4 bit unsigned immediate (OP_*_SA4)
 466    "5" 8 bit unsigned immediate (OP_*_IMM8)
 467    "6" 5 bit unsigned immediate (OP_*_RS)
 468    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 469    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 470    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 471    "0" 6 bit signed immediate (OP_*_DSPSFT)
 472    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 473    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 474    "@" 10 bit signed immediate (OP_*_IMM10)
 475
 476    MT ASE usage:
 477    "!" 1 bit usermode flag (OP_*_MT_U)
 478    "$" 1 bit load high flag (OP_*_MT_H)
 479    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 480    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 481    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 482    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 483    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 484
 485    MCU ASE usage:
 486    "~" 12 bit offset (OP_*_OFFSET12)
 487    "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
 488
 489    UDI immediates:
 490    "+1" UDI immediate bits 6-10
 491    "+2" UDI immediate bits 6-15
 492    "+3" UDI immediate bits 6-20
 493    "+4" UDI immediate bits 6-25
 494
 495    Octeon:
 496    "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
 497    "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
 498         otherwise skips to next candidate.
 499    "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
 500    "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
 501         32 <= pos < 64, otherwise skips to next candidate.
 502    "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
 503    "+s" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.
 504    "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
 505         cint32/exts32.  Enforces non-negative value and that
 506         pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
 507         position field is "+p" or "+P".
 508
 509    Loongson-3A:
 510    "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
 511    "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
 512    "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
 513    "+z" 5-bit rz register (OP_*_RZ)
 514    "+Z" 5-bit fz register (OP_*_FZ)
 515
 516    Other:
 517    "()" parens surrounding optional value
 518    ","  separates operands
 519    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 520    "+"  Start of extension sequence.
 521
 522    Characters used so far, for quick reference when adding more:
 523    "1234567890"
 524    "%[]<>(),+:'@!$*&\~"
 525    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 526    "abcdefghijklopqrstuvwxz"
 527
 528    Extension character sequences used so far ("+" followed by the
 529    following), for quick reference when adding more:
 530    "1234"
 531    "ABCDEFGHIPQSTXZ"
 532    "abcpstxz"
 533 */
 534
 535 /* These are the bits which may be set in the pinfo field of an
 536    instructions, if it is not equal to INSN_MACRO.  */
 537
 538 /* Modifies the general purpose register in OP_*_RD.  */
 539 #define INSN_WRITE_GPR_D            0x00000001
 540 /* Modifies the general purpose register in OP_*_RT.  */
 541 #define INSN_WRITE_GPR_T            0x00000002
 542 /* Modifies general purpose register 31.  */
 543 #define INSN_WRITE_GPR_31           0x00000004
 544 /* Modifies the floating point register in OP_*_FD.  */
 545 #define INSN_WRITE_FPR_D            0x00000008
 546 /* Modifies the floating point register in OP_*_FS.  */
 547 #define INSN_WRITE_FPR_S            0x00000010
 548 /* Modifies the floating point register in OP_*_FT.  */
 549 #define INSN_WRITE_FPR_T            0x00000020
 550 /* Reads the general purpose register in OP_*_RS.  */
 551 #define INSN_READ_GPR_S             0x00000040
 552 /* Reads the general purpose register in OP_*_RT.  */
 553 #define INSN_READ_GPR_T             0x00000080
 554 /* Reads the floating point register in OP_*_FS.  */
 555 #define INSN_READ_FPR_S             0x00000100
 556 /* Reads the floating point register in OP_*_FT.  */
 557 #define INSN_READ_FPR_T             0x00000200
 558 /* Reads the floating point register in OP_*_FR.  */
 559 #define INSN_READ_FPR_R             0x00000400
 560 /* Modifies coprocessor condition code.  */
 561 #define INSN_WRITE_COND_CODE        0x00000800
 562 /* Reads coprocessor condition code.  */
 563 #define INSN_READ_COND_CODE         0x00001000
 564 /* TLB operation.  */
 565 #define INSN_TLB                    0x00002000
 566 /* Reads coprocessor register other than floating point register.  */
 567 #define INSN_COP                    0x00004000
 568 /* Instruction loads value from memory, requiring delay.  */
 569 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 570 /* Instruction loads value from coprocessor, requiring delay.  */
 571 #define INSN_LOAD_COPROC_DELAY      0x00010000
 572 /* Instruction has unconditional branch delay slot.  */
 573 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 574 /* Instruction has conditional branch delay slot.  */
 575 #define INSN_COND_BRANCH_DELAY      0x00040000
 576 /* Conditional branch likely: if branch not taken, insn nullified.  */
 577 #define INSN_COND_BRANCH_LIKELY     0x00080000
 578 /* Moves to coprocessor register, requiring delay.  */
 579 #define INSN_COPROC_MOVE_DELAY      0x00100000
 580 /* Loads coprocessor register from memory, requiring delay.  */
 581 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 582 /* Reads the HI register.  */
 583 #define INSN_READ_HI                0x00400000
 584 /* Reads the LO register.  */
 585 #define INSN_READ_LO                0x00800000
 586 /* Modifies the HI register.  */
 587 #define INSN_WRITE_HI               0x01000000
 588 /* Modifies the LO register.  */
 589 #define INSN_WRITE_LO               0x02000000
 590 /* Not to be placed in a branch delay slot, either architecturally
 591    or for ease of handling (such as with instructions that take a trap).  */
 592 #define INSN_NO_DELAY_SLOT          0x04000000
 593 /* Instruction stores value into memory.  */
 594 #define INSN_STORE_MEMORY           0x08000000
 595 /* Instruction uses single precision floating point.  */
 596 #define FP_S                        0x10000000
 597 /* Instruction uses double precision floating point.  */
 598 #define FP_D                        0x20000000
 599 /* Instruction is part of the tx39's integer multiply family.    */
 600 #define INSN_MULT                   0x40000000
 601 /* Modifies the general purpose register in MICROMIPSOP_*_RS.  */
 602 #define INSN_WRITE_GPR_S            0x80000000
 603 /* Instruction is actually a macro.  It should be ignored by the
 604    disassembler, and requires special treatment by the assembler.  */
 605 #define INSN_MACRO                  0xffffffff
 606
 607 /* These are the bits which may be set in the pinfo2 field of an
 608    instruction. */
 609
 610 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 611 #define INSN2_ALIAS                 0x00000001
 612 /* Instruction reads MDMX accumulator. */
 613 #define INSN2_READ_MDMX_ACC         0x00000002
 614 /* Instruction writes MDMX accumulator. */
 615 #define INSN2_WRITE_MDMX_ACC        0x00000004
 616 /* Macro uses single-precision floating-point instructions.  This should
 617    only be set for macros.  For instructions, FP_S in pinfo carries the
 618    same information.  */
 619 #define INSN2_M_FP_S                0x00000008
 620 /* Macro uses double-precision floating-point instructions.  This should
 621    only be set for macros.  For instructions, FP_D in pinfo carries the
 622    same information.  */
 623 #define INSN2_M_FP_D                0x00000010
 624 /* Modifies the general purpose register in OP_*_RZ.  */
 625 #define INSN2_WRITE_GPR_Z           0x00000020
 626 /* Modifies the floating point register in OP_*_FZ.  */
 627 #define INSN2_WRITE_FPR_Z           0x00000040
 628 /* Reads the general purpose register in OP_*_RZ.  */
 629 #define INSN2_READ_GPR_Z            0x00000080
 630 /* Reads the floating point register in OP_*_FZ.  */
 631 #define INSN2_READ_FPR_Z            0x00000100
 632 /* Reads the general purpose register in OP_*_RD.  */
 633 #define INSN2_READ_GPR_D            0x00000200
 634
 635
 636 /* Instruction has a branch delay slot that requires a 16-bit instruction.  */
 637 #define INSN2_BRANCH_DELAY_16BIT    0x00000400
 638 /* Instruction has a branch delay slot that requires a 32-bit instruction.  */
 639 #define INSN2_BRANCH_DELAY_32BIT    0x00000800
 640 /* Reads the floating point register in MICROMIPSOP_*_FD.  */
 641 #define INSN2_READ_FPR_D            0x00001000
 642 /* Modifies the general purpose register in MICROMIPSOP_*_MB.  */
 643 #define INSN2_WRITE_GPR_MB          0x00002000
 644 /* Reads the general purpose register in MICROMIPSOP_*_MC.  */
 645 #define INSN2_READ_GPR_MC           0x00004000
 646 /* Reads/writes the general purpose register in MICROMIPSOP_*_MD.  */
 647 #define INSN2_MOD_GPR_MD            0x00008000
 648 /* Reads the general purpose register in MICROMIPSOP_*_ME.  */
 649 #define INSN2_READ_GPR_ME           0x00010000
 650 /* Reads/writes the general purpose register in MICROMIPSOP_*_MF.  */
 651 #define INSN2_MOD_GPR_MF            0x00020000
 652 /* Reads the general purpose register in MICROMIPSOP_*_MG.  */
 653 #define INSN2_READ_GPR_MG           0x00040000
 654 /* Reads the general purpose register in MICROMIPSOP_*_MJ.  */
 655 #define INSN2_READ_GPR_MJ           0x00080000
 656 /* Modifies the general purpose register in MICROMIPSOP_*_MJ.  */
 657 #define INSN2_WRITE_GPR_MJ          0x00100000
 658 /* Reads the general purpose register in MICROMIPSOP_*_MP.  */
 659 #define INSN2_READ_GPR_MP           0x00200000
 660 /* Modifies the general purpose register in MICROMIPSOP_*_MP.  */
 661 #define INSN2_WRITE_GPR_MP          0x00400000
 662 /* Reads the general purpose register in MICROMIPSOP_*_MQ.  */
 663 #define INSN2_READ_GPR_MQ           0x00800000
 664 /* Reads/Writes the stack pointer ($29).  */
 665 #define INSN2_MOD_SP                0x01000000
 666 /* Reads the RA ($31) register.  */
 667 #define INSN2_READ_GPR_31           0x02000000
 668 /* Reads the global pointer ($28).  */
 669 #define INSN2_READ_GP               0x04000000
 670 /* Reads the program counter ($pc).  */
 671 #define INSN2_READ_PC               0x08000000
 672 /* Is an unconditional branch insn. */
 673 #define INSN2_UNCOND_BRANCH         0x10000000
 674 /* Is a conditional branch insn. */
 675 #define INSN2_COND_BRANCH           0x20000000
 676 /* Modifies the general purpose registers in MICROMIPSOP_*_MH/I.  */
 677 #define INSN2_WRITE_GPR_MHI         0x40000000
 678 /* Reads the general purpose registers in MICROMIPSOP_*_MM/N.  */
 679 #define INSN2_READ_GPR_MMN          0x80000000
 680
 681 /* Masks used to mark instructions to indicate which MIPS ISA level
 682    they were introduced in.  INSN_ISA_MASK masks an enumeration that
 683    specifies the base ISA level(s).  The remainder of a 32-bit
 684    word constructed using these macros is a bitmask of the remaining
 685    INSN_* values below.  */
 686
 687 #define INSN_ISA_MASK             0x0000000ful
 688
 689 /* We cannot start at zero due to ISA_UNKNOWN below.  */
 690 #define INSN_ISA1                 1
 691 #define INSN_ISA2                 2
 692 #define INSN_ISA3                 3
 693 #define INSN_ISA4                 4
 694 #define INSN_ISA5                 5
 695 #define INSN_ISA32                6
 696 #define INSN_ISA32R2              7
 697 #define INSN_ISA64                8
 698 #define INSN_ISA64R2              9
 699 /* Below this point the INSN_* values correspond to combinations of ISAs.
 700    They are only for use in the opcodes table to indicate membership of
 701    a combination of ISAs that cannot be expressed using the usual inclusion
 702    ordering on the above INSN_* values.  */
 703 #define INSN_ISA3_32              10
 704 #define INSN_ISA3_32R2            11
 705 #define INSN_ISA4_32              12
 706 #define INSN_ISA4_32R2            13
 707 #define INSN_ISA5_32R2            14
 708
 709 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
 710    INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
 711    this table describes whether at least one of the ISAs described by X
 712    is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
 713    a particular core and X as the ISA level(s) at which a certain instruction
 714    is defined.)  The ISA(s) described by X is/are implemented by Y iff
 715    (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
 716    is non-zero.  */
 717 static const unsigned int mips_isa_table[] =
 718   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 719
 720 /* Masks used for Chip specific instructions.  */
 721 #define INSN_CHIP_MASK            0xc3ff0f20
 722
 723 /* Cavium Networks Octeon instructions.  */
 724 #define INSN_OCTEON               0x00000800
 725 #define INSN_OCTEONP              0x00000200
 726 #define INSN_OCTEON2              0x00000100
 727
 728 /* Masks used for MIPS-defined ASEs.  */
 729 #define INSN_ASE_MASK             0x3c00f010
 730
 731 /* DSP ASE */
 732 #define INSN_DSP                  0x00001000
 733 #define INSN_DSP64                0x00002000
 734
 735 /* MIPS R5900 instruction */
 736 #define INSN_5900                 0x00004000
 737
 738 /* MIPS-3D ASE */
 739 #define INSN_MIPS3D               0x00008000
 740
 741 /* MIPS R4650 instruction.  */
 742 #define INSN_4650                 0x00010000
 743 /* LSI R4010 instruction.  */
 744 #define INSN_4010                 0x00020000
 745 /* NEC VR4100 instruction.  */
 746 #define INSN_4100                 0x00040000
 747 /* Toshiba R3900 instruction.  */
 748 #define INSN_3900                 0x00080000
 749 /* MIPS R10000 instruction.  */
 750 #define INSN_10000                0x00100000
 751 /* Broadcom SB-1 instruction.  */
 752 #define INSN_SB1                  0x00200000
 753 /* NEC VR4111/VR4181 instruction.  */
 754 #define INSN_4111                 0x00400000
 755 /* NEC VR4120 instruction.  */
 756 #define INSN_4120                 0x00800000
 757 /* NEC VR5400 instruction.  */
 758 #define INSN_5400                 0x01000000
 759 /* NEC VR5500 instruction.  */
 760 #define INSN_5500                 0x02000000
 761
 762 /* MDMX ASE */
 763 #define INSN_MDMX                 0x04000000
 764 /* MT ASE */
 765 #define INSN_MT                   0x08000000
 766 /* SmartMIPS ASE  */
 767 #define INSN_SMARTMIPS            0x10000000
 768 /* DSP R2 ASE  */
 769 #define INSN_DSPR2                0x20000000
 770 /* ST Microelectronics Loongson 2E.  */
 771 #define INSN_LOONGSON_2E          0x40000000
 772 /* ST Microelectronics Loongson 2F.  */
 773 #define INSN_LOONGSON_2F          0x80000000
 774 /* Loongson 3A.  */
 775 #define INSN_LOONGSON_3A          0x00000400
 776 /* RMI Xlr instruction */
 777 #define INSN_XLR                  0x00000020
 778
 779 /* MCU (MicroController) ASE */
 780 #define INSN_MCU                  0x00000010
 781
 782 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 783
 784 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 785 #define       ISA_MIPS1       INSN_ISA1
 786 #define       ISA_MIPS2       INSN_ISA2
 787 #define       ISA_MIPS3       INSN_ISA3
 788 #define       ISA_MIPS4       INSN_ISA4
 789 #define       ISA_MIPS5       INSN_ISA5
 790
 791 #define       ISA_MIPS32      INSN_ISA32
 792 #define       ISA_MIPS64      INSN_ISA64
 793
 794 #define       ISA_MIPS32R2    INSN_ISA32R2
 795 #define       ISA_MIPS64R2    INSN_ISA64R2
 796
 797
 798 /* CPU defines, use instead of hardcoding processor number. Keep this
 799    in sync with bfd/archures.c in order for machine selection to work.  */
 800 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 801 #define CPU_R3000       3000
 802 #define CPU_R3900       3900
 803 #define CPU_R4000       4000
 804 #define CPU_R4010       4010
 805 #define CPU_VR4100      4100
 806 #define CPU_R4111       4111
 807 #define CPU_VR4120      4120
 808 #define CPU_R4300       4300
 809 #define CPU_R4400       4400
 810 #define CPU_R4600       4600
 811 #define CPU_R4650       4650
 812 #define CPU_R5000       5000
 813 #define CPU_VR5400      5400
 814 #define CPU_VR5500      5500
 815 #define CPU_R5900       5900
 816 #define CPU_R6000       6000
 817 #define CPU_RM7000      7000
 818 #define CPU_R8000       8000
 819 #define CPU_RM9000      9000
 820 #define CPU_R10000      10000
 821 #define CPU_R12000      12000
 822 #define CPU_R14000      14000
 823 #define CPU_R16000      16000
 824 #define CPU_MIPS16      16
 825 #define CPU_MIPS32      32
 826 #define CPU_MIPS32R2    33
 827 #define CPU_MIPS5       5
 828 #define CPU_MIPS64      64
 829 #define CPU_MIPS64R2    65
 830 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 831 #define CPU_LOONGSON_2E 3001
 832 #define CPU_LOONGSON_2F 3002
 833 #define CPU_LOONGSON_3A 3003
 834 #define CPU_OCTEON      6501
 835 #define CPU_OCTEONP     6601
 836 #define CPU_OCTEON2     6502
 837 #define CPU_XLR         887682          /* decimal 'XLR'   */
 838
 839 /* Return true if the given CPU is included in INSN_* mask MASK.  */
 840
 841 static inline bfd_boolean
 842 cpu_is_member (int cpu, unsigned int mask)
 843 {
 844   switch (cpu)
 845     {
 846     case CPU_R4650:
 847     case CPU_RM7000:
 848     case CPU_RM9000:
 849       return (mask & INSN_4650) != 0;
 850
 851     case CPU_R4010:
 852       return (mask & INSN_4010) != 0;
 853
 854     case CPU_VR4100:
 855       return (mask & INSN_4100) != 0;
 856
 857     case CPU_R3900:
 858       return (mask & INSN_3900) != 0;
 859
 860     case CPU_R10000:
 861     case CPU_R12000:
 862     case CPU_R14000:
 863     case CPU_R16000:
 864       return (mask & INSN_10000) != 0;
 865
 866     case CPU_SB1:
 867       return (mask & INSN_SB1) != 0;
 868
 869     case CPU_R4111:
 870       return (mask & INSN_4111) != 0;
 871
 872     case CPU_VR4120:
 873       return (mask & INSN_4120) != 0;
 874
 875     case CPU_VR5400:
 876       return (mask & INSN_5400) != 0;
 877
 878     case CPU_VR5500:
 879       return (mask & INSN_5500) != 0;
 880
 881     case CPU_R5900:
 882       return (mask & INSN_5900) != 0;
 883
 884     case CPU_LOONGSON_2E:
 885       return (mask & INSN_LOONGSON_2E) != 0;
 886
 887     case CPU_LOONGSON_2F:
 888       return (mask & INSN_LOONGSON_2F) != 0;
 889
 890     case CPU_LOONGSON_3A:
 891       return (mask & INSN_LOONGSON_3A) != 0;
 892
 893     case CPU_OCTEON:
 894       return (mask & INSN_OCTEON) != 0;
 895
 896     case CPU_OCTEONP:
 897       return (mask & INSN_OCTEONP) != 0;
 898
 899     case CPU_OCTEON2:
 900       return (mask & INSN_OCTEON2) != 0;
 901
 902     case CPU_XLR:
 903       return (mask & INSN_XLR) != 0;
 904
 905     default:
 906       return FALSE;
 907     }
 908 }
 909
 910 /* Test for membership in an ISA including chip specific ISAs.  INSN
 911    is pointer to an element of the opcode table; ISA is the specified
 912    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 913    test, or zero if no CPU specific ISA test is desired.  Return true
 914    if instruction INSN is available to the given ISA and CPU. */
 915
 916 static inline bfd_boolean
 917 opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
 918 {
 919   if (!cpu_is_member (cpu, insn->exclusions))
 920     {
 921       /* Test for ISA level compatibility.  */
 922       if ((isa & INSN_ISA_MASK) != 0
 923           && (insn->membership & INSN_ISA_MASK) != 0
 924           && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
 925                >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
 926         return TRUE;
 927
 928       /* Test for ASE compatibility.  */
 929       if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
 930         return TRUE;
 931
 932       /* Test for processor-specific extensions.  */
 933       if (cpu_is_member (cpu, insn->membership))
 934         return TRUE;
 935     }
 936   return FALSE;
 937 }
 938
 939 /* This is a list of macro expanded instructions.
 940
 941    _I appended means immediate
 942    _A appended means address
 943    _AB appended means address with base register
 944    _D appended means 64 bit floating point constant
 945    _S appended means 32 bit floating point constant.  */
 946
 947 enum
 948 {
 949   M_ABS,
 950   M_ACLR_AB,
 951   M_ACLR_OB,
 952   M_ADD_I,
 953   M_ADDU_I,
 954   M_AND_I,
 955   M_ASET_AB,
 956   M_ASET_OB,
 957   M_BALIGN,
 958   M_BC1FL,
 959   M_BC1TL,
 960   M_BC2FL,
 961   M_BC2TL,
 962   M_BEQ,
 963   M_BEQ_I,
 964   M_BEQL,
 965   M_BEQL_I,
 966   M_BGE,
 967   M_BGEL,
 968   M_BGE_I,
 969   M_BGEL_I,
 970   M_BGEU,
 971   M_BGEUL,
 972   M_BGEU_I,
 973   M_BGEUL_I,
 974   M_BGEZ,
 975   M_BGEZL,
 976   M_BGEZALL,
 977   M_BGT,
 978   M_BGTL,
 979   M_BGT_I,
 980   M_BGTL_I,
 981   M_BGTU,
 982   M_BGTUL,
 983   M_BGTU_I,
 984   M_BGTUL_I,
 985   M_BGTZ,
 986   M_BGTZL,
 987   M_BLE,
 988   M_BLEL,
 989   M_BLE_I,
 990   M_BLEL_I,
 991   M_BLEU,
 992   M_BLEUL,
 993   M_BLEU_I,
 994   M_BLEUL_I,
 995   M_BLEZ,
 996   M_BLEZL,
 997   M_BLT,
 998   M_BLTL,
 999   M_BLT_I,
1000   M_BLTL_I,
1001   M_BLTU,
1002   M_BLTUL,
1003   M_BLTU_I,
1004   M_BLTUL_I,
1005   M_BLTZ,
1006   M_BLTZL,
1007   M_BLTZALL,
1008   M_BNE,
1009   M_BNEL,
1010   M_BNE_I,
1011   M_BNEL_I,
1012   M_CACHE_AB,
1013   M_CACHE_OB,
1014   M_DABS,
1015   M_DADD_I,
1016   M_DADDU_I,
1017   M_DDIV_3,
1018   M_DDIV_3I,
1019   M_DDIVU_3,
1020   M_DDIVU_3I,
1021   M_DEXT,
1022   M_DINS,
1023   M_DIV_3,
1024   M_DIV_3I,
1025   M_DIVU_3,
1026   M_DIVU_3I,
1027   M_DLA_AB,
1028   M_DLCA_AB,
1029   M_DLI,
1030   M_DMUL,
1031   M_DMUL_I,
1032   M_DMULO,
1033   M_DMULO_I,
1034   M_DMULOU,
1035   M_DMULOU_I,
1036   M_DREM_3,
1037   M_DREM_3I,
1038   M_DREMU_3,
1039   M_DREMU_3I,
1040   M_DSUB_I,
1041   M_DSUBU_I,
1042   M_DSUBU_I_2,
1043   M_J_A,
1044   M_JAL_1,
1045   M_JAL_2,
1046   M_JAL_A,
1047   M_JALS_1,
1048   M_JALS_2,
1049   M_JALS_A,
1050   M_L_DOB,
1051   M_L_DAB,
1052   M_LA_AB,
1053   M_LB_A,
1054   M_LB_AB,
1055   M_LBU_A,
1056   M_LBU_AB,
1057   M_LCA_AB,
1058   M_LD_A,
1059   M_LD_OB,
1060   M_LD_AB,
1061   M_LDC1_AB,
1062   M_LDC2_AB,
1063   M_LDC2_OB,
1064   M_LDC3_AB,
1065   M_LDL_AB,
1066   M_LDL_OB,
1067   M_LDM_AB,
1068   M_LDM_OB,
1069   M_LDP_AB,
1070   M_LDP_OB,
1071   M_LDR_AB,
1072   M_LDR_OB,
1073   M_LH_A,
1074   M_LH_AB,
1075   M_LHU_A,
1076   M_LHU_AB,
1077   M_LI,
1078   M_LI_D,
1079   M_LI_DD,
1080   M_LI_S,
1081   M_LI_SS,
1082   M_LL_AB,
1083   M_LL_OB,
1084   M_LLD_AB,
1085   M_LLD_OB,
1086   M_LQ_AB,
1087   M_LS_A,
1088   M_LW_A,
1089   M_LW_AB,
1090   M_LWC0_A,
1091   M_LWC0_AB,
1092   M_LWC1_A,
1093   M_LWC1_AB,
1094   M_LWC2_A,
1095   M_LWC2_AB,
1096   M_LWC2_OB,
1097   M_LWC3_A,
1098   M_LWC3_AB,
1099   M_LWL_A,
1100   M_LWL_AB,
1101   M_LWL_OB,
1102   M_LWM_AB,
1103   M_LWM_OB,
1104   M_LWP_AB,
1105   M_LWP_OB,
1106   M_LWR_A,
1107   M_LWR_AB,
1108   M_LWR_OB,
1109   M_LWU_AB,
1110   M_LWU_OB,
1111   M_MSGSND,
1112   M_MSGLD,
1113   M_MSGLD_T,
1114   M_MSGWAIT,
1115   M_MSGWAIT_T,
1116   M_MOVE,
1117   M_MUL,
1118   M_MUL_I,
1119   M_MULO,
1120   M_MULO_I,
1121   M_MULOU,
1122   M_MULOU_I,
1123   M_NOR_I,
1124   M_OR_I,
1125   M_PREF_AB,
1126   M_PREF_OB,
1127   M_REM_3,
1128   M_REM_3I,
1129   M_REMU_3,
1130   M_REMU_3I,
1131   M_DROL,
1132   M_ROL,
1133   M_DROL_I,
1134   M_ROL_I,
1135   M_DROR,
1136   M_ROR,
1137   M_DROR_I,
1138   M_ROR_I,
1139   M_S_DA,
1140   M_S_DOB,
1141   M_S_DAB,
1142   M_S_S,
1143   M_SAA_AB,
1144   M_SAA_OB,
1145   M_SAAD_AB,
1146   M_SAAD_OB,
1147   M_SC_AB,
1148   M_SC_OB,
1149   M_SCD_AB,
1150   M_SCD_OB,
1151   M_SD_A,
1152   M_SD_OB,
1153   M_SD_AB,
1154   M_SDC1_AB,
1155   M_SDC2_AB,
1156   M_SDC2_OB,
1157   M_SDC3_AB,
1158   M_SDL_AB,
1159   M_SDL_OB,
1160   M_SDM_AB,
1161   M_SDM_OB,
1162   M_SDP_AB,
1163   M_SDP_OB,
1164   M_SDR_AB,
1165   M_SDR_OB,
1166   M_SEQ,
1167   M_SEQ_I,
1168   M_SGE,
1169   M_SGE_I,
1170   M_SGEU,
1171   M_SGEU_I,
1172   M_SGT,
1173   M_SGT_I,
1174   M_SGTU,
1175   M_SGTU_I,
1176   M_SLE,
1177   M_SLE_I,
1178   M_SLEU,
1179   M_SLEU_I,
1180   M_SLT_I,
1181   M_SLTU_I,
1182   M_SNE,
1183   M_SNE_I,
1184   M_SB_A,
1185   M_SB_AB,
1186   M_SH_A,
1187   M_SH_AB,
1188   M_SQ_AB,
1189   M_SW_A,
1190   M_SW_AB,
1191   M_SWC0_A,
1192   M_SWC0_AB,
1193   M_SWC1_A,
1194   M_SWC1_AB,
1195   M_SWC2_A,
1196   M_SWC2_AB,
1197   M_SWC2_OB,
1198   M_SWC3_A,
1199   M_SWC3_AB,
1200   M_SWL_A,
1201   M_SWL_AB,
1202   M_SWL_OB,
1203   M_SWM_AB,
1204   M_SWM_OB,
1205   M_SWP_AB,
1206   M_SWP_OB,
1207   M_SWR_A,
1208   M_SWR_AB,
1209   M_SWR_OB,
1210   M_SUB_I,
1211   M_SUBU_I,
1212   M_SUBU_I_2,
1213   M_TEQ_I,
1214   M_TGE_I,
1215   M_TGEU_I,
1216   M_TLT_I,
1217   M_TLTU_I,
1218   M_TNE_I,
1219   M_TRUNCWD,
1220   M_TRUNCWS,
1221   M_ULD,
1222   M_ULD_A,
1223   M_ULH,
1224   M_ULH_A,
1225   M_ULHU,
1226   M_ULHU_A,
1227   M_ULW,
1228   M_ULW_A,
1229   M_USH,
1230   M_USH_A,
1231   M_USW,
1232   M_USW_A,
1233   M_USD,
1234   M_USD_A,
1235   M_XOR_I,
1236   M_COP0,
1237   M_COP1,
1238   M_COP2,
1239   M_COP3,
1240   M_NUM_MACROS
1241 };
1242
1243
1244 /* The order of overloaded instructions matters.  Label arguments and
1245    register arguments look the same. Instructions that can have either
1246    for arguments must apear in the correct order in this table for the
1247    assembler to pick the right one. In other words, entries with
1248    immediate operands must apear after the same instruction with
1249    registers.
1250
1251    Many instructions are short hand for other instructions (i.e., The
1252    jal <register> instruction is short for jalr <register>).  */
1253
1254 extern const struct mips_opcode mips_builtin_opcodes[];
1255 extern const int bfd_mips_num_builtin_opcodes;
1256 extern struct mips_opcode *mips_opcodes;
1257 extern int bfd_mips_num_opcodes;
1258 #define NUMOPCODES bfd_mips_num_opcodes
1259
1260 \f
1261 /* The rest of this file adds definitions for the mips16 TinyRISC
1262    processor.  */
1263
1264 /* These are the bitmasks and shift counts used for the different
1265    fields in the instruction formats.  Other than OP, no masks are
1266    provided for the fixed portions of an instruction, since they are
1267    not needed.
1268
1269    The I format uses IMM11.
1270
1271    The RI format uses RX and IMM8.
1272
1273    The RR format uses RX, and RY.
1274
1275    The RRI format uses RX, RY, and IMM5.
1276
1277    The RRR format uses RX, RY, and RZ.
1278
1279    The RRI_A format uses RX, RY, and IMM4.
1280
1281    The SHIFT format uses RX, RY, and SHAMT.
1282
1283    The I8 format uses IMM8.
1284
1285    The I8_MOVR32 format uses RY and REGR32.
1286
1287    The IR_MOV32R format uses REG32R and MOV32Z.
1288
1289    The I64 format uses IMM8.
1290
1291    The RI64 format uses RY and IMM5.
1292    */
1293
1294 #define MIPS16OP_MASK_OP        0x1f
1295 #define MIPS16OP_SH_OP          11
1296 #define MIPS16OP_MASK_IMM11     0x7ff
1297 #define MIPS16OP_SH_IMM11       0
1298 #define MIPS16OP_MASK_RX        0x7
1299 #define MIPS16OP_SH_RX          8
1300 #define MIPS16OP_MASK_IMM8      0xff
1301 #define MIPS16OP_SH_IMM8        0
1302 #define MIPS16OP_MASK_RY        0x7
1303 #define MIPS16OP_SH_RY          5
1304 #define MIPS16OP_MASK_IMM5      0x1f
1305 #define MIPS16OP_SH_IMM5        0
1306 #define MIPS16OP_MASK_RZ        0x7
1307 #define MIPS16OP_SH_RZ          2
1308 #define MIPS16OP_MASK_IMM4      0xf
1309 #define MIPS16OP_SH_IMM4        0
1310 #define MIPS16OP_MASK_REGR32    0x1f
1311 #define MIPS16OP_SH_REGR32      0
1312 #define MIPS16OP_MASK_REG32R    0x1f
1313 #define MIPS16OP_SH_REG32R      3
1314 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1315 #define MIPS16OP_MASK_MOVE32Z   0x7
1316 #define MIPS16OP_SH_MOVE32Z     0
1317 #define MIPS16OP_MASK_IMM6      0x3f
1318 #define MIPS16OP_SH_IMM6        5
1319
1320 /* These are the characters which may appears in the args field of a MIPS16
1321    instruction.  They appear in the order in which the fields appear when the
1322    instruction is used.  Commas and parentheses in the args string are ignored
1323    when assembling, and written into the output when disassembling.
1324
1325    "y" 3 bit register (MIPS16OP_*_RY)
1326    "x" 3 bit register (MIPS16OP_*_RX)
1327    "z" 3 bit register (MIPS16OP_*_RZ)
1328    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1329    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1330    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1331    "0" zero register ($0)
1332    "S" stack pointer ($sp or $29)
1333    "P" program counter
1334    "R" return address register ($ra or $31)
1335    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1336    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1337    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1338    "a" 26 bit jump address
1339    "e" 11 bit extension value
1340    "l" register list for entry instruction
1341    "L" register list for exit instruction
1342
1343    The remaining codes may be extended.  Except as otherwise noted,
1344    the full extended operand is a 16 bit signed value.
1345    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1346    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1347    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1348    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1349    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1350    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1351    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1352    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1353    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1354    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1355    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1356    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1357    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1358    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1359    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1360    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1361    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1362    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1363    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1364    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1365    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1366    "m" 7 bit register list for save instruction (18 bit extended)
1367    "M" 7 bit register list for restore instruction (18 bit extended)
1368   */
1369
1370 /* Save/restore encoding for the args field when all 4 registers are
1371    either saved as arguments or saved/restored as statics.  */
1372 #define MIPS16_ALL_ARGS    0xe
1373 #define MIPS16_ALL_STATICS 0xb
1374
1375 /* For the mips16, we use the same opcode table format and a few of
1376    the same flags.  However, most of the flags are different.  */
1377
1378 /* Modifies the register in MIPS16OP_*_RX.  */
1379 #define MIPS16_INSN_WRITE_X                 0x00000001
1380 /* Modifies the register in MIPS16OP_*_RY.  */
1381 #define MIPS16_INSN_WRITE_Y                 0x00000002
1382 /* Modifies the register in MIPS16OP_*_RZ.  */
1383 #define MIPS16_INSN_WRITE_Z                 0x00000004
1384 /* Modifies the T ($24) register.  */
1385 #define MIPS16_INSN_WRITE_T                 0x00000008
1386 /* Modifies the SP ($29) register.  */
1387 #define MIPS16_INSN_WRITE_SP                0x00000010
1388 /* Modifies the RA ($31) register.  */
1389 #define MIPS16_INSN_WRITE_31                0x00000020
1390 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1391 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1392 /* Reads the register in MIPS16OP_*_RX.  */
1393 #define MIPS16_INSN_READ_X                  0x00000080
1394 /* Reads the register in MIPS16OP_*_RY.  */
1395 #define MIPS16_INSN_READ_Y                  0x00000100
1396 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1397 #define MIPS16_INSN_READ_Z                  0x00000200
1398 /* Reads the T ($24) register.  */
1399 #define MIPS16_INSN_READ_T                  0x00000400
1400 /* Reads the SP ($29) register.  */
1401 #define MIPS16_INSN_READ_SP                 0x00000800
1402 /* Reads the RA ($31) register.  */
1403 #define MIPS16_INSN_READ_31                 0x00001000
1404 /* Reads the program counter.  */
1405 #define MIPS16_INSN_READ_PC                 0x00002000
1406 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1407 #define MIPS16_INSN_READ_GPR_X              0x00004000
1408 /* Is an unconditional branch insn. */
1409 #define MIPS16_INSN_UNCOND_BRANCH           0x00008000
1410 /* Is a conditional branch insn. */
1411 #define MIPS16_INSN_COND_BRANCH             0x00010000
1412
1413 /* The following flags have the same value for the mips16 opcode
1414    table:
1415
1416    INSN_ISA3
1417
1418    INSN_UNCOND_BRANCH_DELAY
1419    INSN_COND_BRANCH_DELAY
1420    INSN_COND_BRANCH_LIKELY (never used)
1421    INSN_READ_HI
1422    INSN_READ_LO
1423    INSN_WRITE_HI
1424    INSN_WRITE_LO
1425    INSN_TRAP
1426    FP_D (never used)
1427    */
1428
1429 extern const struct mips_opcode mips16_opcodes[];
1430 extern const int bfd_mips16_num_opcodes;
1431
1432 /* These are the bit masks and shift counts used for the different fields
1433    in the microMIPS instruction formats.  No masks are provided for the
1434    fixed portions of an instruction, since they are not needed.  */
1435
1436 #define MICROMIPSOP_MASK_IMMEDIATE      0xffff
1437 #define MICROMIPSOP_SH_IMMEDIATE        0
1438 #define MICROMIPSOP_MASK_DELTA          0xffff
1439 #define MICROMIPSOP_SH_DELTA            0
1440 #define MICROMIPSOP_MASK_CODE10         0x3ff
1441 #define MICROMIPSOP_SH_CODE10           16      /* 10-bit wait code.  */
1442 #define MICROMIPSOP_MASK_TRAP           0xf
1443 #define MICROMIPSOP_SH_TRAP             12      /* 4-bit trap code.  */
1444 #define MICROMIPSOP_MASK_SHAMT          0x1f
1445 #define MICROMIPSOP_SH_SHAMT            11
1446 #define MICROMIPSOP_MASK_TARGET         0x3ffffff
1447 #define MICROMIPSOP_SH_TARGET           0
1448 #define MICROMIPSOP_MASK_EXTLSB         0x1f    /* "ext" LSB.  */
1449 #define MICROMIPSOP_SH_EXTLSB           6
1450 #define MICROMIPSOP_MASK_EXTMSBD        0x1f    /* "ext" MSBD.  */
1451 #define MICROMIPSOP_SH_EXTMSBD          11
1452 #define MICROMIPSOP_MASK_INSMSB         0x1f    /* "ins" MSB.  */
1453 #define MICROMIPSOP_SH_INSMSB           11
1454 #define MICROMIPSOP_MASK_CODE           0x3ff
1455 #define MICROMIPSOP_SH_CODE             16      /* 10-bit higher break code. */
1456 #define MICROMIPSOP_MASK_CODE2          0x3ff
1457 #define MICROMIPSOP_SH_CODE2            6       /* 10-bit lower break code.  */
1458 #define MICROMIPSOP_MASK_CACHE          0x1f
1459 #define MICROMIPSOP_SH_CACHE            21      /* 5-bit cache op.  */
1460 #define MICROMIPSOP_MASK_SEL            0x7
1461 #define MICROMIPSOP_SH_SEL              11
1462 #define MICROMIPSOP_MASK_OFFSET12       0xfff
1463 #define MICROMIPSOP_SH_OFFSET12         0
1464 #define MICROMIPSOP_MASK_3BITPOS        0x7
1465 #define MICROMIPSOP_SH_3BITPOS          21
1466 #define MICROMIPSOP_MASK_STYPE          0x1f
1467 #define MICROMIPSOP_SH_STYPE            16
1468 #define MICROMIPSOP_MASK_OFFSET10       0x3ff
1469 #define MICROMIPSOP_SH_OFFSET10         6
1470 #define MICROMIPSOP_MASK_RS             0x1f
1471 #define MICROMIPSOP_SH_RS               16
1472 #define MICROMIPSOP_MASK_RT             0x1f
1473 #define MICROMIPSOP_SH_RT               21
1474 #define MICROMIPSOP_MASK_RD             0x1f
1475 #define MICROMIPSOP_SH_RD               11
1476 #define MICROMIPSOP_MASK_FS             0x1f
1477 #define MICROMIPSOP_SH_FS               16
1478 #define MICROMIPSOP_MASK_FT             0x1f
1479 #define MICROMIPSOP_SH_FT               21
1480 #define MICROMIPSOP_MASK_FD             0x1f
1481 #define MICROMIPSOP_SH_FD               11
1482 #define MICROMIPSOP_MASK_FR             0x1f
1483 #define MICROMIPSOP_SH_FR               6
1484 #define MICROMIPSOP_MASK_RS3            0x1f
1485 #define MICROMIPSOP_SH_RS3              6
1486 #define MICROMIPSOP_MASK_PREFX          0x1f
1487 #define MICROMIPSOP_SH_PREFX            11
1488 #define MICROMIPSOP_MASK_BCC            0x7
1489 #define MICROMIPSOP_SH_BCC              18
1490 #define MICROMIPSOP_MASK_CCC            0x7
1491 #define MICROMIPSOP_SH_CCC              13
1492 #define MICROMIPSOP_MASK_COPZ           0x7fffff
1493 #define MICROMIPSOP_SH_COPZ             3
1494
1495 #define MICROMIPSOP_MASK_MB             0x7
1496 #define MICROMIPSOP_SH_MB               23
1497 #define MICROMIPSOP_MASK_MC             0x7
1498 #define MICROMIPSOP_SH_MC               4
1499 #define MICROMIPSOP_MASK_MD             0x7
1500 #define MICROMIPSOP_SH_MD               7
1501 #define MICROMIPSOP_MASK_ME             0x7
1502 #define MICROMIPSOP_SH_ME               1
1503 #define MICROMIPSOP_MASK_MF             0x7
1504 #define MICROMIPSOP_SH_MF               3
1505 #define MICROMIPSOP_MASK_MG             0x7
1506 #define MICROMIPSOP_SH_MG               0
1507 #define MICROMIPSOP_MASK_MH             0x7
1508 #define MICROMIPSOP_SH_MH               7
1509 #define MICROMIPSOP_MASK_MI             0x7
1510 #define MICROMIPSOP_SH_MI               7
1511 #define MICROMIPSOP_MASK_MJ             0x1f
1512 #define MICROMIPSOP_SH_MJ               0
1513 #define MICROMIPSOP_MASK_ML             0x7
1514 #define MICROMIPSOP_SH_ML               4
1515 #define MICROMIPSOP_MASK_MM             0x7
1516 #define MICROMIPSOP_SH_MM               1
1517 #define MICROMIPSOP_MASK_MN             0x7
1518 #define MICROMIPSOP_SH_MN               4
1519 #define MICROMIPSOP_MASK_MP             0x1f
1520 #define MICROMIPSOP_SH_MP               5
1521 #define MICROMIPSOP_MASK_MQ             0x7
1522 #define MICROMIPSOP_SH_MQ               7
1523
1524 #define MICROMIPSOP_MASK_IMMA           0x7f
1525 #define MICROMIPSOP_SH_IMMA             0
1526 #define MICROMIPSOP_MASK_IMMB           0x7
1527 #define MICROMIPSOP_SH_IMMB             1
1528 #define MICROMIPSOP_MASK_IMMC           0xf
1529 #define MICROMIPSOP_SH_IMMC             0
1530 #define MICROMIPSOP_MASK_IMMD           0x3ff
1531 #define MICROMIPSOP_SH_IMMD             0
1532 #define MICROMIPSOP_MASK_IMME           0x7f
1533 #define MICROMIPSOP_SH_IMME             0
1534 #define MICROMIPSOP_MASK_IMMF           0xf
1535 #define MICROMIPSOP_SH_IMMF             0
1536 #define MICROMIPSOP_MASK_IMMG           0xf
1537 #define MICROMIPSOP_SH_IMMG             0
1538 #define MICROMIPSOP_MASK_IMMH           0xf
1539 #define MICROMIPSOP_SH_IMMH             0
1540 #define MICROMIPSOP_MASK_IMMI           0x7f
1541 #define MICROMIPSOP_SH_IMMI             0
1542 #define MICROMIPSOP_MASK_IMMJ           0xf
1543 #define MICROMIPSOP_SH_IMMJ             0
1544 #define MICROMIPSOP_MASK_IMML           0xf
1545 #define MICROMIPSOP_SH_IMML             0
1546 #define MICROMIPSOP_MASK_IMMM           0x7
1547 #define MICROMIPSOP_SH_IMMM             1
1548 #define MICROMIPSOP_MASK_IMMN           0x3
1549 #define MICROMIPSOP_SH_IMMN             4
1550 #define MICROMIPSOP_MASK_IMMO           0xf
1551 #define MICROMIPSOP_SH_IMMO             0
1552 #define MICROMIPSOP_MASK_IMMP           0x1f
1553 #define MICROMIPSOP_SH_IMMP             0
1554 #define MICROMIPSOP_MASK_IMMQ           0x7fffff
1555 #define MICROMIPSOP_SH_IMMQ             0
1556 #define MICROMIPSOP_MASK_IMMU           0x1f
1557 #define MICROMIPSOP_SH_IMMU             0
1558 #define MICROMIPSOP_MASK_IMMW           0x3f
1559 #define MICROMIPSOP_SH_IMMW             1
1560 #define MICROMIPSOP_MASK_IMMX           0xf
1561 #define MICROMIPSOP_SH_IMMX             1
1562 #define MICROMIPSOP_MASK_IMMY           0x1ff
1563 #define MICROMIPSOP_SH_IMMY             1
1564
1565 /* MIPS DSP ASE */
1566 #define MICROMIPSOP_MASK_DSPACC         0x3
1567 #define MICROMIPSOP_SH_DSPACC           14
1568 #define MICROMIPSOP_MASK_DSPSFT         0x3f
1569 #define MICROMIPSOP_SH_DSPSFT           16
1570 #define MICROMIPSOP_MASK_SA3            0x7
1571 #define MICROMIPSOP_SH_SA3              13
1572 #define MICROMIPSOP_MASK_SA4            0xf
1573 #define MICROMIPSOP_SH_SA4              12
1574 #define MICROMIPSOP_MASK_IMM8           0xff
1575 #define MICROMIPSOP_SH_IMM8             13
1576 #define MICROMIPSOP_MASK_IMM10          0x3ff
1577 #define MICROMIPSOP_SH_IMM10            16
1578 #define MICROMIPSOP_MASK_WRDSP          0x3f
1579 #define MICROMIPSOP_SH_WRDSP            14
1580 #define MICROMIPSOP_MASK_BP             0x3
1581 #define MICROMIPSOP_SH_BP               14
1582
1583 /* Placeholders for fields that only exist in the traditional 32-bit
1584    instruction encoding; see the comment above for details.  */
1585 #define MICROMIPSOP_MASK_CODE20         0
1586 #define MICROMIPSOP_SH_CODE20           0
1587 #define MICROMIPSOP_MASK_PERFREG        0
1588 #define MICROMIPSOP_SH_PERFREG          0
1589 #define MICROMIPSOP_MASK_CODE19         0
1590 #define MICROMIPSOP_SH_CODE19           0
1591 #define MICROMIPSOP_MASK_ALN            0
1592 #define MICROMIPSOP_SH_ALN              0
1593 #define MICROMIPSOP_MASK_VECBYTE        0
1594 #define MICROMIPSOP_SH_VECBYTE          0
1595 #define MICROMIPSOP_MASK_VECALIGN       0
1596 #define MICROMIPSOP_SH_VECALIGN         0
1597 #define MICROMIPSOP_MASK_DSPACC_S       0
1598 #define MICROMIPSOP_SH_DSPACC_S         0
1599 #define MICROMIPSOP_MASK_DSPSFT_7       0
1600 #define MICROMIPSOP_SH_DSPSFT_7         0
1601 #define MICROMIPSOP_MASK_RDDSP          0
1602 #define MICROMIPSOP_SH_RDDSP            0
1603 #define MICROMIPSOP_MASK_MT_U           0
1604 #define MICROMIPSOP_SH_MT_U             0
1605 #define MICROMIPSOP_MASK_MT_H           0
1606 #define MICROMIPSOP_SH_MT_H             0
1607 #define MICROMIPSOP_MASK_MTACC_T        0
1608 #define MICROMIPSOP_SH_MTACC_T          0
1609 #define MICROMIPSOP_MASK_MTACC_D        0
1610 #define MICROMIPSOP_SH_MTACC_D          0
1611 #define MICROMIPSOP_MASK_BBITIND        0
1612 #define MICROMIPSOP_SH_BBITIND          0
1613 #define MICROMIPSOP_MASK_CINSPOS        0
1614 #define MICROMIPSOP_SH_CINSPOS          0
1615 #define MICROMIPSOP_MASK_CINSLM1        0
1616 #define MICROMIPSOP_SH_CINSLM1          0
1617 #define MICROMIPSOP_MASK_SEQI           0
1618 #define MICROMIPSOP_SH_SEQI             0
1619 #define MICROMIPSOP_SH_OFFSET_A         0
1620 #define MICROMIPSOP_MASK_OFFSET_A       0
1621 #define MICROMIPSOP_SH_OFFSET_B         0
1622 #define MICROMIPSOP_MASK_OFFSET_B       0
1623 #define MICROMIPSOP_SH_OFFSET_C         0
1624 #define MICROMIPSOP_MASK_OFFSET_C       0
1625 #define MICROMIPSOP_SH_RZ               0
1626 #define MICROMIPSOP_MASK_RZ             0
1627 #define MICROMIPSOP_SH_FZ               0
1628 #define MICROMIPSOP_MASK_FZ             0
1629
1630 /* These are the characters which may appears in the args field of a microMIPS
1631    instruction.  They appear in the order in which the fields appear
1632    when the instruction is used.  Commas and parentheses in the args
1633    string are ignored when assembling, and written into the output
1634    when disassembling.
1635
1636    The followings are for 16-bit microMIPS instructions.
1637
1638    "ma" must be $28
1639    "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1640         The same register used as both source and target.
1641    "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1642    "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1643         The same register used as both source and target.
1644    "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1645    "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1646    "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
1647    "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
1648         ("mh" and "mi" form a valid 3-bit register pair)
1649    "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1650    "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1651    "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1652    "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1653    "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1654    "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1655    "mr" must be program counter
1656    "ms" must be $29
1657    "mt" must be the same as the previous register
1658    "mx" must be the same as the destination register
1659    "my" must be $31
1660    "mz" must be $0
1661
1662    "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1663    "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1664    "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1665         32768, 65535) (MICROMIPSOP_*_IMMC)
1666    "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1667    "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1668    "mF" 4-bit immediate (0 .. 15)  (MICROMIPSOP_*_IMMF)
1669    "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1670    "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1671    "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1672    "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1673    "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1674    "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1675    "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1676    "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1677    "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1678    "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1679    "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1680    "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1681    "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1682    "mZ" must be zero
1683
1684    In most cases 32-bit microMIPS instructions use the same characters
1685    as MIPS (with ADDIUPC being a notable exception, but there are some
1686    others too).
1687
1688    "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1689    "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
1690    "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1691    ">" shift amount between 32 and 63, stored after subtracting 32
1692        (MICROMIPSOP_*_SHAMT)
1693    "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1694    "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1695    "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1696    "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1697    "b" 5-bit base register (MICROMIPSOP_*_RS)
1698    "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1699    "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1700    "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1701    "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1702    "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1703    "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1704    "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1705    "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1706    "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1707    "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1708    "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1709    "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1710    "t" 5-bit target register (MICROMIPSOP_*_RT)
1711    "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1712    "v" 5-bit same register used as both source and destination
1713        (MICROMIPSOP_*_RS)
1714    "w" 5-bit same register used as both target and destination
1715        (MICROMIPSOP_*_RT)
1716    "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1717    "z" must be zero register
1718    "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1719    "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1720    "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1721
1722    "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1723         LSB (MICROMIPSOP_*_EXTLSB).
1724         Enforces: 0 <= pos < 32.
1725    "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1726         Requires that "+A" or "+E" occur first to set position.
1727         Enforces: 0 < (pos+size) <= 32.
1728    "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1729         Requires that "+A" or "+E" occur first to set position.
1730         Enforces: 0 < (pos+size) <= 32.
1731         (Also used by DEXT w/ different limits, but limits for
1732         that are checked by the M_DEXT macro.)
1733    "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1734         Enforces: 32 <= pos < 64.
1735    "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1736         Requires that "+A" or "+E" occur first to set position.
1737         Enforces: 32 < (pos+size) <= 64.
1738    "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1739         Requires that "+A" or "+E" occur first to set position.
1740         Enforces: 32 < (pos+size) <= 64.
1741    "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1742         Requires that "+A" or "+E" occur first to set position.
1743         Enforces: 32 < (pos+size) <= 64.
1744
1745    PC-relative addition (ADDIUPC) instruction:
1746    "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1747    "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1748
1749    Floating point instructions:
1750    "D" 5-bit destination register (MICROMIPSOP_*_FD)
1751    "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1752    "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1753    "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1754    "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1755    "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1756    "V" 5-bit same register used as floating source and destination or target
1757        (MICROMIPSOP_*_FS)
1758
1759    Coprocessor instructions:
1760    "E" 5-bit target register (MICROMIPSOP_*_RT)
1761    "G" 5-bit destination register (MICROMIPSOP_*_RD)
1762    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1763    "+D" combined destination register ("G") and sel ("H") for CP0 ops,
1764         for pretty-printing in disassembly only
1765
1766    Macro instructions:
1767    "A" general 32 bit expression
1768    "I" 32-bit immediate (value placed in imm_expr).
1769    "+I" 32-bit immediate (value placed in imm2_expr).
1770    "F" 64-bit floating point constant in .rdata
1771    "L" 64-bit floating point constant in .lit8
1772    "f" 32-bit floating point constant
1773    "l" 32-bit floating point constant in .lit4
1774
1775    DSP ASE usage:
1776    "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
1777    "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
1778    "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
1779    "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
1780    "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
1781    "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
1782    "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
1783    "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
1784    "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
1785    "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
1786
1787    Other:
1788    "()" parens surrounding optional value
1789    ","  separates operands
1790    "+"  start of extension sequence
1791    "m"  start of microMIPS extension sequence
1792
1793    Characters used so far, for quick reference when adding more:
1794    "12345678 0"
1795    "<>(),+.@\^|~"
1796    "ABCDEFGHI KLMN   RST V    "
1797    "abcd f hijklmnopqrstuvw yz"
1798
1799    Extension character sequences used so far ("+" followed by the
1800    following), for quick reference when adding more:
1801    ""
1802    ""
1803    "ABCDEFGHI"
1804    ""
1805
1806    Extension character sequences used so far ("m" followed by the
1807    following), for quick reference when adding more:
1808    ""
1809    ""
1810    " BCDEFGHIJ LMNOPQ   U WXYZ"
1811    " bcdefghij lmn pq st   xyz"
1812 */
1813
1814 extern const struct mips_opcode micromips_opcodes[];
1815 extern const int bfd_micromips_num_opcodes;
1816
1817 /* A NOP insn impemented as "or at,at,zero".
1818    Used to implement -mfix-loongson2f.  */
1819 #define LOONGSON2F_NOP_INSN     0x00200825
1820
1821 #endif /* _MIPS_H_ */