1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
7 This file is part of GDB, GAS, and the GNU binutils.
9 GDB, GAS, and the GNU binutils are free software; you can redistribute
10 them and/or modify them under the terms of the GNU General Public
11 License as published by the Free Software Foundation; either version
12 1, or (at your option) any later version.
14 GDB, GAS, and the GNU binutils are distributed in the hope that they
15 will be useful, but WITHOUT ANY WARRANTY; without even the implied
16 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17 the GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this file; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 /* These are bit masks and shift counts to use to access the various
27 fields of an instruction. To retrieve the X field of an
28 instruction, use the expression
29 (i >> OP_SH_X) & OP_MASK_X
30 To set the same field (to j), use
31 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
33 Make sure you use fields that are appropriate for the instruction,
36 The 'i' format uses OP, RS, RT and IMMEDIATE.
38 The 'j' format uses OP and TARGET.
40 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
42 The 'b' format uses OP, RS, RT and DELTA.
44 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
46 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
48 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
49 breakpoint instruction are not defined; Kane says the breakpoint
50 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
51 only use ten bits). An optional two-operand form of break/sdbbp
52 allows the lower ten bits to be set too, and MIPS32 and later
53 architectures allow 20 bits to be set with a signal operand
56 The syscall instruction uses CODE20.
58 The general coprocessor instructions use COPZ. */
60 #define OP_MASK_OP 0x3f
62 #define OP_MASK_RS 0x1f
64 #define OP_MASK_FR 0x1f
66 #define OP_MASK_FMT 0x1f
68 #define OP_MASK_BCC 0x7
70 #define OP_MASK_CODE 0x3ff
72 #define OP_MASK_CODE2 0x3ff
74 #define OP_MASK_RT 0x1f
76 #define OP_MASK_FT 0x1f
78 #define OP_MASK_CACHE 0x1f
79 #define OP_SH_CACHE 16
80 #define OP_MASK_RD 0x1f
82 #define OP_MASK_FS 0x1f
84 #define OP_MASK_PREFX 0x1f
85 #define OP_SH_PREFX 11
86 #define OP_MASK_CCC 0x7
88 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
89 #define OP_SH_CODE20 6
90 #define OP_MASK_SHAMT 0x1f
92 #define OP_MASK_FD 0x1f
94 #define OP_MASK_TARGET 0x3ffffff
95 #define OP_SH_TARGET 0
96 #define OP_MASK_COPZ 0x1ffffff
98 #define OP_MASK_IMMEDIATE 0xffff
99 #define OP_SH_IMMEDIATE 0
100 #define OP_MASK_DELTA 0xffff
101 #define OP_SH_DELTA 0
102 #define OP_MASK_FUNCT 0x3f
103 #define OP_SH_FUNCT 0
104 #define OP_MASK_SPEC 0x3f
106 #define OP_SH_LOCC 8 /* FP condition code. */
107 #define OP_SH_HICC 18 /* FP condition code. */
108 #define OP_MASK_CC 0x7
109 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
110 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
111 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
112 #define OP_MASK_COP1SPEC 0xf
113 #define OP_MASK_COP1SCLR 0x4
114 #define OP_MASK_COP1CMP 0x3
115 #define OP_SH_COP1CMP 4
116 #define OP_SH_FORMAT 21 /* FP short format field. */
117 #define OP_MASK_FORMAT 0x7
118 #define OP_SH_TRUE 16
119 #define OP_MASK_TRUE 0x1
121 #define OP_MASK_GE 0x01
122 #define OP_SH_UNSIGNED 16
123 #define OP_MASK_UNSIGNED 0x1
124 #define OP_SH_HINT 16
125 #define OP_MASK_HINT 0x1f
126 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
127 #define OP_MASK_MMI 0x3f
128 #define OP_SH_MMISUB 6
129 #define OP_MASK_MMISUB 0x1f
130 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
131 #define OP_SH_PERFREG 1
132 #define OP_SH_SEL 0 /* Coprocessor select field. */
133 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
134 #define OP_SH_CODE19 6 /* 19 bit wait code. */
135 #define OP_MASK_CODE19 0x7ffff
137 #define OP_MASK_ALN 0x7
138 #define OP_SH_VSEL 21
139 #define OP_MASK_VSEL 0x1f
140 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
141 but 0x8-0xf don't select bytes. */
142 #define OP_SH_VECBYTE 22
143 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
144 #define OP_SH_VECALIGN 21
146 #define OP_OP_COP0 0x10
147 #define OP_OP_COP1 0x11
148 #define OP_OP_COP2 0x12
149 #define OP_OP_COP3 0x13
150 #define OP_OP_LWC1 0x31
151 #define OP_OP_LWC2 0x32
152 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
153 #define OP_OP_LDC1 0x35
154 #define OP_OP_LDC2 0x36
155 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
156 #define OP_OP_SWC1 0x39
157 #define OP_OP_SWC2 0x3a
158 #define OP_OP_SWC3 0x3b
159 #define OP_OP_SDC1 0x3d
160 #define OP_OP_SDC2 0x3e
161 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
163 /* Values in the 'VSEL' field. */
164 #define MDMX_FMTSEL_IMM_QH 0x1d
165 #define MDMX_FMTSEL_IMM_OB 0x1e
166 #define MDMX_FMTSEL_VEC_QH 0x15
167 #define MDMX_FMTSEL_VEC_OB 0x16
169 /* This structure holds information for a particular instruction. */
173 /* The name of the instruction. */
175 /* A string describing the arguments for this instruction. */
177 /* The basic opcode for the instruction. When assembling, this
178 opcode is modified by the arguments to produce the actual opcode
179 that is used. If pinfo is INSN_MACRO, then this is 0. */
181 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
182 relevant portions of the opcode when disassembling. If the
183 actual opcode anded with the match field equals the opcode field,
184 then we have found the correct instruction. If pinfo is
185 INSN_MACRO, then this field is the macro identifier. */
187 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
188 of bits describing the instruction, notably any relevant hazard
191 /* A collection of bits describing the instruction sets of which this
192 instruction or macro is a member. */
193 unsigned long membership
;
196 /* These are the characters which may appears in the args field of an
197 instruction. They appear in the order in which the fields appear
198 when the instruction is used. Commas and parentheses in the args
199 string are ignored when assembling, and written into the output
202 Each of these characters corresponds to a mask field defined above.
204 "<" 5 bit shift amount (OP_*_SHAMT)
205 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
206 "a" 26 bit target address (OP_*_TARGET)
207 "b" 5 bit base register (OP_*_RS)
208 "c" 10 bit breakpoint code (OP_*_CODE)
209 "d" 5 bit destination register specifier (OP_*_RD)
210 "h" 5 bit prefx hint (OP_*_PREFX)
211 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
212 "j" 16 bit signed immediate (OP_*_DELTA)
213 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
214 Also used for immediate operands in vr5400 vector insns.
215 "o" 16 bit signed offset (OP_*_DELTA)
216 "p" 16 bit PC relative branch target address (OP_*_DELTA)
217 "q" 10 bit extra breakpoint code (OP_*_CODE2)
218 "r" 5 bit same register used as both source and target (OP_*_RS)
219 "s" 5 bit source register specifier (OP_*_RS)
220 "t" 5 bit target register (OP_*_RT)
221 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
222 "v" 5 bit same register used as both source and destination (OP_*_RS)
223 "w" 5 bit same register used as both target and destination (OP_*_RT)
224 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
225 (used by clo and clz)
226 "C" 25 bit coprocessor function code (OP_*_COPZ)
227 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
228 "J" 19 bit wait function code (OP_*_CODE19)
229 "x" accept and ignore register name
230 "z" must be zero register
232 Floating point instructions:
233 "D" 5 bit destination register (OP_*_FD)
234 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
235 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
236 "S" 5 bit fs source 1 register (OP_*_FS)
237 "T" 5 bit ft source 2 register (OP_*_FT)
238 "R" 5 bit fr source 3 register (OP_*_FR)
239 "V" 5 bit same register used as floating source and destination (OP_*_FS)
240 "W" 5 bit same register used as floating target and destination (OP_*_FT)
242 Coprocessor instructions:
243 "E" 5 bit target register (OP_*_RT)
244 "G" 5 bit destination register (OP_*_RD)
245 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
246 "P" 5 bit performance-monitor register (OP_*_PERFREG)
247 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
248 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
252 "A" General 32 bit expression
254 "F" 64 bit floating point constant in .rdata
255 "L" 64 bit floating point constant in .lit8
256 "f" 32 bit floating point constant
257 "l" 32 bit floating point constant in .lit4
259 MDMX instruction operands (note that while these use the FP register
260 fields, they accept both $fN and $vN names for the registers):
261 "O" MDMX alignment offset (OP_*_ALN)
262 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
263 "X" MDMX destination register (OP_*_FD)
264 "Y" MDMX source register (OP_*_FS)
265 "Z" MDMX source register (OP_*_FT)
268 "()" parens surrounding optional value
269 "," separates operands
270 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
272 Characters used so far, for quick reference when adding more:
274 "ABCDEFGHIJLMNOPQRSTUVWXYZ"
275 "abcdefhijklopqrstuvwxz"
278 /* These are the bits which may be set in the pinfo field of an
279 instructions, if it is not equal to INSN_MACRO. */
281 /* Modifies the general purpose register in OP_*_RD. */
282 #define INSN_WRITE_GPR_D 0x00000001
283 /* Modifies the general purpose register in OP_*_RT. */
284 #define INSN_WRITE_GPR_T 0x00000002
285 /* Modifies general purpose register 31. */
286 #define INSN_WRITE_GPR_31 0x00000004
287 /* Modifies the floating point register in OP_*_FD. */
288 #define INSN_WRITE_FPR_D 0x00000008
289 /* Modifies the floating point register in OP_*_FS. */
290 #define INSN_WRITE_FPR_S 0x00000010
291 /* Modifies the floating point register in OP_*_FT. */
292 #define INSN_WRITE_FPR_T 0x00000020
293 /* Reads the general purpose register in OP_*_RS. */
294 #define INSN_READ_GPR_S 0x00000040
295 /* Reads the general purpose register in OP_*_RT. */
296 #define INSN_READ_GPR_T 0x00000080
297 /* Reads the floating point register in OP_*_FS. */
298 #define INSN_READ_FPR_S 0x00000100
299 /* Reads the floating point register in OP_*_FT. */
300 #define INSN_READ_FPR_T 0x00000200
301 /* Reads the floating point register in OP_*_FR. */
302 #define INSN_READ_FPR_R 0x00000400
303 /* Modifies coprocessor condition code. */
304 #define INSN_WRITE_COND_CODE 0x00000800
305 /* Reads coprocessor condition code. */
306 #define INSN_READ_COND_CODE 0x00001000
308 #define INSN_TLB 0x00002000
309 /* Reads coprocessor register other than floating point register. */
310 #define INSN_COP 0x00004000
311 /* Instruction loads value from memory, requiring delay. */
312 #define INSN_LOAD_MEMORY_DELAY 0x00008000
313 /* Instruction loads value from coprocessor, requiring delay. */
314 #define INSN_LOAD_COPROC_DELAY 0x00010000
315 /* Instruction has unconditional branch delay slot. */
316 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
317 /* Instruction has conditional branch delay slot. */
318 #define INSN_COND_BRANCH_DELAY 0x00040000
319 /* Conditional branch likely: if branch not taken, insn nullified. */
320 #define INSN_COND_BRANCH_LIKELY 0x00080000
321 /* Moves to coprocessor register, requiring delay. */
322 #define INSN_COPROC_MOVE_DELAY 0x00100000
323 /* Loads coprocessor register from memory, requiring delay. */
324 #define INSN_COPROC_MEMORY_DELAY 0x00200000
325 /* Reads the HI register. */
326 #define INSN_READ_HI 0x00400000
327 /* Reads the LO register. */
328 #define INSN_READ_LO 0x00800000
329 /* Modifies the HI register. */
330 #define INSN_WRITE_HI 0x01000000
331 /* Modifies the LO register. */
332 #define INSN_WRITE_LO 0x02000000
333 /* Takes a trap (easier to keep out of delay slot). */
334 #define INSN_TRAP 0x04000000
335 /* Instruction stores value into memory. */
336 #define INSN_STORE_MEMORY 0x08000000
337 /* Instruction uses single precision floating point. */
338 #define FP_S 0x10000000
339 /* Instruction uses double precision floating point. */
340 #define FP_D 0x20000000
341 /* Instruction is part of the tx39's integer multiply family. */
342 #define INSN_MULT 0x40000000
343 /* Instruction synchronize shared memory. */
344 #define INSN_SYNC 0x80000000
345 /* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
346 #define INSN_READ_MDMX_ACC 0
347 /* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
348 #define INSN_WRITE_MDMX_ACC 0
350 /* Instruction is actually a macro. It should be ignored by the
351 disassembler, and requires special treatment by the assembler. */
352 #define INSN_MACRO 0xffffffff
354 /* Masks used to mark instructions to indicate which MIPS ISA level
355 they were introduced in. ISAs, as defined below, are logical
356 ORs of these bits, indicatingthat they support the instructions
357 defined at the given level. */
359 #define INSN_ISA_MASK 0x00000fff
360 #define INSN_ISA1 0x00000010
361 #define INSN_ISA2 0x00000020
362 #define INSN_ISA3 0x00000040
363 #define INSN_ISA4 0x00000080
364 #define INSN_ISA5 0x00000100
365 #define INSN_ISA32 0x00000200
366 #define INSN_ISA64 0x00000400
368 /* Masks used for MIPS-defined ASEs. */
369 #define INSN_ASE_MASK 0x0000f000
372 #define INSN_MIPS16 0x00002000
374 #define INSN_MIPS3D 0x00004000
376 #define INSN_MDMX 0x00008000
378 /* Chip specific instructions. These are bitmasks. */
380 /* MIPS R4650 instruction. */
381 #define INSN_4650 0x00010000
382 /* LSI R4010 instruction. */
383 #define INSN_4010 0x00020000
384 /* NEC VR4100 instruction. */
385 #define INSN_4100 0x00040000
386 /* Toshiba R3900 instruction. */
387 #define INSN_3900 0x00080000
388 /* MIPS R10000 instruction. */
389 #define INSN_10000 0x00100000
390 /* Broadcom SB-1 instruction. */
391 #define INSN_SB1 0x00200000
392 /* NEC VR4111/VR4181 instruction. */
393 #define INSN_4111 0x00400000
394 /* NEC VR4120 instruction. */
395 #define INSN_4120 0x00800000
396 /* NEC VR5400 instruction. */
397 #define INSN_5400 0x01000000
398 /* NEC VR5500 instruction. */
399 #define INSN_5500 0x02000000
401 /* MIPS ISA defines, use instead of hardcoding ISA level. */
403 #define ISA_UNKNOWN 0 /* Gas internal use. */
404 #define ISA_MIPS1 (INSN_ISA1)
405 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
406 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
407 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
408 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
409 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
410 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
412 /* CPU defines, use instead of hardcoding processor number. Keep this
413 in sync with bfd/archures.c in order for machine selection to work. */
414 #define CPU_UNKNOWN 0 /* Gas internal use. */
415 #define CPU_R3000 3000
416 #define CPU_R3900 3900
417 #define CPU_R4000 4000
418 #define CPU_R4010 4010
419 #define CPU_VR4100 4100
420 #define CPU_R4111 4111
421 #define CPU_VR4120 4120
422 #define CPU_R4300 4300
423 #define CPU_R4400 4400
424 #define CPU_R4600 4600
425 #define CPU_R4650 4650
426 #define CPU_R5000 5000
427 #define CPU_VR5400 5400
428 #define CPU_VR5500 5500
429 #define CPU_R6000 6000
430 #define CPU_R8000 8000
431 #define CPU_R10000 10000
432 #define CPU_R12000 12000
433 #define CPU_MIPS16 16
434 #define CPU_MIPS32 32
436 #define CPU_MIPS64 64
437 #define CPU_SB1 12310201 /* octal 'SB', 01. */
439 /* Test for membership in an ISA including chip specific ISAs. INSN
440 is pointer to an element of the opcode table; ISA is the specified
441 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
442 test, or zero if no CPU specific ISA test is desired. */
444 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
445 (((insn)->membership & isa) != 0 \
446 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
447 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
448 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
449 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
450 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
451 && ((insn)->membership & INSN_10000) != 0) \
452 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
453 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
454 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
455 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
456 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
457 || 0) /* Please keep this term for easier source merging. */
459 /* This is a list of macro expanded instructions.
461 _I appended means immediate
462 _A appended means address
463 _AB appended means address with base register
464 _D appended means 64 bit floating point constant
465 _S appended means 32 bit floating point constant. */
688 /* The order of overloaded instructions matters. Label arguments and
689 register arguments look the same. Instructions that can have either
690 for arguments must apear in the correct order in this table for the
691 assembler to pick the right one. In other words, entries with
692 immediate operands must apear after the same instruction with
695 Many instructions are short hand for other instructions (i.e., The
696 jal <register> instruction is short for jalr <register>). */
698 extern const struct mips_opcode mips_builtin_opcodes
[];
699 extern const int bfd_mips_num_builtin_opcodes
;
700 extern struct mips_opcode
*mips_opcodes
;
701 extern int bfd_mips_num_opcodes
;
702 #define NUMOPCODES bfd_mips_num_opcodes
705 /* The rest of this file adds definitions for the mips16 TinyRISC
708 /* These are the bitmasks and shift counts used for the different
709 fields in the instruction formats. Other than OP, no masks are
710 provided for the fixed portions of an instruction, since they are
713 The I format uses IMM11.
715 The RI format uses RX and IMM8.
717 The RR format uses RX, and RY.
719 The RRI format uses RX, RY, and IMM5.
721 The RRR format uses RX, RY, and RZ.
723 The RRI_A format uses RX, RY, and IMM4.
725 The SHIFT format uses RX, RY, and SHAMT.
727 The I8 format uses IMM8.
729 The I8_MOVR32 format uses RY and REGR32.
731 The IR_MOV32R format uses REG32R and MOV32Z.
733 The I64 format uses IMM8.
735 The RI64 format uses RY and IMM5.
738 #define MIPS16OP_MASK_OP 0x1f
739 #define MIPS16OP_SH_OP 11
740 #define MIPS16OP_MASK_IMM11 0x7ff
741 #define MIPS16OP_SH_IMM11 0
742 #define MIPS16OP_MASK_RX 0x7
743 #define MIPS16OP_SH_RX 8
744 #define MIPS16OP_MASK_IMM8 0xff
745 #define MIPS16OP_SH_IMM8 0
746 #define MIPS16OP_MASK_RY 0x7
747 #define MIPS16OP_SH_RY 5
748 #define MIPS16OP_MASK_IMM5 0x1f
749 #define MIPS16OP_SH_IMM5 0
750 #define MIPS16OP_MASK_RZ 0x7
751 #define MIPS16OP_SH_RZ 2
752 #define MIPS16OP_MASK_IMM4 0xf
753 #define MIPS16OP_SH_IMM4 0
754 #define MIPS16OP_MASK_REGR32 0x1f
755 #define MIPS16OP_SH_REGR32 0
756 #define MIPS16OP_MASK_REG32R 0x1f
757 #define MIPS16OP_SH_REG32R 3
758 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
759 #define MIPS16OP_MASK_MOVE32Z 0x7
760 #define MIPS16OP_SH_MOVE32Z 0
761 #define MIPS16OP_MASK_IMM6 0x3f
762 #define MIPS16OP_SH_IMM6 5
764 /* These are the characters which may appears in the args field of an
765 instruction. They appear in the order in which the fields appear
766 when the instruction is used. Commas and parentheses in the args
767 string are ignored when assembling, and written into the output
770 "y" 3 bit register (MIPS16OP_*_RY)
771 "x" 3 bit register (MIPS16OP_*_RX)
772 "z" 3 bit register (MIPS16OP_*_RZ)
773 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
774 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
775 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
776 "0" zero register ($0)
777 "S" stack pointer ($sp or $29)
779 "R" return address register ($ra or $31)
780 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
781 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
782 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
783 "a" 26 bit jump address
784 "e" 11 bit extension value
785 "l" register list for entry instruction
786 "L" register list for exit instruction
788 The remaining codes may be extended. Except as otherwise noted,
789 the full extended operand is a 16 bit signed value.
790 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
791 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
792 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
793 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
794 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
795 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
796 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
797 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
798 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
799 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
800 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
801 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
802 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
803 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
804 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
805 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
806 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
807 "q" 11 bit branch address (MIPS16OP_*_IMM11)
808 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
809 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
810 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
813 /* For the mips16, we use the same opcode table format and a few of
814 the same flags. However, most of the flags are different. */
816 /* Modifies the register in MIPS16OP_*_RX. */
817 #define MIPS16_INSN_WRITE_X 0x00000001
818 /* Modifies the register in MIPS16OP_*_RY. */
819 #define MIPS16_INSN_WRITE_Y 0x00000002
820 /* Modifies the register in MIPS16OP_*_RZ. */
821 #define MIPS16_INSN_WRITE_Z 0x00000004
822 /* Modifies the T ($24) register. */
823 #define MIPS16_INSN_WRITE_T 0x00000008
824 /* Modifies the SP ($29) register. */
825 #define MIPS16_INSN_WRITE_SP 0x00000010
826 /* Modifies the RA ($31) register. */
827 #define MIPS16_INSN_WRITE_31 0x00000020
828 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
829 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
830 /* Reads the register in MIPS16OP_*_RX. */
831 #define MIPS16_INSN_READ_X 0x00000080
832 /* Reads the register in MIPS16OP_*_RY. */
833 #define MIPS16_INSN_READ_Y 0x00000100
834 /* Reads the register in MIPS16OP_*_MOVE32Z. */
835 #define MIPS16_INSN_READ_Z 0x00000200
836 /* Reads the T ($24) register. */
837 #define MIPS16_INSN_READ_T 0x00000400
838 /* Reads the SP ($29) register. */
839 #define MIPS16_INSN_READ_SP 0x00000800
840 /* Reads the RA ($31) register. */
841 #define MIPS16_INSN_READ_31 0x00001000
842 /* Reads the program counter. */
843 #define MIPS16_INSN_READ_PC 0x00002000
844 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
845 #define MIPS16_INSN_READ_GPR_X 0x00004000
846 /* Is a branch insn. */
847 #define MIPS16_INSN_BRANCH 0x00010000
849 /* The following flags have the same value for the mips16 opcode
851 INSN_UNCOND_BRANCH_DELAY
852 INSN_COND_BRANCH_DELAY
853 INSN_COND_BRANCH_LIKELY (never used)
862 extern const struct mips_opcode mips16_opcodes
[];
863 extern const int bfd_mips16_num_opcodes
;
865 #endif /* _MIPS_H_ */