1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
8 This file is part of GDB, GAS, and the GNU binutils.
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version
13 1, or (at your option) any later version.
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
27 /* These are bit masks and shift counts to use to access the various
28 fields of an instruction. To retrieve the X field of an
29 instruction, use the expression
30 (i >> OP_SH_X) & OP_MASK_X
31 To set the same field (to j), use
32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
34 Make sure you use fields that are appropriate for the instruction,
37 The 'i' format uses OP, RS, RT and IMMEDIATE.
39 The 'j' format uses OP and TARGET.
41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
43 The 'b' format uses OP, RS, RT and DELTA.
45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
50 breakpoint instruction are not defined; Kane says the breakpoint
51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
52 only use ten bits). An optional two-operand form of break/sdbbp
53 allows the lower ten bits to be set too, and MIPS32 and later
54 architectures allow 20 bits to be set with a signal operand
57 The syscall instruction uses CODE20.
59 The general coprocessor instructions use COPZ. */
61 #define OP_MASK_OP 0x3f
63 #define OP_MASK_RS 0x1f
65 #define OP_MASK_FR 0x1f
67 #define OP_MASK_FMT 0x1f
69 #define OP_MASK_BCC 0x7
71 #define OP_MASK_CODE 0x3ff
73 #define OP_MASK_CODE2 0x3ff
75 #define OP_MASK_RT 0x1f
77 #define OP_MASK_FT 0x1f
79 #define OP_MASK_CACHE 0x1f
80 #define OP_SH_CACHE 16
81 #define OP_MASK_RD 0x1f
83 #define OP_MASK_FS 0x1f
85 #define OP_MASK_PREFX 0x1f
86 #define OP_SH_PREFX 11
87 #define OP_MASK_CCC 0x7
89 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
90 #define OP_SH_CODE20 6
91 #define OP_MASK_SHAMT 0x1f
93 #define OP_MASK_FD 0x1f
95 #define OP_MASK_TARGET 0x3ffffff
96 #define OP_SH_TARGET 0
97 #define OP_MASK_COPZ 0x1ffffff
99 #define OP_MASK_IMMEDIATE 0xffff
100 #define OP_SH_IMMEDIATE 0
101 #define OP_MASK_DELTA 0xffff
102 #define OP_SH_DELTA 0
103 #define OP_MASK_FUNCT 0x3f
104 #define OP_SH_FUNCT 0
105 #define OP_MASK_SPEC 0x3f
107 #define OP_SH_LOCC 8 /* FP condition code. */
108 #define OP_SH_HICC 18 /* FP condition code. */
109 #define OP_MASK_CC 0x7
110 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
111 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
112 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
113 #define OP_MASK_COP1SPEC 0xf
114 #define OP_MASK_COP1SCLR 0x4
115 #define OP_MASK_COP1CMP 0x3
116 #define OP_SH_COP1CMP 4
117 #define OP_SH_FORMAT 21 /* FP short format field. */
118 #define OP_MASK_FORMAT 0x7
119 #define OP_SH_TRUE 16
120 #define OP_MASK_TRUE 0x1
122 #define OP_MASK_GE 0x01
123 #define OP_SH_UNSIGNED 16
124 #define OP_MASK_UNSIGNED 0x1
125 #define OP_SH_HINT 16
126 #define OP_MASK_HINT 0x1f
127 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
128 #define OP_MASK_MMI 0x3f
129 #define OP_SH_MMISUB 6
130 #define OP_MASK_MMISUB 0x1f
131 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
132 #define OP_SH_PERFREG 1
133 #define OP_SH_SEL 0 /* Coprocessor select field. */
134 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
135 #define OP_SH_CODE19 6 /* 19 bit wait code. */
136 #define OP_MASK_CODE19 0x7ffff
138 #define OP_MASK_ALN 0x7
139 #define OP_SH_VSEL 21
140 #define OP_MASK_VSEL 0x1f
141 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
142 but 0x8-0xf don't select bytes. */
143 #define OP_SH_VECBYTE 22
144 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
145 #define OP_SH_VECALIGN 21
146 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
147 #define OP_SH_INSMSB 11
148 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
149 #define OP_SH_EXTMSBD 11
152 #define OP_SH_DSPACC 11
153 #define OP_MASK_DSPACC 0x3
154 #define OP_SH_DSPACC_S 21
155 #define OP_MASK_DSPACC_S 0x3
156 #define OP_SH_DSPSFT 20
157 #define OP_MASK_DSPSFT 0x3f
158 #define OP_SH_DSPSFT_7 19
159 #define OP_MASK_DSPSFT_7 0x7f
161 #define OP_MASK_SA3 0x7
163 #define OP_MASK_SA4 0xf
164 #define OP_SH_IMM8 16
165 #define OP_MASK_IMM8 0xff
166 #define OP_SH_IMM10 16
167 #define OP_MASK_IMM10 0x3ff
168 #define OP_SH_WRDSP 11
169 #define OP_MASK_WRDSP 0x3f
170 #define OP_SH_RDDSP 16
171 #define OP_MASK_RDDSP 0x3f
173 #define OP_OP_COP0 0x10
174 #define OP_OP_COP1 0x11
175 #define OP_OP_COP2 0x12
176 #define OP_OP_COP3 0x13
177 #define OP_OP_LWC1 0x31
178 #define OP_OP_LWC2 0x32
179 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
180 #define OP_OP_LDC1 0x35
181 #define OP_OP_LDC2 0x36
182 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
183 #define OP_OP_SWC1 0x39
184 #define OP_OP_SWC2 0x3a
185 #define OP_OP_SWC3 0x3b
186 #define OP_OP_SDC1 0x3d
187 #define OP_OP_SDC2 0x3e
188 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
190 /* Values in the 'VSEL' field. */
191 #define MDMX_FMTSEL_IMM_QH 0x1d
192 #define MDMX_FMTSEL_IMM_OB 0x1e
193 #define MDMX_FMTSEL_VEC_QH 0x15
194 #define MDMX_FMTSEL_VEC_OB 0x16
196 /* This structure holds information for a particular instruction. */
200 /* The name of the instruction. */
202 /* A string describing the arguments for this instruction. */
204 /* The basic opcode for the instruction. When assembling, this
205 opcode is modified by the arguments to produce the actual opcode
206 that is used. If pinfo is INSN_MACRO, then this is 0. */
208 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
209 relevant portions of the opcode when disassembling. If the
210 actual opcode anded with the match field equals the opcode field,
211 then we have found the correct instruction. If pinfo is
212 INSN_MACRO, then this field is the macro identifier. */
214 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
215 of bits describing the instruction, notably any relevant hazard
218 /* A collection of additional bits describing the instruction. */
219 unsigned long pinfo2
;
220 /* A collection of bits describing the instruction sets of which this
221 instruction or macro is a member. */
222 unsigned long membership
;
225 /* These are the characters which may appear in the args field of an
226 instruction. They appear in the order in which the fields appear
227 when the instruction is used. Commas and parentheses in the args
228 string are ignored when assembling, and written into the output
231 Each of these characters corresponds to a mask field defined above.
233 "<" 5 bit shift amount (OP_*_SHAMT)
234 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
235 "a" 26 bit target address (OP_*_TARGET)
236 "b" 5 bit base register (OP_*_RS)
237 "c" 10 bit breakpoint code (OP_*_CODE)
238 "d" 5 bit destination register specifier (OP_*_RD)
239 "h" 5 bit prefx hint (OP_*_PREFX)
240 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
241 "j" 16 bit signed immediate (OP_*_DELTA)
242 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
243 Also used for immediate operands in vr5400 vector insns.
244 "o" 16 bit signed offset (OP_*_DELTA)
245 "p" 16 bit PC relative branch target address (OP_*_DELTA)
246 "q" 10 bit extra breakpoint code (OP_*_CODE2)
247 "r" 5 bit same register used as both source and target (OP_*_RS)
248 "s" 5 bit source register specifier (OP_*_RS)
249 "t" 5 bit target register (OP_*_RT)
250 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
251 "v" 5 bit same register used as both source and destination (OP_*_RS)
252 "w" 5 bit same register used as both target and destination (OP_*_RT)
253 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
254 (used by clo and clz)
255 "C" 25 bit coprocessor function code (OP_*_COPZ)
256 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
257 "J" 19 bit wait function code (OP_*_CODE19)
258 "x" accept and ignore register name
259 "z" must be zero register
260 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
261 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
262 Enforces: 0 <= pos < 32.
263 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
264 Requires that "+A" or "+E" occur first to set position.
265 Enforces: 0 < (pos+size) <= 32.
266 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
267 Requires that "+A" or "+E" occur first to set position.
268 Enforces: 0 < (pos+size) <= 32.
269 (Also used by "dext" w/ different limits, but limits for
270 that are checked by the M_DEXT macro.)
271 "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
272 Enforces: 32 <= pos < 64.
273 "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
274 Requires that "+A" or "+E" occur first to set position.
275 Enforces: 32 < (pos+size) <= 64.
276 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
277 Requires that "+A" or "+E" occur first to set position.
278 Enforces: 32 < (pos+size) <= 64.
279 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
280 Requires that "+A" or "+E" occur first to set position.
281 Enforces: 32 < (pos+size) <= 64.
283 Floating point instructions:
284 "D" 5 bit destination register (OP_*_FD)
285 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
286 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
287 "S" 5 bit fs source 1 register (OP_*_FS)
288 "T" 5 bit ft source 2 register (OP_*_FT)
289 "R" 5 bit fr source 3 register (OP_*_FR)
290 "V" 5 bit same register used as floating source and destination (OP_*_FS)
291 "W" 5 bit same register used as floating target and destination (OP_*_FT)
293 Coprocessor instructions:
294 "E" 5 bit target register (OP_*_RT)
295 "G" 5 bit destination register (OP_*_RD)
296 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
297 "P" 5 bit performance-monitor register (OP_*_PERFREG)
298 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
299 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
301 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
302 for pretty-printing in disassembly only.
305 "A" General 32 bit expression
306 "I" 32 bit immediate (value placed in imm_expr).
307 "+I" 32 bit immediate (value placed in imm2_expr).
308 "F" 64 bit floating point constant in .rdata
309 "L" 64 bit floating point constant in .lit8
310 "f" 32 bit floating point constant
311 "l" 32 bit floating point constant in .lit4
313 MDMX instruction operands (note that while these use the FP register
314 fields, they accept both $fN and $vN names for the registers):
315 "O" MDMX alignment offset (OP_*_ALN)
316 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
317 "X" MDMX destination register (OP_*_FD)
318 "Y" MDMX source register (OP_*_FS)
319 "Z" MDMX source register (OP_*_FT)
322 "3" 3 bit unsigned immediate (OP_*_SA3)
323 "4" 4 bit unsigned immediate (OP_*_SA4)
324 "5" 8 bit unsigned immediate (OP_*_IMM8)
325 "6" 5 bit unsigned immediate (OP_*_RS)
326 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
327 "8" 6 bit unsigned immediate (OP_*_WRDSP)
328 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
329 "0" 6 bit signed immediate (OP_*_DSPSFT)
330 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
331 "'" 6 bit unsigned immediate (OP_*_RDDSP)
332 "@" 10 bit signed immediate (OP_*_IMM10)
335 "()" parens surrounding optional value
336 "," separates operands
337 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
338 "+" Start of extension sequence.
340 Characters used so far, for quick reference when adding more:
343 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
344 "abcdefhijklopqrstuvwxz"
346 Extension character sequences used so far ("+" followed by the
347 following), for quick reference when adding more:
351 /* These are the bits which may be set in the pinfo field of an
352 instructions, if it is not equal to INSN_MACRO. */
354 /* Modifies the general purpose register in OP_*_RD. */
355 #define INSN_WRITE_GPR_D 0x00000001
356 /* Modifies the general purpose register in OP_*_RT. */
357 #define INSN_WRITE_GPR_T 0x00000002
358 /* Modifies general purpose register 31. */
359 #define INSN_WRITE_GPR_31 0x00000004
360 /* Modifies the floating point register in OP_*_FD. */
361 #define INSN_WRITE_FPR_D 0x00000008
362 /* Modifies the floating point register in OP_*_FS. */
363 #define INSN_WRITE_FPR_S 0x00000010
364 /* Modifies the floating point register in OP_*_FT. */
365 #define INSN_WRITE_FPR_T 0x00000020
366 /* Reads the general purpose register in OP_*_RS. */
367 #define INSN_READ_GPR_S 0x00000040
368 /* Reads the general purpose register in OP_*_RT. */
369 #define INSN_READ_GPR_T 0x00000080
370 /* Reads the floating point register in OP_*_FS. */
371 #define INSN_READ_FPR_S 0x00000100
372 /* Reads the floating point register in OP_*_FT. */
373 #define INSN_READ_FPR_T 0x00000200
374 /* Reads the floating point register in OP_*_FR. */
375 #define INSN_READ_FPR_R 0x00000400
376 /* Modifies coprocessor condition code. */
377 #define INSN_WRITE_COND_CODE 0x00000800
378 /* Reads coprocessor condition code. */
379 #define INSN_READ_COND_CODE 0x00001000
381 #define INSN_TLB 0x00002000
382 /* Reads coprocessor register other than floating point register. */
383 #define INSN_COP 0x00004000
384 /* Instruction loads value from memory, requiring delay. */
385 #define INSN_LOAD_MEMORY_DELAY 0x00008000
386 /* Instruction loads value from coprocessor, requiring delay. */
387 #define INSN_LOAD_COPROC_DELAY 0x00010000
388 /* Instruction has unconditional branch delay slot. */
389 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
390 /* Instruction has conditional branch delay slot. */
391 #define INSN_COND_BRANCH_DELAY 0x00040000
392 /* Conditional branch likely: if branch not taken, insn nullified. */
393 #define INSN_COND_BRANCH_LIKELY 0x00080000
394 /* Moves to coprocessor register, requiring delay. */
395 #define INSN_COPROC_MOVE_DELAY 0x00100000
396 /* Loads coprocessor register from memory, requiring delay. */
397 #define INSN_COPROC_MEMORY_DELAY 0x00200000
398 /* Reads the HI register. */
399 #define INSN_READ_HI 0x00400000
400 /* Reads the LO register. */
401 #define INSN_READ_LO 0x00800000
402 /* Modifies the HI register. */
403 #define INSN_WRITE_HI 0x01000000
404 /* Modifies the LO register. */
405 #define INSN_WRITE_LO 0x02000000
406 /* Takes a trap (easier to keep out of delay slot). */
407 #define INSN_TRAP 0x04000000
408 /* Instruction stores value into memory. */
409 #define INSN_STORE_MEMORY 0x08000000
410 /* Instruction uses single precision floating point. */
411 #define FP_S 0x10000000
412 /* Instruction uses double precision floating point. */
413 #define FP_D 0x20000000
414 /* Instruction is part of the tx39's integer multiply family. */
415 #define INSN_MULT 0x40000000
416 /* Instruction synchronize shared memory. */
417 #define INSN_SYNC 0x80000000
419 /* These are the bits which may be set in the pinfo2 field of an
422 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
423 #define INSN2_ALIAS 0x00000001
424 /* Instruction reads MDMX accumulator. */
425 #define INSN2_READ_MDMX_ACC 0x00000002
426 /* Instruction writes MDMX accumulator. */
427 #define INSN2_WRITE_MDMX_ACC 0x00000004
429 /* Instruction is actually a macro. It should be ignored by the
430 disassembler, and requires special treatment by the assembler. */
431 #define INSN_MACRO 0xffffffff
433 /* Masks used to mark instructions to indicate which MIPS ISA level
434 they were introduced in. ISAs, as defined below, are logical
435 ORs of these bits, indicating that they support the instructions
436 defined at the given level. */
438 #define INSN_ISA_MASK 0x00000fff
439 #define INSN_ISA1 0x00000001
440 #define INSN_ISA2 0x00000002
441 #define INSN_ISA3 0x00000004
442 #define INSN_ISA4 0x00000008
443 #define INSN_ISA5 0x00000010
444 #define INSN_ISA32 0x00000020
445 #define INSN_ISA64 0x00000040
446 #define INSN_ISA32R2 0x00000080
447 #define INSN_ISA64R2 0x00000100
449 /* Masks used for MIPS-defined ASEs. */
450 #define INSN_ASE_MASK 0x0000f000
453 #define INSN_DSP 0x00001000
455 #define INSN_MIPS16 0x00002000
457 #define INSN_MIPS3D 0x00004000
459 #define INSN_MDMX 0x00008000
461 /* Chip specific instructions. These are bitmasks. */
463 /* MIPS R4650 instruction. */
464 #define INSN_4650 0x00010000
465 /* LSI R4010 instruction. */
466 #define INSN_4010 0x00020000
467 /* NEC VR4100 instruction. */
468 #define INSN_4100 0x00040000
469 /* Toshiba R3900 instruction. */
470 #define INSN_3900 0x00080000
471 /* MIPS R10000 instruction. */
472 #define INSN_10000 0x00100000
473 /* Broadcom SB-1 instruction. */
474 #define INSN_SB1 0x00200000
475 /* NEC VR4111/VR4181 instruction. */
476 #define INSN_4111 0x00400000
477 /* NEC VR4120 instruction. */
478 #define INSN_4120 0x00800000
479 /* NEC VR5400 instruction. */
480 #define INSN_5400 0x01000000
481 /* NEC VR5500 instruction. */
482 #define INSN_5500 0x02000000
484 /* MIPS ISA defines, use instead of hardcoding ISA level. */
486 #define ISA_UNKNOWN 0 /* Gas internal use. */
487 #define ISA_MIPS1 (INSN_ISA1)
488 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
489 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
490 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
491 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
493 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
494 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
496 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
497 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
500 /* CPU defines, use instead of hardcoding processor number. Keep this
501 in sync with bfd/archures.c in order for machine selection to work. */
502 #define CPU_UNKNOWN 0 /* Gas internal use. */
503 #define CPU_R3000 3000
504 #define CPU_R3900 3900
505 #define CPU_R4000 4000
506 #define CPU_R4010 4010
507 #define CPU_VR4100 4100
508 #define CPU_R4111 4111
509 #define CPU_VR4120 4120
510 #define CPU_R4300 4300
511 #define CPU_R4400 4400
512 #define CPU_R4600 4600
513 #define CPU_R4650 4650
514 #define CPU_R5000 5000
515 #define CPU_VR5400 5400
516 #define CPU_VR5500 5500
517 #define CPU_R6000 6000
518 #define CPU_RM7000 7000
519 #define CPU_R8000 8000
520 #define CPU_RM9000 9000
521 #define CPU_R10000 10000
522 #define CPU_R12000 12000
523 #define CPU_MIPS16 16
524 #define CPU_MIPS32 32
525 #define CPU_MIPS32R2 33
527 #define CPU_MIPS64 64
528 #define CPU_MIPS64R2 65
529 #define CPU_SB1 12310201 /* octal 'SB', 01. */
531 /* Test for membership in an ISA including chip specific ISAs. INSN
532 is pointer to an element of the opcode table; ISA is the specified
533 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
534 test, or zero if no CPU specific ISA test is desired. */
536 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
537 (((insn)->membership & isa) != 0 \
538 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
539 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
540 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
541 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
542 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
543 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
544 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
545 && ((insn)->membership & INSN_10000) != 0) \
546 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
547 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
548 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
549 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
550 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
551 || 0) /* Please keep this term for easier source merging. */
553 /* This is a list of macro expanded instructions.
555 _I appended means immediate
556 _A appended means address
557 _AB appended means address with base register
558 _D appended means 64 bit floating point constant
559 _S appended means 32 bit floating point constant. */
786 /* The order of overloaded instructions matters. Label arguments and
787 register arguments look the same. Instructions that can have either
788 for arguments must apear in the correct order in this table for the
789 assembler to pick the right one. In other words, entries with
790 immediate operands must apear after the same instruction with
793 Many instructions are short hand for other instructions (i.e., The
794 jal <register> instruction is short for jalr <register>). */
796 extern const struct mips_opcode mips_builtin_opcodes
[];
797 extern const int bfd_mips_num_builtin_opcodes
;
798 extern struct mips_opcode
*mips_opcodes
;
799 extern int bfd_mips_num_opcodes
;
800 #define NUMOPCODES bfd_mips_num_opcodes
803 /* The rest of this file adds definitions for the mips16 TinyRISC
806 /* These are the bitmasks and shift counts used for the different
807 fields in the instruction formats. Other than OP, no masks are
808 provided for the fixed portions of an instruction, since they are
811 The I format uses IMM11.
813 The RI format uses RX and IMM8.
815 The RR format uses RX, and RY.
817 The RRI format uses RX, RY, and IMM5.
819 The RRR format uses RX, RY, and RZ.
821 The RRI_A format uses RX, RY, and IMM4.
823 The SHIFT format uses RX, RY, and SHAMT.
825 The I8 format uses IMM8.
827 The I8_MOVR32 format uses RY and REGR32.
829 The IR_MOV32R format uses REG32R and MOV32Z.
831 The I64 format uses IMM8.
833 The RI64 format uses RY and IMM5.
836 #define MIPS16OP_MASK_OP 0x1f
837 #define MIPS16OP_SH_OP 11
838 #define MIPS16OP_MASK_IMM11 0x7ff
839 #define MIPS16OP_SH_IMM11 0
840 #define MIPS16OP_MASK_RX 0x7
841 #define MIPS16OP_SH_RX 8
842 #define MIPS16OP_MASK_IMM8 0xff
843 #define MIPS16OP_SH_IMM8 0
844 #define MIPS16OP_MASK_RY 0x7
845 #define MIPS16OP_SH_RY 5
846 #define MIPS16OP_MASK_IMM5 0x1f
847 #define MIPS16OP_SH_IMM5 0
848 #define MIPS16OP_MASK_RZ 0x7
849 #define MIPS16OP_SH_RZ 2
850 #define MIPS16OP_MASK_IMM4 0xf
851 #define MIPS16OP_SH_IMM4 0
852 #define MIPS16OP_MASK_REGR32 0x1f
853 #define MIPS16OP_SH_REGR32 0
854 #define MIPS16OP_MASK_REG32R 0x1f
855 #define MIPS16OP_SH_REG32R 3
856 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
857 #define MIPS16OP_MASK_MOVE32Z 0x7
858 #define MIPS16OP_SH_MOVE32Z 0
859 #define MIPS16OP_MASK_IMM6 0x3f
860 #define MIPS16OP_SH_IMM6 5
862 /* These are the characters which may appears in the args field of an
863 instruction. They appear in the order in which the fields appear
864 when the instruction is used. Commas and parentheses in the args
865 string are ignored when assembling, and written into the output
868 "y" 3 bit register (MIPS16OP_*_RY)
869 "x" 3 bit register (MIPS16OP_*_RX)
870 "z" 3 bit register (MIPS16OP_*_RZ)
871 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
872 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
873 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
874 "0" zero register ($0)
875 "S" stack pointer ($sp or $29)
877 "R" return address register ($ra or $31)
878 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
879 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
880 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
881 "a" 26 bit jump address
882 "e" 11 bit extension value
883 "l" register list for entry instruction
884 "L" register list for exit instruction
886 The remaining codes may be extended. Except as otherwise noted,
887 the full extended operand is a 16 bit signed value.
888 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
889 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
890 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
891 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
892 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
893 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
894 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
895 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
896 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
897 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
898 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
899 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
900 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
901 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
902 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
903 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
904 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
905 "q" 11 bit branch address (MIPS16OP_*_IMM11)
906 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
907 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
908 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
911 /* For the mips16, we use the same opcode table format and a few of
912 the same flags. However, most of the flags are different. */
914 /* Modifies the register in MIPS16OP_*_RX. */
915 #define MIPS16_INSN_WRITE_X 0x00000001
916 /* Modifies the register in MIPS16OP_*_RY. */
917 #define MIPS16_INSN_WRITE_Y 0x00000002
918 /* Modifies the register in MIPS16OP_*_RZ. */
919 #define MIPS16_INSN_WRITE_Z 0x00000004
920 /* Modifies the T ($24) register. */
921 #define MIPS16_INSN_WRITE_T 0x00000008
922 /* Modifies the SP ($29) register. */
923 #define MIPS16_INSN_WRITE_SP 0x00000010
924 /* Modifies the RA ($31) register. */
925 #define MIPS16_INSN_WRITE_31 0x00000020
926 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
927 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
928 /* Reads the register in MIPS16OP_*_RX. */
929 #define MIPS16_INSN_READ_X 0x00000080
930 /* Reads the register in MIPS16OP_*_RY. */
931 #define MIPS16_INSN_READ_Y 0x00000100
932 /* Reads the register in MIPS16OP_*_MOVE32Z. */
933 #define MIPS16_INSN_READ_Z 0x00000200
934 /* Reads the T ($24) register. */
935 #define MIPS16_INSN_READ_T 0x00000400
936 /* Reads the SP ($29) register. */
937 #define MIPS16_INSN_READ_SP 0x00000800
938 /* Reads the RA ($31) register. */
939 #define MIPS16_INSN_READ_31 0x00001000
940 /* Reads the program counter. */
941 #define MIPS16_INSN_READ_PC 0x00002000
942 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
943 #define MIPS16_INSN_READ_GPR_X 0x00004000
944 /* Is a branch insn. */
945 #define MIPS16_INSN_BRANCH 0x00010000
947 /* The following flags have the same value for the mips16 opcode
949 INSN_UNCOND_BRANCH_DELAY
950 INSN_COND_BRANCH_DELAY
951 INSN_COND_BRANCH_LIKELY (never used)
960 extern const struct mips_opcode mips16_opcodes
[];
961 extern const int bfd_mips16_num_opcodes
;
963 #endif /* _MIPS_H_ */