include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   3    2003, 2004, 2005, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5    Contributed by Ralph Campbell and OSF
   6    Commented and modified by Ian Lance Taylor, Cygnus Support
   7
   8    This file is part of GDB, GAS, and the GNU binutils.
   9
  10    GDB, GAS, and the GNU binutils are free software; you can redistribute
  11    them and/or modify them under the terms of the GNU General Public
  12    License as published by the Free Software Foundation; either version 3,
  13    or (at your option) any later version.
  14
  15    GDB, GAS, and the GNU binutils are distributed in the hope that they
  16    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  17    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  18    the GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this file; see the file COPYING3.  If not, write to the Free
  22    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  23    MA 02110-1301, USA.  */
  24
  25 #ifndef _MIPS_H_
  26 #define _MIPS_H_
  27
  28 /* These are bit masks and shift counts to use to access the various
  29    fields of an instruction.  To retrieve the X field of an
  30    instruction, use the expression
  31         (i >> OP_SH_X) & OP_MASK_X
  32    To set the same field (to j), use
  33         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  34
  35    Make sure you use fields that are appropriate for the instruction,
  36    of course.
  37
  38    The 'i' format uses OP, RS, RT and IMMEDIATE.
  39
  40    The 'j' format uses OP and TARGET.
  41
  42    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  43
  44    The 'b' format uses OP, RS, RT and DELTA.
  45
  46    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  47
  48    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  49
  50    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  51    breakpoint instruction are not defined; Kane says the breakpoint
  52    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  53    only use ten bits).  An optional two-operand form of break/sdbbp
  54    allows the lower ten bits to be set too, and MIPS32 and later
  55    architectures allow 20 bits to be set with a signal operand
  56    (using CODE20).
  57
  58    The syscall instruction uses CODE20.
  59
  60    The general coprocessor instructions use COPZ.  */
  61
  62 #define OP_MASK_OP              0x3f
  63 #define OP_SH_OP                26
  64 #define OP_MASK_RS              0x1f
  65 #define OP_SH_RS                21
  66 #define OP_MASK_FR              0x1f
  67 #define OP_SH_FR                21
  68 #define OP_MASK_FMT             0x1f
  69 #define OP_SH_FMT               21
  70 #define OP_MASK_BCC             0x7
  71 #define OP_SH_BCC               18
  72 #define OP_MASK_CODE            0x3ff
  73 #define OP_SH_CODE              16
  74 #define OP_MASK_CODE2           0x3ff
  75 #define OP_SH_CODE2             6
  76 #define OP_MASK_RT              0x1f
  77 #define OP_SH_RT                16
  78 #define OP_MASK_FT              0x1f
  79 #define OP_SH_FT                16
  80 #define OP_MASK_CACHE           0x1f
  81 #define OP_SH_CACHE             16
  82 #define OP_MASK_RD              0x1f
  83 #define OP_SH_RD                11
  84 #define OP_MASK_FS              0x1f
  85 #define OP_SH_FS                11
  86 #define OP_MASK_PREFX           0x1f
  87 #define OP_SH_PREFX             11
  88 #define OP_MASK_CCC             0x7
  89 #define OP_SH_CCC               8
  90 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  91 #define OP_SH_CODE20            6
  92 #define OP_MASK_SHAMT           0x1f
  93 #define OP_SH_SHAMT             6
  94 #define OP_MASK_FD              0x1f
  95 #define OP_SH_FD                6
  96 #define OP_MASK_TARGET          0x3ffffff
  97 #define OP_SH_TARGET            0
  98 #define OP_MASK_COPZ            0x1ffffff
  99 #define OP_SH_COPZ              0
 100 #define OP_MASK_IMMEDIATE       0xffff
 101 #define OP_SH_IMMEDIATE         0
 102 #define OP_MASK_DELTA           0xffff
 103 #define OP_SH_DELTA             0
 104 #define OP_MASK_FUNCT           0x3f
 105 #define OP_SH_FUNCT             0
 106 #define OP_MASK_SPEC            0x3f
 107 #define OP_SH_SPEC              0
 108 #define OP_SH_LOCC              8       /* FP condition code.  */
 109 #define OP_SH_HICC              18      /* FP condition code.  */
 110 #define OP_MASK_CC              0x7
 111 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 112 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 113 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 114 #define OP_MASK_COP1SPEC        0xf
 115 #define OP_MASK_COP1SCLR        0x4
 116 #define OP_MASK_COP1CMP         0x3
 117 #define OP_SH_COP1CMP           4
 118 #define OP_SH_FORMAT            21      /* FP short format field.  */
 119 #define OP_MASK_FORMAT          0x7
 120 #define OP_SH_TRUE              16
 121 #define OP_MASK_TRUE            0x1
 122 #define OP_SH_GE                17
 123 #define OP_MASK_GE              0x01
 124 #define OP_SH_UNSIGNED          16
 125 #define OP_MASK_UNSIGNED        0x1
 126 #define OP_SH_HINT              16
 127 #define OP_MASK_HINT            0x1f
 128 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 129 #define OP_MASK_MMI             0x3f
 130 #define OP_SH_MMISUB            6
 131 #define OP_MASK_MMISUB          0x1f
 132 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 133 #define OP_SH_PERFREG           1
 134 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 135 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 136 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 137 #define OP_MASK_CODE19          0x7ffff
 138 #define OP_SH_ALN               21
 139 #define OP_MASK_ALN             0x7
 140 #define OP_SH_VSEL              21
 141 #define OP_MASK_VSEL            0x1f
 142 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 143                                            but 0x8-0xf don't select bytes.  */
 144 #define OP_SH_VECBYTE           22
 145 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 146 #define OP_SH_VECALIGN          21
 147 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 148 #define OP_SH_INSMSB            11
 149 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 150 #define OP_SH_EXTMSBD           11
 151
 152 /* MIPS DSP ASE */
 153 #define OP_SH_DSPACC            11
 154 #define OP_MASK_DSPACC          0x3
 155 #define OP_SH_DSPACC_S          21
 156 #define OP_MASK_DSPACC_S        0x3
 157 #define OP_SH_DSPSFT            20
 158 #define OP_MASK_DSPSFT          0x3f
 159 #define OP_SH_DSPSFT_7          19
 160 #define OP_MASK_DSPSFT_7        0x7f
 161 #define OP_SH_SA3               21
 162 #define OP_MASK_SA3             0x7
 163 #define OP_SH_SA4               21
 164 #define OP_MASK_SA4             0xf
 165 #define OP_SH_IMM8              16
 166 #define OP_MASK_IMM8            0xff
 167 #define OP_SH_IMM10             16
 168 #define OP_MASK_IMM10           0x3ff
 169 #define OP_SH_WRDSP             11
 170 #define OP_MASK_WRDSP           0x3f
 171 #define OP_SH_RDDSP             16
 172 #define OP_MASK_RDDSP           0x3f
 173 #define OP_SH_BP                11
 174 #define OP_MASK_BP              0x3
 175
 176 /* MIPS MT ASE */
 177 #define OP_SH_MT_U              5
 178 #define OP_MASK_MT_U            0x1
 179 #define OP_SH_MT_H              4
 180 #define OP_MASK_MT_H            0x1
 181 #define OP_SH_MTACC_T           18
 182 #define OP_MASK_MTACC_T         0x3
 183 #define OP_SH_MTACC_D           13
 184 #define OP_MASK_MTACC_D         0x3
 185
 186 #define OP_OP_COP0              0x10
 187 #define OP_OP_COP1              0x11
 188 #define OP_OP_COP2              0x12
 189 #define OP_OP_COP3              0x13
 190 #define OP_OP_LWC1              0x31
 191 #define OP_OP_LWC2              0x32
 192 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 193 #define OP_OP_LDC1              0x35
 194 #define OP_OP_LDC2              0x36
 195 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 196 #define OP_OP_SWC1              0x39
 197 #define OP_OP_SWC2              0x3a
 198 #define OP_OP_SWC3              0x3b
 199 #define OP_OP_SDC1              0x3d
 200 #define OP_OP_SDC2              0x3e
 201 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 202
 203 /* Values in the 'VSEL' field.  */
 204 #define MDMX_FMTSEL_IMM_QH      0x1d
 205 #define MDMX_FMTSEL_IMM_OB      0x1e
 206 #define MDMX_FMTSEL_VEC_QH      0x15
 207 #define MDMX_FMTSEL_VEC_OB      0x16
 208
 209 /* UDI */
 210 #define OP_SH_UDI1              6
 211 #define OP_MASK_UDI1            0x1f
 212 #define OP_SH_UDI2              6
 213 #define OP_MASK_UDI2            0x3ff
 214 #define OP_SH_UDI3              6
 215 #define OP_MASK_UDI3            0x7fff
 216 #define OP_SH_UDI4              6
 217 #define OP_MASK_UDI4            0xfffff
 218
 219 /* Octeon */
 220 #define OP_SH_BBITIND           16
 221 #define OP_MASK_BBITIND         0x1f
 222 #define OP_SH_CINSPOS           6
 223 #define OP_MASK_CINSPOS         0x1f
 224 #define OP_SH_CINSLM1           11
 225 #define OP_MASK_CINSLM1         0x1f
 226 #define OP_SH_SEQI              6
 227 #define OP_MASK_SEQI            0x3ff
 228
 229 /* This structure holds information for a particular instruction.  */
 230
 231 struct mips_opcode
 232 {
 233   /* The name of the instruction.  */
 234   const char *name;
 235   /* A string describing the arguments for this instruction.  */
 236   const char *args;
 237   /* The basic opcode for the instruction.  When assembling, this
 238      opcode is modified by the arguments to produce the actual opcode
 239      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 240   unsigned long match;
 241   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 242      relevant portions of the opcode when disassembling.  If the
 243      actual opcode anded with the match field equals the opcode field,
 244      then we have found the correct instruction.  If pinfo is
 245      INSN_MACRO, then this field is the macro identifier.  */
 246   unsigned long mask;
 247   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 248      of bits describing the instruction, notably any relevant hazard
 249      information.  */
 250   unsigned long pinfo;
 251   /* A collection of additional bits describing the instruction. */
 252   unsigned long pinfo2;
 253   /* A collection of bits describing the instruction sets of which this
 254      instruction or macro is a member. */
 255   unsigned long membership;
 256 };
 257
 258 /* These are the characters which may appear in the args field of an
 259    instruction.  They appear in the order in which the fields appear
 260    when the instruction is used.  Commas and parentheses in the args
 261    string are ignored when assembling, and written into the output
 262    when disassembling.
 263
 264    Each of these characters corresponds to a mask field defined above.
 265
 266    "1" 5 bit sync type (OP_*_SHAMT)
 267    "<" 5 bit shift amount (OP_*_SHAMT)
 268    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 269    "a" 26 bit target address (OP_*_TARGET)
 270    "b" 5 bit base register (OP_*_RS)
 271    "c" 10 bit breakpoint code (OP_*_CODE)
 272    "d" 5 bit destination register specifier (OP_*_RD)
 273    "h" 5 bit prefx hint (OP_*_PREFX)
 274    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 275    "j" 16 bit signed immediate (OP_*_DELTA)
 276    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 277        Also used for immediate operands in vr5400 vector insns.
 278    "o" 16 bit signed offset (OP_*_DELTA)
 279    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 280    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 281    "r" 5 bit same register used as both source and target (OP_*_RS)
 282    "s" 5 bit source register specifier (OP_*_RS)
 283    "t" 5 bit target register (OP_*_RT)
 284    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 285    "v" 5 bit same register used as both source and destination (OP_*_RS)
 286    "w" 5 bit same register used as both target and destination (OP_*_RT)
 287    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 288        (used by clo and clz)
 289    "C" 25 bit coprocessor function code (OP_*_COPZ)
 290    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 291    "J" 19 bit wait function code (OP_*_CODE19)
 292    "x" accept and ignore register name
 293    "z" must be zero register
 294    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 295    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 296         LSB (OP_*_SHAMT).
 297         Enforces: 0 <= pos < 32.
 298    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 299         Requires that "+A" or "+E" occur first to set position.
 300         Enforces: 0 < (pos+size) <= 32.
 301    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 302         Requires that "+A" or "+E" occur first to set position.
 303         Enforces: 0 < (pos+size) <= 32.
 304         (Also used by "dext" w/ different limits, but limits for
 305         that are checked by the M_DEXT macro.)
 306    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 307         Enforces: 32 <= pos < 64.
 308    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 309         Requires that "+A" or "+E" occur first to set position.
 310         Enforces: 32 < (pos+size) <= 64.
 311    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 312         Requires that "+A" or "+E" occur first to set position.
 313         Enforces: 32 < (pos+size) <= 64.
 314    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 315         Requires that "+A" or "+E" occur first to set position.
 316         Enforces: 32 < (pos+size) <= 64.
 317
 318    Floating point instructions:
 319    "D" 5 bit destination register (OP_*_FD)
 320    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 321    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 322    "S" 5 bit fs source 1 register (OP_*_FS)
 323    "T" 5 bit ft source 2 register (OP_*_FT)
 324    "R" 5 bit fr source 3 register (OP_*_FR)
 325    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 326    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 327
 328    Coprocessor instructions:
 329    "E" 5 bit target register (OP_*_RT)
 330    "G" 5 bit destination register (OP_*_RD)
 331    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 332    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 333    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 334    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 335    see also "k" above
 336    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 337         for pretty-printing in disassembly only.
 338
 339    Macro instructions:
 340    "A" General 32 bit expression
 341    "I" 32 bit immediate (value placed in imm_expr).
 342    "+I" 32 bit immediate (value placed in imm2_expr).
 343    "F" 64 bit floating point constant in .rdata
 344    "L" 64 bit floating point constant in .lit8
 345    "f" 32 bit floating point constant
 346    "l" 32 bit floating point constant in .lit4
 347
 348    MDMX instruction operands (note that while these use the FP register
 349    fields, they accept both $fN and $vN names for the registers):
 350    "O"  MDMX alignment offset (OP_*_ALN)
 351    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 352    "X"  MDMX destination register (OP_*_FD)
 353    "Y"  MDMX source register (OP_*_FS)
 354    "Z"  MDMX source register (OP_*_FT)
 355
 356    DSP ASE usage:
 357    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 358    "3" 3 bit unsigned immediate (OP_*_SA3)
 359    "4" 4 bit unsigned immediate (OP_*_SA4)
 360    "5" 8 bit unsigned immediate (OP_*_IMM8)
 361    "6" 5 bit unsigned immediate (OP_*_RS)
 362    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 363    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 364    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 365    "0" 6 bit signed immediate (OP_*_DSPSFT)
 366    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 367    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 368    "@" 10 bit signed immediate (OP_*_IMM10)
 369
 370    MT ASE usage:
 371    "!" 1 bit usermode flag (OP_*_MT_U)
 372    "$" 1 bit load high flag (OP_*_MT_H)
 373    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 374    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 375    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 376    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 377    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 378
 379    UDI immediates:
 380    "+1" UDI immediate bits 6-10
 381    "+2" UDI immediate bits 6-15
 382    "+3" UDI immediate bits 6-20
 383    "+4" UDI immediate bits 6-25
 384
 385    Octeon:
 386    "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
 387    "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
 388         otherwise skips to next candidate.
 389    "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
 390    "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
 391         32 <= pos < 64, otherwise skips to next candidate.
 392    "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
 393    "+s" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.
 394    "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
 395         cint32/exts32.  Enforces non-negative value and that
 396         pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
 397         position field is "+p" or "+P".
 398
 399    Other:
 400    "()" parens surrounding optional value
 401    ","  separates operands
 402    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 403    "+"  Start of extension sequence.
 404
 405    Characters used so far, for quick reference when adding more:
 406    "1234567890"
 407    "%[]<>(),+:'@!$*&"
 408    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 409    "abcdefghijklopqrstuvwxz"
 410
 411    Extension character sequences used so far ("+" followed by the
 412    following), for quick reference when adding more:
 413    "1234"
 414    "ABCDEFGHIPQSTX"
 415    "pstx"
 416 */
 417
 418 /* These are the bits which may be set in the pinfo field of an
 419    instructions, if it is not equal to INSN_MACRO.  */
 420
 421 /* Modifies the general purpose register in OP_*_RD.  */
 422 #define INSN_WRITE_GPR_D            0x00000001
 423 /* Modifies the general purpose register in OP_*_RT.  */
 424 #define INSN_WRITE_GPR_T            0x00000002
 425 /* Modifies general purpose register 31.  */
 426 #define INSN_WRITE_GPR_31           0x00000004
 427 /* Modifies the floating point register in OP_*_FD.  */
 428 #define INSN_WRITE_FPR_D            0x00000008
 429 /* Modifies the floating point register in OP_*_FS.  */
 430 #define INSN_WRITE_FPR_S            0x00000010
 431 /* Modifies the floating point register in OP_*_FT.  */
 432 #define INSN_WRITE_FPR_T            0x00000020
 433 /* Reads the general purpose register in OP_*_RS.  */
 434 #define INSN_READ_GPR_S             0x00000040
 435 /* Reads the general purpose register in OP_*_RT.  */
 436 #define INSN_READ_GPR_T             0x00000080
 437 /* Reads the floating point register in OP_*_FS.  */
 438 #define INSN_READ_FPR_S             0x00000100
 439 /* Reads the floating point register in OP_*_FT.  */
 440 #define INSN_READ_FPR_T             0x00000200
 441 /* Reads the floating point register in OP_*_FR.  */
 442 #define INSN_READ_FPR_R             0x00000400
 443 /* Modifies coprocessor condition code.  */
 444 #define INSN_WRITE_COND_CODE        0x00000800
 445 /* Reads coprocessor condition code.  */
 446 #define INSN_READ_COND_CODE         0x00001000
 447 /* TLB operation.  */
 448 #define INSN_TLB                    0x00002000
 449 /* Reads coprocessor register other than floating point register.  */
 450 #define INSN_COP                    0x00004000
 451 /* Instruction loads value from memory, requiring delay.  */
 452 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 453 /* Instruction loads value from coprocessor, requiring delay.  */
 454 #define INSN_LOAD_COPROC_DELAY      0x00010000
 455 /* Instruction has unconditional branch delay slot.  */
 456 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 457 /* Instruction has conditional branch delay slot.  */
 458 #define INSN_COND_BRANCH_DELAY      0x00040000
 459 /* Conditional branch likely: if branch not taken, insn nullified.  */
 460 #define INSN_COND_BRANCH_LIKELY     0x00080000
 461 /* Moves to coprocessor register, requiring delay.  */
 462 #define INSN_COPROC_MOVE_DELAY      0x00100000
 463 /* Loads coprocessor register from memory, requiring delay.  */
 464 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 465 /* Reads the HI register.  */
 466 #define INSN_READ_HI                0x00400000
 467 /* Reads the LO register.  */
 468 #define INSN_READ_LO                0x00800000
 469 /* Modifies the HI register.  */
 470 #define INSN_WRITE_HI               0x01000000
 471 /* Modifies the LO register.  */
 472 #define INSN_WRITE_LO               0x02000000
 473 /* Takes a trap (easier to keep out of delay slot).  */
 474 #define INSN_TRAP                   0x04000000
 475 /* Instruction stores value into memory.  */
 476 #define INSN_STORE_MEMORY           0x08000000
 477 /* Instruction uses single precision floating point.  */
 478 #define FP_S                        0x10000000
 479 /* Instruction uses double precision floating point.  */
 480 #define FP_D                        0x20000000
 481 /* Instruction is part of the tx39's integer multiply family.    */
 482 #define INSN_MULT                   0x40000000
 483 /* Instruction synchronize shared memory.  */
 484 #define INSN_SYNC                   0x80000000
 485 /* Instruction is actually a macro.  It should be ignored by the
 486    disassembler, and requires special treatment by the assembler.  */
 487 #define INSN_MACRO                  0xffffffff
 488
 489 /* These are the bits which may be set in the pinfo2 field of an
 490    instruction. */
 491
 492 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 493 #define INSN2_ALIAS                 0x00000001
 494 /* Instruction reads MDMX accumulator. */
 495 #define INSN2_READ_MDMX_ACC         0x00000002
 496 /* Instruction writes MDMX accumulator. */
 497 #define INSN2_WRITE_MDMX_ACC        0x00000004
 498 /* Macro uses single-precision floating-point instructions.  This should
 499    only be set for macros.  For instructions, FP_S in pinfo carries the
 500    same information.  */
 501 #define INSN2_M_FP_S                0x00000008
 502 /* Macro uses double-precision floating-point instructions.  This should
 503    only be set for macros.  For instructions, FP_D in pinfo carries the
 504    same information.  */
 505 #define INSN2_M_FP_D                0x00000010
 506
 507 /* Masks used to mark instructions to indicate which MIPS ISA level
 508    they were introduced in.  INSN_ISA_MASK masks an enumeration that
 509    specifies the base ISA level(s).  The remainder of a 32-bit
 510    word constructed using these macros is a bitmask of the remaining
 511    INSN_* values below.  */
 512
 513 #define INSN_ISA_MASK             0x0000000ful
 514
 515 /* We cannot start at zero due to ISA_UNKNOWN below.  */
 516 #define INSN_ISA1                 1
 517 #define INSN_ISA2                 2
 518 #define INSN_ISA3                 3
 519 #define INSN_ISA4                 4
 520 #define INSN_ISA5                 5
 521 #define INSN_ISA32                6
 522 #define INSN_ISA32R2              7
 523 #define INSN_ISA64                8
 524 #define INSN_ISA64R2              9
 525 /* Below this point the INSN_* values correspond to combinations of ISAs.
 526    They are only for use in the opcodes table to indicate membership of
 527    a combination of ISAs that cannot be expressed using the usual inclusion
 528    ordering on the above INSN_* values.  */
 529 #define INSN_ISA3_32              10
 530 #define INSN_ISA3_32R2            11
 531 #define INSN_ISA4_32              12
 532 #define INSN_ISA4_32R2            13
 533 #define INSN_ISA5_32R2            14
 534
 535 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
 536    INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
 537    this table describes whether at least one of the ISAs described by X
 538    is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
 539    a particular core and X as the ISA level(s) at which a certain instruction
 540    is defined.)  The ISA(s) described by X is/are implemented by Y iff
 541    (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
 542    is non-zero.  */
 543 static const unsigned int mips_isa_table[] =
 544   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 545
 546 /* Masks used for Chip specific instructions.  */
 547 #define INSN_CHIP_MASK            0xc3ff0820
 548
 549 /* Cavium Networks Octeon instructions.  */
 550 #define INSN_OCTEON               0x00000800
 551
 552 /* Masks used for MIPS-defined ASEs.  */
 553 #define INSN_ASE_MASK             0x3c00f000
 554
 555 /* DSP ASE */
 556 #define INSN_DSP                  0x00001000
 557 #define INSN_DSP64                0x00002000
 558
 559 /* 0x00004000 is unused.  */
 560
 561 /* MIPS-3D ASE */
 562 #define INSN_MIPS3D               0x00008000
 563
 564 /* MIPS R4650 instruction.  */
 565 #define INSN_4650                 0x00010000
 566 /* LSI R4010 instruction.  */
 567 #define INSN_4010                 0x00020000
 568 /* NEC VR4100 instruction.  */
 569 #define INSN_4100                 0x00040000
 570 /* Toshiba R3900 instruction.  */
 571 #define INSN_3900                 0x00080000
 572 /* MIPS R10000 instruction.  */
 573 #define INSN_10000                0x00100000
 574 /* Broadcom SB-1 instruction.  */
 575 #define INSN_SB1                  0x00200000
 576 /* NEC VR4111/VR4181 instruction.  */
 577 #define INSN_4111                 0x00400000
 578 /* NEC VR4120 instruction.  */
 579 #define INSN_4120                 0x00800000
 580 /* NEC VR5400 instruction.  */
 581 #define INSN_5400                 0x01000000
 582 /* NEC VR5500 instruction.  */
 583 #define INSN_5500                 0x02000000
 584
 585 /* MDMX ASE */
 586 #define INSN_MDMX                 0x04000000
 587 /* MT ASE */
 588 #define INSN_MT                   0x08000000
 589 /* SmartMIPS ASE  */
 590 #define INSN_SMARTMIPS            0x10000000
 591 /* DSP R2 ASE  */
 592 #define INSN_DSPR2                0x20000000
 593 /* ST Microelectronics Loongson 2E.  */
 594 #define INSN_LOONGSON_2E          0x40000000
 595 /* ST Microelectronics Loongson 2F.  */
 596 #define INSN_LOONGSON_2F          0x80000000
 597 /* RMI Xlr instruction */
 598 #define INSN_XLR                  0x00000020
 599
 600 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 601
 602 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 603 #define       ISA_MIPS1       INSN_ISA1
 604 #define       ISA_MIPS2       INSN_ISA2
 605 #define       ISA_MIPS3       INSN_ISA3
 606 #define       ISA_MIPS4       INSN_ISA4
 607 #define       ISA_MIPS5       INSN_ISA5
 608
 609 #define       ISA_MIPS32      INSN_ISA32
 610 #define       ISA_MIPS64      INSN_ISA64
 611
 612 #define       ISA_MIPS32R2    INSN_ISA32R2
 613 #define       ISA_MIPS64R2    INSN_ISA64R2
 614
 615
 616 /* CPU defines, use instead of hardcoding processor number. Keep this
 617    in sync with bfd/archures.c in order for machine selection to work.  */
 618 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 619 #define CPU_R3000       3000
 620 #define CPU_R3900       3900
 621 #define CPU_R4000       4000
 622 #define CPU_R4010       4010
 623 #define CPU_VR4100      4100
 624 #define CPU_R4111       4111
 625 #define CPU_VR4120      4120
 626 #define CPU_R4300       4300
 627 #define CPU_R4400       4400
 628 #define CPU_R4600       4600
 629 #define CPU_R4650       4650
 630 #define CPU_R5000       5000
 631 #define CPU_VR5400      5400
 632 #define CPU_VR5500      5500
 633 #define CPU_R6000       6000
 634 #define CPU_RM7000      7000
 635 #define CPU_R8000       8000
 636 #define CPU_RM9000      9000
 637 #define CPU_R10000      10000
 638 #define CPU_R12000      12000
 639 #define CPU_R14000      14000
 640 #define CPU_R16000      16000
 641 #define CPU_MIPS16      16
 642 #define CPU_MIPS32      32
 643 #define CPU_MIPS32R2    33
 644 #define CPU_MIPS5       5
 645 #define CPU_MIPS64      64
 646 #define CPU_MIPS64R2    65
 647 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 648 #define CPU_LOONGSON_2E 3001
 649 #define CPU_LOONGSON_2F 3002
 650 #define CPU_OCTEON      6501
 651 #define CPU_XLR         887682          /* decimal 'XLR'   */
 652
 653 /* Test for membership in an ISA including chip specific ISAs.  INSN
 654    is pointer to an element of the opcode table; ISA is the specified
 655    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 656    test, or zero if no CPU specific ISA test is desired.  */
 657
 658 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 659     (((isa & INSN_ISA_MASK) != 0                                        \
 660       && ((insn)->membership & INSN_ISA_MASK) != 0                      \
 661       && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >>                \
 662            (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0)       \
 663      || ((isa & ~INSN_ISA_MASK)                                         \
 664           & ((insn)->membership & ~INSN_ISA_MASK)) != 0                 \
 665      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 666      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 667      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 668      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 669      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 670      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 671      || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000   \
 672           || cpu == CPU_R16000)                                         \
 673          && ((insn)->membership & INSN_10000) != 0)                     \
 674      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 675      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 676      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 677      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 678      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 679      || (cpu == CPU_LOONGSON_2E                                         \
 680          && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
 681      || (cpu == CPU_LOONGSON_2F                                         \
 682          && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
 683      || (cpu == CPU_OCTEON                                              \
 684          && ((insn)->membership & INSN_OCTEON) != 0)                    \
 685      || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
 686      || 0)      /* Please keep this term for easier source merging.  */
 687
 688 /* This is a list of macro expanded instructions.
 689
 690    _I appended means immediate
 691    _A appended means address
 692    _AB appended means address with base register
 693    _D appended means 64 bit floating point constant
 694    _S appended means 32 bit floating point constant.  */
 695
 696 enum
 697 {
 698   M_ABS,
 699   M_ADD_I,
 700   M_ADDU_I,
 701   M_AND_I,
 702   M_BALIGN,
 703   M_BEQ,
 704   M_BEQ_I,
 705   M_BEQL_I,
 706   M_BGE,
 707   M_BGEL,
 708   M_BGE_I,
 709   M_BGEL_I,
 710   M_BGEU,
 711   M_BGEUL,
 712   M_BGEU_I,
 713   M_BGEUL_I,
 714   M_BGT,
 715   M_BGTL,
 716   M_BGT_I,
 717   M_BGTL_I,
 718   M_BGTU,
 719   M_BGTUL,
 720   M_BGTU_I,
 721   M_BGTUL_I,
 722   M_BLE,
 723   M_BLEL,
 724   M_BLE_I,
 725   M_BLEL_I,
 726   M_BLEU,
 727   M_BLEUL,
 728   M_BLEU_I,
 729   M_BLEUL_I,
 730   M_BLT,
 731   M_BLTL,
 732   M_BLT_I,
 733   M_BLTL_I,
 734   M_BLTU,
 735   M_BLTUL,
 736   M_BLTU_I,
 737   M_BLTUL_I,
 738   M_BNE,
 739   M_BNE_I,
 740   M_BNEL_I,
 741   M_CACHE_AB,
 742   M_DABS,
 743   M_DADD_I,
 744   M_DADDU_I,
 745   M_DDIV_3,
 746   M_DDIV_3I,
 747   M_DDIVU_3,
 748   M_DDIVU_3I,
 749   M_DEXT,
 750   M_DINS,
 751   M_DIV_3,
 752   M_DIV_3I,
 753   M_DIVU_3,
 754   M_DIVU_3I,
 755   M_DLA_AB,
 756   M_DLCA_AB,
 757   M_DLI,
 758   M_DMUL,
 759   M_DMUL_I,
 760   M_DMULO,
 761   M_DMULO_I,
 762   M_DMULOU,
 763   M_DMULOU_I,
 764   M_DREM_3,
 765   M_DREM_3I,
 766   M_DREMU_3,
 767   M_DREMU_3I,
 768   M_DSUB_I,
 769   M_DSUBU_I,
 770   M_DSUBU_I_2,
 771   M_J_A,
 772   M_JAL_1,
 773   M_JAL_2,
 774   M_JAL_A,
 775   M_L_DOB,
 776   M_L_DAB,
 777   M_LA_AB,
 778   M_LB_A,
 779   M_LB_AB,
 780   M_LBU_A,
 781   M_LBU_AB,
 782   M_LCA_AB,
 783   M_LD_A,
 784   M_LD_OB,
 785   M_LD_AB,
 786   M_LDC1_AB,
 787   M_LDC2_AB,
 788   M_LDC3_AB,
 789   M_LDL_AB,
 790   M_LDR_AB,
 791   M_LH_A,
 792   M_LH_AB,
 793   M_LHU_A,
 794   M_LHU_AB,
 795   M_LI,
 796   M_LI_D,
 797   M_LI_DD,
 798   M_LI_S,
 799   M_LI_SS,
 800   M_LL_AB,
 801   M_LLD_AB,
 802   M_LS_A,
 803   M_LW_A,
 804   M_LW_AB,
 805   M_LWC0_A,
 806   M_LWC0_AB,
 807   M_LWC1_A,
 808   M_LWC1_AB,
 809   M_LWC2_A,
 810   M_LWC2_AB,
 811   M_LWC3_A,
 812   M_LWC3_AB,
 813   M_LWL_A,
 814   M_LWL_AB,
 815   M_LWR_A,
 816   M_LWR_AB,
 817   M_LWU_AB,
 818   M_MSGSND,
 819   M_MSGLD,
 820   M_MSGLD_T,
 821   M_MSGWAIT,
 822   M_MSGWAIT_T,
 823   M_MOVE,
 824   M_MUL,
 825   M_MUL_I,
 826   M_MULO,
 827   M_MULO_I,
 828   M_MULOU,
 829   M_MULOU_I,
 830   M_NOR_I,
 831   M_OR_I,
 832   M_REM_3,
 833   M_REM_3I,
 834   M_REMU_3,
 835   M_REMU_3I,
 836   M_DROL,
 837   M_ROL,
 838   M_DROL_I,
 839   M_ROL_I,
 840   M_DROR,
 841   M_ROR,
 842   M_DROR_I,
 843   M_ROR_I,
 844   M_S_DA,
 845   M_S_DOB,
 846   M_S_DAB,
 847   M_S_S,
 848   M_SC_AB,
 849   M_SCD_AB,
 850   M_SD_A,
 851   M_SD_OB,
 852   M_SD_AB,
 853   M_SDC1_AB,
 854   M_SDC2_AB,
 855   M_SDC3_AB,
 856   M_SDL_AB,
 857   M_SDR_AB,
 858   M_SEQ,
 859   M_SEQ_I,
 860   M_SGE,
 861   M_SGE_I,
 862   M_SGEU,
 863   M_SGEU_I,
 864   M_SGT,
 865   M_SGT_I,
 866   M_SGTU,
 867   M_SGTU_I,
 868   M_SLE,
 869   M_SLE_I,
 870   M_SLEU,
 871   M_SLEU_I,
 872   M_SLT_I,
 873   M_SLTU_I,
 874   M_SNE,
 875   M_SNE_I,
 876   M_SB_A,
 877   M_SB_AB,
 878   M_SH_A,
 879   M_SH_AB,
 880   M_SW_A,
 881   M_SW_AB,
 882   M_SWC0_A,
 883   M_SWC0_AB,
 884   M_SWC1_A,
 885   M_SWC1_AB,
 886   M_SWC2_A,
 887   M_SWC2_AB,
 888   M_SWC3_A,
 889   M_SWC3_AB,
 890   M_SWL_A,
 891   M_SWL_AB,
 892   M_SWR_A,
 893   M_SWR_AB,
 894   M_SUB_I,
 895   M_SUBU_I,
 896   M_SUBU_I_2,
 897   M_TEQ_I,
 898   M_TGE_I,
 899   M_TGEU_I,
 900   M_TLT_I,
 901   M_TLTU_I,
 902   M_TNE_I,
 903   M_TRUNCWD,
 904   M_TRUNCWS,
 905   M_ULD,
 906   M_ULD_A,
 907   M_ULH,
 908   M_ULH_A,
 909   M_ULHU,
 910   M_ULHU_A,
 911   M_ULW,
 912   M_ULW_A,
 913   M_USH,
 914   M_USH_A,
 915   M_USW,
 916   M_USW_A,
 917   M_USD,
 918   M_USD_A,
 919   M_XOR_I,
 920   M_COP0,
 921   M_COP1,
 922   M_COP2,
 923   M_COP3,
 924   M_NUM_MACROS
 925 };
 926
 927
 928 /* The order of overloaded instructions matters.  Label arguments and
 929    register arguments look the same. Instructions that can have either
 930    for arguments must apear in the correct order in this table for the
 931    assembler to pick the right one. In other words, entries with
 932    immediate operands must apear after the same instruction with
 933    registers.
 934
 935    Many instructions are short hand for other instructions (i.e., The
 936    jal <register> instruction is short for jalr <register>).  */
 937
 938 extern const struct mips_opcode mips_builtin_opcodes[];
 939 extern const int bfd_mips_num_builtin_opcodes;
 940 extern struct mips_opcode *mips_opcodes;
 941 extern int bfd_mips_num_opcodes;
 942 #define NUMOPCODES bfd_mips_num_opcodes
 943
 944 \f
 945 /* The rest of this file adds definitions for the mips16 TinyRISC
 946    processor.  */
 947
 948 /* These are the bitmasks and shift counts used for the different
 949    fields in the instruction formats.  Other than OP, no masks are
 950    provided for the fixed portions of an instruction, since they are
 951    not needed.
 952
 953    The I format uses IMM11.
 954
 955    The RI format uses RX and IMM8.
 956
 957    The RR format uses RX, and RY.
 958
 959    The RRI format uses RX, RY, and IMM5.
 960
 961    The RRR format uses RX, RY, and RZ.
 962
 963    The RRI_A format uses RX, RY, and IMM4.
 964
 965    The SHIFT format uses RX, RY, and SHAMT.
 966
 967    The I8 format uses IMM8.
 968
 969    The I8_MOVR32 format uses RY and REGR32.
 970
 971    The IR_MOV32R format uses REG32R and MOV32Z.
 972
 973    The I64 format uses IMM8.
 974
 975    The RI64 format uses RY and IMM5.
 976    */
 977
 978 #define MIPS16OP_MASK_OP        0x1f
 979 #define MIPS16OP_SH_OP          11
 980 #define MIPS16OP_MASK_IMM11     0x7ff
 981 #define MIPS16OP_SH_IMM11       0
 982 #define MIPS16OP_MASK_RX        0x7
 983 #define MIPS16OP_SH_RX          8
 984 #define MIPS16OP_MASK_IMM8      0xff
 985 #define MIPS16OP_SH_IMM8        0
 986 #define MIPS16OP_MASK_RY        0x7
 987 #define MIPS16OP_SH_RY          5
 988 #define MIPS16OP_MASK_IMM5      0x1f
 989 #define MIPS16OP_SH_IMM5        0
 990 #define MIPS16OP_MASK_RZ        0x7
 991 #define MIPS16OP_SH_RZ          2
 992 #define MIPS16OP_MASK_IMM4      0xf
 993 #define MIPS16OP_SH_IMM4        0
 994 #define MIPS16OP_MASK_REGR32    0x1f
 995 #define MIPS16OP_SH_REGR32      0
 996 #define MIPS16OP_MASK_REG32R    0x1f
 997 #define MIPS16OP_SH_REG32R      3
 998 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 999 #define MIPS16OP_MASK_MOVE32Z   0x7
1000 #define MIPS16OP_SH_MOVE32Z     0
1001 #define MIPS16OP_MASK_IMM6      0x3f
1002 #define MIPS16OP_SH_IMM6        5
1003
1004 /* These are the characters which may appears in the args field of a MIPS16
1005    instruction.  They appear in the order in which the fields appear when the
1006    instruction is used.  Commas and parentheses in the args string are ignored
1007    when assembling, and written into the output when disassembling.
1008
1009    "y" 3 bit register (MIPS16OP_*_RY)
1010    "x" 3 bit register (MIPS16OP_*_RX)
1011    "z" 3 bit register (MIPS16OP_*_RZ)
1012    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1013    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1014    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1015    "0" zero register ($0)
1016    "S" stack pointer ($sp or $29)
1017    "P" program counter
1018    "R" return address register ($ra or $31)
1019    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1020    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1021    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1022    "a" 26 bit jump address
1023    "e" 11 bit extension value
1024    "l" register list for entry instruction
1025    "L" register list for exit instruction
1026
1027    The remaining codes may be extended.  Except as otherwise noted,
1028    the full extended operand is a 16 bit signed value.
1029    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1030    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1031    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1032    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1033    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1034    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1035    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1036    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1037    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1038    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1039    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1040    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1041    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1042    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1043    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1044    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1045    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1046    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1047    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1048    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1049    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1050    "m" 7 bit register list for save instruction (18 bit extended)
1051    "M" 7 bit register list for restore instruction (18 bit extended)
1052   */
1053
1054 /* Save/restore encoding for the args field when all 4 registers are
1055    either saved as arguments or saved/restored as statics.  */
1056 #define MIPS16_ALL_ARGS    0xe
1057 #define MIPS16_ALL_STATICS 0xb
1058
1059 /* For the mips16, we use the same opcode table format and a few of
1060    the same flags.  However, most of the flags are different.  */
1061
1062 /* Modifies the register in MIPS16OP_*_RX.  */
1063 #define MIPS16_INSN_WRITE_X                 0x00000001
1064 /* Modifies the register in MIPS16OP_*_RY.  */
1065 #define MIPS16_INSN_WRITE_Y                 0x00000002
1066 /* Modifies the register in MIPS16OP_*_RZ.  */
1067 #define MIPS16_INSN_WRITE_Z                 0x00000004
1068 /* Modifies the T ($24) register.  */
1069 #define MIPS16_INSN_WRITE_T                 0x00000008
1070 /* Modifies the SP ($29) register.  */
1071 #define MIPS16_INSN_WRITE_SP                0x00000010
1072 /* Modifies the RA ($31) register.  */
1073 #define MIPS16_INSN_WRITE_31                0x00000020
1074 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1075 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1076 /* Reads the register in MIPS16OP_*_RX.  */
1077 #define MIPS16_INSN_READ_X                  0x00000080
1078 /* Reads the register in MIPS16OP_*_RY.  */
1079 #define MIPS16_INSN_READ_Y                  0x00000100
1080 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1081 #define MIPS16_INSN_READ_Z                  0x00000200
1082 /* Reads the T ($24) register.  */
1083 #define MIPS16_INSN_READ_T                  0x00000400
1084 /* Reads the SP ($29) register.  */
1085 #define MIPS16_INSN_READ_SP                 0x00000800
1086 /* Reads the RA ($31) register.  */
1087 #define MIPS16_INSN_READ_31                 0x00001000
1088 /* Reads the program counter.  */
1089 #define MIPS16_INSN_READ_PC                 0x00002000
1090 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1091 #define MIPS16_INSN_READ_GPR_X              0x00004000
1092 /* Is an unconditional branch insn. */
1093 #define MIPS16_INSN_UNCOND_BRANCH           0x00008000
1094 /* Is a conditional branch insn. */
1095 #define MIPS16_INSN_COND_BRANCH             0x00010000
1096
1097 /* The following flags have the same value for the mips16 opcode
1098    table:
1099    INSN_UNCOND_BRANCH_DELAY
1100    INSN_COND_BRANCH_DELAY
1101    INSN_COND_BRANCH_LIKELY (never used)
1102    INSN_READ_HI
1103    INSN_READ_LO
1104    INSN_WRITE_HI
1105    INSN_WRITE_LO
1106    INSN_TRAP
1107    INSN_ISA3
1108    */
1109
1110 extern const struct mips_opcode mips16_opcodes[];
1111 extern const int bfd_mips16_num_opcodes;
1112
1113 /* A NOP insn impemented as "or at,at,zero".
1114    Used to implement -mfix-loongson2f.  */
1115 #define LOONGSON2F_NOP_INSN     0x00200825
1116
1117 #endif /* _MIPS_H_ */