1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2008, 2009, 2010, 2013
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
8 This file is part of GDB, GAS, and the GNU binutils.
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version 3,
13 or (at your option) any later version.
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING3. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
30 /* These are bit masks and shift counts to use to access the various
31 fields of an instruction. To retrieve the X field of an
32 instruction, use the expression
33 (i >> OP_SH_X) & OP_MASK_X
34 To set the same field (to j), use
35 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
37 Make sure you use fields that are appropriate for the instruction,
40 The 'i' format uses OP, RS, RT and IMMEDIATE.
42 The 'j' format uses OP and TARGET.
44 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
46 The 'b' format uses OP, RS, RT and DELTA.
48 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
50 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
52 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
53 breakpoint instruction are not defined; Kane says the breakpoint
54 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
55 only use ten bits). An optional two-operand form of break/sdbbp
56 allows the lower ten bits to be set too, and MIPS32 and later
57 architectures allow 20 bits to be set with a signal operand
60 The syscall instruction uses CODE20.
62 The general coprocessor instructions use COPZ. */
64 #define OP_MASK_OP 0x3f
66 #define OP_MASK_RS 0x1f
68 #define OP_MASK_FR 0x1f
70 #define OP_MASK_FMT 0x1f
72 #define OP_MASK_BCC 0x7
74 #define OP_MASK_CODE 0x3ff
76 #define OP_MASK_CODE2 0x3ff
78 #define OP_MASK_RT 0x1f
80 #define OP_MASK_FT 0x1f
82 #define OP_MASK_CACHE 0x1f
83 #define OP_SH_CACHE 16
84 #define OP_MASK_RD 0x1f
86 #define OP_MASK_FS 0x1f
88 #define OP_MASK_PREFX 0x1f
89 #define OP_SH_PREFX 11
90 #define OP_MASK_CCC 0x7
92 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
93 #define OP_SH_CODE20 6
94 #define OP_MASK_SHAMT 0x1f
96 #define OP_MASK_EXTLSB OP_MASK_SHAMT
97 #define OP_SH_EXTLSB OP_SH_SHAMT
98 #define OP_MASK_STYPE OP_MASK_SHAMT
99 #define OP_SH_STYPE OP_SH_SHAMT
100 #define OP_MASK_FD 0x1f
102 #define OP_MASK_TARGET 0x3ffffff
103 #define OP_SH_TARGET 0
104 #define OP_MASK_COPZ 0x1ffffff
106 #define OP_MASK_IMMEDIATE 0xffff
107 #define OP_SH_IMMEDIATE 0
108 #define OP_MASK_DELTA 0xffff
109 #define OP_SH_DELTA 0
110 #define OP_MASK_FUNCT 0x3f
111 #define OP_SH_FUNCT 0
112 #define OP_MASK_SPEC 0x3f
114 #define OP_SH_LOCC 8 /* FP condition code. */
115 #define OP_SH_HICC 18 /* FP condition code. */
116 #define OP_MASK_CC 0x7
117 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
118 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
119 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
120 #define OP_MASK_COP1SPEC 0xf
121 #define OP_MASK_COP1SCLR 0x4
122 #define OP_MASK_COP1CMP 0x3
123 #define OP_SH_COP1CMP 4
124 #define OP_SH_FORMAT 21 /* FP short format field. */
125 #define OP_MASK_FORMAT 0x7
126 #define OP_SH_TRUE 16
127 #define OP_MASK_TRUE 0x1
129 #define OP_MASK_GE 0x01
130 #define OP_SH_UNSIGNED 16
131 #define OP_MASK_UNSIGNED 0x1
132 #define OP_SH_HINT 16
133 #define OP_MASK_HINT 0x1f
134 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
135 #define OP_MASK_MMI 0x3f
136 #define OP_SH_MMISUB 6
137 #define OP_MASK_MMISUB 0x1f
138 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
139 #define OP_SH_PERFREG 1
140 #define OP_SH_SEL 0 /* Coprocessor select field. */
141 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
142 #define OP_SH_CODE19 6 /* 19 bit wait code. */
143 #define OP_MASK_CODE19 0x7ffff
145 #define OP_MASK_ALN 0x7
146 #define OP_SH_VSEL 21
147 #define OP_MASK_VSEL 0x1f
148 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
149 but 0x8-0xf don't select bytes. */
150 #define OP_SH_VECBYTE 22
151 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
152 #define OP_SH_VECALIGN 21
153 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
154 #define OP_SH_INSMSB 11
155 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
156 #define OP_SH_EXTMSBD 11
159 #define OP_SH_DSPACC 11
160 #define OP_MASK_DSPACC 0x3
161 #define OP_SH_DSPACC_S 21
162 #define OP_MASK_DSPACC_S 0x3
163 #define OP_SH_DSPSFT 20
164 #define OP_MASK_DSPSFT 0x3f
165 #define OP_SH_DSPSFT_7 19
166 #define OP_MASK_DSPSFT_7 0x7f
168 #define OP_MASK_SA3 0x7
170 #define OP_MASK_SA4 0xf
171 #define OP_SH_IMM8 16
172 #define OP_MASK_IMM8 0xff
173 #define OP_SH_IMM10 16
174 #define OP_MASK_IMM10 0x3ff
175 #define OP_SH_WRDSP 11
176 #define OP_MASK_WRDSP 0x3f
177 #define OP_SH_RDDSP 16
178 #define OP_MASK_RDDSP 0x3f
180 #define OP_MASK_BP 0x3
184 #define OP_MASK_MT_U 0x1
186 #define OP_MASK_MT_H 0x1
187 #define OP_SH_MTACC_T 18
188 #define OP_MASK_MTACC_T 0x3
189 #define OP_SH_MTACC_D 13
190 #define OP_MASK_MTACC_D 0x3
193 #define OP_MASK_3BITPOS 0x7
194 #define OP_SH_3BITPOS 12
195 #define OP_MASK_OFFSET12 0xfff
196 #define OP_SH_OFFSET12 0
198 #define OP_OP_COP0 0x10
199 #define OP_OP_COP1 0x11
200 #define OP_OP_COP2 0x12
201 #define OP_OP_COP3 0x13
202 #define OP_OP_LWC1 0x31
203 #define OP_OP_LWC2 0x32
204 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
205 #define OP_OP_LDC1 0x35
206 #define OP_OP_LDC2 0x36
207 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
208 #define OP_OP_SWC1 0x39
209 #define OP_OP_SWC2 0x3a
210 #define OP_OP_SWC3 0x3b
211 #define OP_OP_SDC1 0x3d
212 #define OP_OP_SDC2 0x3e
213 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
216 #define OP_MASK_CODE10 0x3ff
217 #define OP_SH_CODE10 11
219 /* Values in the 'VSEL' field. */
220 #define MDMX_FMTSEL_IMM_QH 0x1d
221 #define MDMX_FMTSEL_IMM_OB 0x1e
222 #define MDMX_FMTSEL_VEC_QH 0x15
223 #define MDMX_FMTSEL_VEC_OB 0x16
227 #define OP_MASK_UDI1 0x1f
229 #define OP_MASK_UDI2 0x3ff
231 #define OP_MASK_UDI3 0x7fff
233 #define OP_MASK_UDI4 0xfffff
236 #define OP_SH_BBITIND 16
237 #define OP_MASK_BBITIND 0x1f
238 #define OP_SH_CINSPOS 6
239 #define OP_MASK_CINSPOS 0x1f
240 #define OP_SH_CINSLM1 11
241 #define OP_MASK_CINSLM1 0x1f
243 #define OP_MASK_SEQI 0x3ff
246 #define OP_SH_OFFSET_A 6
247 #define OP_MASK_OFFSET_A 0xff
248 #define OP_SH_OFFSET_B 3
249 #define OP_MASK_OFFSET_B 0xff
250 #define OP_SH_OFFSET_C 6
251 #define OP_MASK_OFFSET_C 0x1ff
253 #define OP_MASK_RZ 0x1f
255 #define OP_MASK_FZ 0x1f
257 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
258 definition, and vice versa. This simplifies various parts
259 of the operand handling in GAS. The fields below only exist
260 in the microMIPS encoding, so define each one to have an empty
262 #define OP_MASK_TRAP 0
264 #define OP_MASK_OFFSET10 0
265 #define OP_SH_OFFSET10 0
266 #define OP_MASK_RS3 0
294 #define OP_MASK_IMMA 0
296 #define OP_MASK_IMMB 0
298 #define OP_MASK_IMMC 0
300 #define OP_MASK_IMMF 0
302 #define OP_MASK_IMMG 0
304 #define OP_MASK_IMMH 0
306 #define OP_MASK_IMMI 0
308 #define OP_MASK_IMMJ 0
310 #define OP_MASK_IMML 0
312 #define OP_MASK_IMMM 0
314 #define OP_MASK_IMMN 0
316 #define OP_MASK_IMMO 0
318 #define OP_MASK_IMMP 0
320 #define OP_MASK_IMMQ 0
322 #define OP_MASK_IMMU 0
324 #define OP_MASK_IMMW 0
326 #define OP_MASK_IMMX 0
328 #define OP_MASK_IMMY 0
331 /* Enhanced VA Scheme */
332 #define OP_SH_EVAOFFSET 7
333 #define OP_MASK_EVAOFFSET 0x1ff
335 /* This structure holds information for a particular instruction. */
339 /* The name of the instruction. */
341 /* A string describing the arguments for this instruction. */
343 /* The basic opcode for the instruction. When assembling, this
344 opcode is modified by the arguments to produce the actual opcode
345 that is used. If pinfo is INSN_MACRO, then this is 0. */
347 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
348 relevant portions of the opcode when disassembling. If the
349 actual opcode anded with the match field equals the opcode field,
350 then we have found the correct instruction. If pinfo is
351 INSN_MACRO, then this field is the macro identifier. */
353 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
354 of bits describing the instruction, notably any relevant hazard
357 /* A collection of additional bits describing the instruction. */
358 unsigned long pinfo2
;
359 /* A collection of bits describing the instruction sets of which this
360 instruction or macro is a member. */
361 unsigned long membership
;
362 /* A collection of bits describing the ASE of which this instruction
363 or macro is a member. */
365 /* A collection of bits describing the instruction sets of which this
366 instruction or macro is not a member. */
367 unsigned long exclusions
;
370 /* These are the characters which may appear in the args field of an
371 instruction. They appear in the order in which the fields appear
372 when the instruction is used. Commas and parentheses in the args
373 string are ignored when assembling, and written into the output
376 Each of these characters corresponds to a mask field defined above.
378 "1" 5 bit sync type (OP_*_STYPE)
379 "<" 5 bit shift amount (OP_*_SHAMT)
380 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
381 "a" 26 bit target address (OP_*_TARGET)
382 "+i" likewise, but flips bit 0
383 "b" 5 bit base register (OP_*_RS)
384 "c" 10 bit breakpoint code (OP_*_CODE)
385 "d" 5 bit destination register specifier (OP_*_RD)
386 "h" 5 bit prefx hint (OP_*_PREFX)
387 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
388 "j" 16 bit signed immediate (OP_*_DELTA)
389 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
390 "o" 16 bit signed offset (OP_*_DELTA)
391 "p" 16 bit PC relative branch target address (OP_*_DELTA)
392 "q" 10 bit extra breakpoint code (OP_*_CODE2)
393 "r" 5 bit same register used as both source and target (OP_*_RS)
394 "s" 5 bit source register specifier (OP_*_RS)
395 "t" 5 bit target register (OP_*_RT)
396 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
397 "v" 5 bit same register used as both source and destination (OP_*_RS)
398 "w" 5 bit same register used as both target and destination (OP_*_RT)
399 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
400 (used by clo and clz)
401 "C" 25 bit coprocessor function code (OP_*_COPZ)
402 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
403 "J" 19 bit wait function code (OP_*_CODE19)
404 "x" accept and ignore register name
405 "z" must be zero register
406 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
407 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
408 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
409 microMIPS compatibility).
410 Enforces: 0 <= pos < 32.
411 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
412 Requires that "+A" or "+E" occur first to set position.
413 Enforces: 0 < (pos+size) <= 32.
414 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
415 Requires that "+A" or "+E" occur first to set position.
416 Enforces: 0 < (pos+size) <= 32.
417 (Also used by "dext" w/ different limits, but limits for
418 that are checked by the M_DEXT macro.)
419 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
420 Enforces: 32 <= pos < 64.
421 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
422 Requires that "+A" or "+E" occur first to set position.
423 Enforces: 32 < (pos+size) <= 64.
424 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
425 Requires that "+A" or "+E" occur first to set position.
426 Enforces: 32 < (pos+size) <= 64.
427 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
428 Requires that "+A" or "+E" occur first to set position.
429 Enforces: 32 < (pos+size) <= 64.
431 Floating point instructions:
432 "D" 5 bit destination register (OP_*_FD)
433 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
434 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
435 "S" 5 bit fs source 1 register (OP_*_FS)
436 "T" 5 bit ft source 2 register (OP_*_FT)
437 "R" 5 bit fr source 3 register (OP_*_FR)
438 "V" 5 bit same register used as floating source and destination (OP_*_FS)
439 "W" 5 bit same register used as floating target and destination (OP_*_FT)
441 Coprocessor instructions:
442 "E" 5 bit target register (OP_*_RT)
443 "G" 5 bit destination register (OP_*_RD)
444 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
445 "P" 5 bit performance-monitor register (OP_*_PERFREG)
446 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
447 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
450 "A" General 32 bit expression
451 "I" 32 bit immediate (value placed in imm_expr).
452 "+I" 32 bit immediate (value placed in imm2_expr).
453 "F" 64 bit floating point constant in .rdata
454 "L" 64 bit floating point constant in .lit8
455 "f" 32 bit floating point constant
456 "l" 32 bit floating point constant in .lit4
458 MDMX and VR5400 instruction operands (note that while these use the
459 FP register fields, the MDMX instructions accept both $fN and $vN names
461 "O" alignment offset (OP_*_ALN)
462 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
463 "X" destination register (OP_*_FD)
464 "Y" source register (OP_*_FS)
465 "Z" source register (OP_*_FT)
468 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
469 "3" 3 bit unsigned immediate (OP_*_SA3)
470 "4" 4 bit unsigned immediate (OP_*_SA4)
471 "5" 8 bit unsigned immediate (OP_*_IMM8)
472 "6" 5 bit unsigned immediate (OP_*_RS)
473 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
474 "8" 6 bit unsigned immediate (OP_*_WRDSP)
475 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
476 "0" 6 bit signed immediate (OP_*_DSPSFT)
477 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
478 "'" 6 bit unsigned immediate (OP_*_RDDSP)
479 "@" 10 bit signed immediate (OP_*_IMM10)
482 "!" 1 bit usermode flag (OP_*_MT_U)
483 "$" 1 bit load high flag (OP_*_MT_H)
484 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
485 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
486 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
487 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
490 "~" 12 bit offset (OP_*_OFFSET12)
491 "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
494 "+J" 10-bit hypcall code (OP_*CODE10)
497 "+1" UDI immediate bits 6-10
498 "+2" UDI immediate bits 6-15
499 "+3" UDI immediate bits 6-20
500 "+4" UDI immediate bits 6-25
503 "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
504 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
505 otherwise skips to next candidate.
506 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
507 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
508 32 <= pos < 64, otherwise skips to next candidate.
509 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
510 "+s" Length-minus-one field of cins32/exts32. Requires msb position
511 of the field to be <= 31.
512 "+S" Length-minus-one field of cins/exts. Requires msb position
513 of the field to be <= 63.
516 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
517 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
518 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
519 "+z" 5-bit rz register (OP_*_RZ)
520 "+Z" 5-bit fz register (OP_*_FZ)
523 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
526 "()" parens surrounding optional value
527 "," separates operands
528 "+" Start of extension sequence.
530 Characters used so far, for quick reference when adding more:
533 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
534 "abcdefghijklopqrstuvwxz"
536 Extension character sequences used so far ("+" followed by the
537 following), for quick reference when adding more:
543 /* These are the bits which may be set in the pinfo field of an
544 instructions, if it is not equal to INSN_MACRO. */
546 /* Modifies the general purpose register in OP_*_RD. */
547 #define INSN_WRITE_GPR_D 0x00000001
548 /* Modifies the general purpose register in OP_*_RT. */
549 #define INSN_WRITE_GPR_T 0x00000002
550 /* Modifies general purpose register 31. */
551 #define INSN_WRITE_GPR_31 0x00000004
552 /* Modifies the floating point register in OP_*_FD. */
553 #define INSN_WRITE_FPR_D 0x00000008
554 /* Modifies the floating point register in OP_*_FS. */
555 #define INSN_WRITE_FPR_S 0x00000010
556 /* Modifies the floating point register in OP_*_FT. */
557 #define INSN_WRITE_FPR_T 0x00000020
558 /* Reads the general purpose register in OP_*_RS. */
559 #define INSN_READ_GPR_S 0x00000040
560 /* Reads the general purpose register in OP_*_RT. */
561 #define INSN_READ_GPR_T 0x00000080
562 /* Reads the floating point register in OP_*_FS. */
563 #define INSN_READ_FPR_S 0x00000100
564 /* Reads the floating point register in OP_*_FT. */
565 #define INSN_READ_FPR_T 0x00000200
566 /* Reads the floating point register in OP_*_FR. */
567 #define INSN_READ_FPR_R 0x00000400
568 /* Modifies coprocessor condition code. */
569 #define INSN_WRITE_COND_CODE 0x00000800
570 /* Reads coprocessor condition code. */
571 #define INSN_READ_COND_CODE 0x00001000
573 #define INSN_TLB 0x00002000
574 /* Reads coprocessor register other than floating point register. */
575 #define INSN_COP 0x00004000
576 /* Instruction loads value from memory, requiring delay. */
577 #define INSN_LOAD_MEMORY_DELAY 0x00008000
578 /* Instruction loads value from coprocessor, requiring delay. */
579 #define INSN_LOAD_COPROC_DELAY 0x00010000
580 /* Instruction has unconditional branch delay slot. */
581 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
582 /* Instruction has conditional branch delay slot. */
583 #define INSN_COND_BRANCH_DELAY 0x00040000
584 /* Conditional branch likely: if branch not taken, insn nullified. */
585 #define INSN_COND_BRANCH_LIKELY 0x00080000
586 /* Moves to coprocessor register, requiring delay. */
587 #define INSN_COPROC_MOVE_DELAY 0x00100000
588 /* Loads coprocessor register from memory, requiring delay. */
589 #define INSN_COPROC_MEMORY_DELAY 0x00200000
590 /* Reads the HI register. */
591 #define INSN_READ_HI 0x00400000
592 /* Reads the LO register. */
593 #define INSN_READ_LO 0x00800000
594 /* Modifies the HI register. */
595 #define INSN_WRITE_HI 0x01000000
596 /* Modifies the LO register. */
597 #define INSN_WRITE_LO 0x02000000
598 /* Not to be placed in a branch delay slot, either architecturally
599 or for ease of handling (such as with instructions that take a trap). */
600 #define INSN_NO_DELAY_SLOT 0x04000000
601 /* Instruction stores value into memory. */
602 #define INSN_STORE_MEMORY 0x08000000
603 /* Instruction uses single precision floating point. */
604 #define FP_S 0x10000000
605 /* Instruction uses double precision floating point. */
606 #define FP_D 0x20000000
607 /* Instruction is part of the tx39's integer multiply family. */
608 #define INSN_MULT 0x40000000
609 /* Modifies the general purpose register in MICROMIPSOP_*_RS. */
610 #define INSN_WRITE_GPR_S 0x80000000
611 /* Instruction is actually a macro. It should be ignored by the
612 disassembler, and requires special treatment by the assembler. */
613 #define INSN_MACRO 0xffffffff
615 /* These are the bits which may be set in the pinfo2 field of an
618 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
619 #define INSN2_ALIAS 0x00000001
620 /* Instruction reads MDMX accumulator. */
621 #define INSN2_READ_MDMX_ACC 0x00000002
622 /* Instruction writes MDMX accumulator. */
623 #define INSN2_WRITE_MDMX_ACC 0x00000004
624 /* Macro uses single-precision floating-point instructions. This should
625 only be set for macros. For instructions, FP_S in pinfo carries the
627 #define INSN2_M_FP_S 0x00000008
628 /* Macro uses double-precision floating-point instructions. This should
629 only be set for macros. For instructions, FP_D in pinfo carries the
631 #define INSN2_M_FP_D 0x00000010
632 /* Modifies the general purpose register in OP_*_RZ. */
633 #define INSN2_WRITE_GPR_Z 0x00000020
634 /* Modifies the floating point register in OP_*_FZ. */
635 #define INSN2_WRITE_FPR_Z 0x00000040
636 /* Reads the general purpose register in OP_*_RZ. */
637 #define INSN2_READ_GPR_Z 0x00000080
638 /* Reads the floating point register in OP_*_FZ. */
639 #define INSN2_READ_FPR_Z 0x00000100
640 /* Reads the general purpose register in OP_*_RD. */
641 #define INSN2_READ_GPR_D 0x00000200
644 /* Instruction has a branch delay slot that requires a 16-bit instruction. */
645 #define INSN2_BRANCH_DELAY_16BIT 0x00000400
646 /* Instruction has a branch delay slot that requires a 32-bit instruction. */
647 #define INSN2_BRANCH_DELAY_32BIT 0x00000800
648 /* Reads the floating point register in MICROMIPSOP_*_FD. */
649 #define INSN2_READ_FPR_D 0x00001000
650 /* Modifies the general purpose register in MICROMIPSOP_*_MB. */
651 #define INSN2_WRITE_GPR_MB 0x00002000
652 /* Reads the general purpose register in MICROMIPSOP_*_MC. */
653 #define INSN2_READ_GPR_MC 0x00004000
654 /* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */
655 #define INSN2_MOD_GPR_MD 0x00008000
656 /* Reads the general purpose register in MICROMIPSOP_*_ME. */
657 #define INSN2_READ_GPR_ME 0x00010000
658 /* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */
659 #define INSN2_MOD_GPR_MF 0x00020000
660 /* Reads the general purpose register in MICROMIPSOP_*_MG. */
661 #define INSN2_READ_GPR_MG 0x00040000
662 /* Reads the general purpose register in MICROMIPSOP_*_MJ. */
663 #define INSN2_READ_GPR_MJ 0x00080000
664 /* Modifies the general purpose register in MICROMIPSOP_*_MJ. */
665 #define INSN2_WRITE_GPR_MJ 0x00100000
666 /* Reads the general purpose register in MICROMIPSOP_*_MP. */
667 #define INSN2_READ_GPR_MP 0x00200000
668 /* Modifies the general purpose register in MICROMIPSOP_*_MP. */
669 #define INSN2_WRITE_GPR_MP 0x00400000
670 /* Reads the general purpose register in MICROMIPSOP_*_MQ. */
671 #define INSN2_READ_GPR_MQ 0x00800000
672 /* Reads/Writes the stack pointer ($29). */
673 #define INSN2_MOD_SP 0x01000000
674 /* Reads the RA ($31) register. */
675 #define INSN2_READ_GPR_31 0x02000000
676 /* Reads the global pointer ($28). */
677 #define INSN2_READ_GP 0x04000000
678 /* Reads the program counter ($pc). */
679 #define INSN2_READ_PC 0x08000000
680 /* Is an unconditional branch insn. */
681 #define INSN2_UNCOND_BRANCH 0x10000000
682 /* Is a conditional branch insn. */
683 #define INSN2_COND_BRANCH 0x20000000
684 /* Modifies the general purpose registers in MICROMIPSOP_*_MH. */
685 #define INSN2_WRITE_GPR_MH 0x40000000
686 /* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
687 #define INSN2_READ_GPR_MMN 0x80000000
689 /* Masks used to mark instructions to indicate which MIPS ISA level
690 they were introduced in. INSN_ISA_MASK masks an enumeration that
691 specifies the base ISA level(s). The remainder of a 32-bit
692 word constructed using these macros is a bitmask of the remaining
693 INSN_* values below. */
695 #define INSN_ISA_MASK 0x0000000ful
697 /* We cannot start at zero due to ISA_UNKNOWN below. */
704 #define INSN_ISA32R2 7
706 #define INSN_ISA64R2 9
707 /* Below this point the INSN_* values correspond to combinations of ISAs.
708 They are only for use in the opcodes table to indicate membership of
709 a combination of ISAs that cannot be expressed using the usual inclusion
710 ordering on the above INSN_* values. */
711 #define INSN_ISA3_32 10
712 #define INSN_ISA3_32R2 11
713 #define INSN_ISA4_32 12
714 #define INSN_ISA4_32R2 13
715 #define INSN_ISA5_32R2 14
717 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
718 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
719 this table describes whether at least one of the ISAs described by X
720 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
721 a particular core and X as the ISA level(s) at which a certain instruction
722 is defined.) The ISA(s) described by X is/are implemented by Y iff
723 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
725 static const unsigned int mips_isa_table
[] =
726 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
728 /* Masks used for Chip specific instructions. */
729 #define INSN_CHIP_MASK 0xc3ff0f20
731 /* Cavium Networks Octeon instructions. */
732 #define INSN_OCTEON 0x00000800
733 #define INSN_OCTEONP 0x00000200
734 #define INSN_OCTEON2 0x00000100
736 /* MIPS R5900 instruction */
737 #define INSN_5900 0x00004000
739 /* MIPS R4650 instruction. */
740 #define INSN_4650 0x00010000
741 /* LSI R4010 instruction. */
742 #define INSN_4010 0x00020000
743 /* NEC VR4100 instruction. */
744 #define INSN_4100 0x00040000
745 /* Toshiba R3900 instruction. */
746 #define INSN_3900 0x00080000
747 /* MIPS R10000 instruction. */
748 #define INSN_10000 0x00100000
749 /* Broadcom SB-1 instruction. */
750 #define INSN_SB1 0x00200000
751 /* NEC VR4111/VR4181 instruction. */
752 #define INSN_4111 0x00400000
753 /* NEC VR4120 instruction. */
754 #define INSN_4120 0x00800000
755 /* NEC VR5400 instruction. */
756 #define INSN_5400 0x01000000
757 /* NEC VR5500 instruction. */
758 #define INSN_5500 0x02000000
760 /* ST Microelectronics Loongson 2E. */
761 #define INSN_LOONGSON_2E 0x40000000
762 /* ST Microelectronics Loongson 2F. */
763 #define INSN_LOONGSON_2F 0x80000000
765 #define INSN_LOONGSON_3A 0x00000400
766 /* RMI Xlr instruction */
767 #define INSN_XLR 0x00000020
770 #define ASE_DSP 0x00000001
771 #define ASE_DSP64 0x00000002
773 #define ASE_DSPR2 0x00000004
774 /* Enhanced VA Scheme */
775 #define ASE_EVA 0x00000008
776 /* MCU (MicroController) ASE */
777 #define ASE_MCU 0x00000010
779 #define ASE_MDMX 0x00000020
781 #define ASE_MIPS3D 0x00000040
783 #define ASE_MT 0x00000080
785 #define ASE_SMARTMIPS 0x00000100
786 /* Virtualization ASE */
787 #define ASE_VIRT 0x00000200
788 #define ASE_VIRT64 0x00000400
790 /* MIPS ISA defines, use instead of hardcoding ISA level. */
792 #define ISA_UNKNOWN 0 /* Gas internal use. */
793 #define ISA_MIPS1 INSN_ISA1
794 #define ISA_MIPS2 INSN_ISA2
795 #define ISA_MIPS3 INSN_ISA3
796 #define ISA_MIPS4 INSN_ISA4
797 #define ISA_MIPS5 INSN_ISA5
799 #define ISA_MIPS32 INSN_ISA32
800 #define ISA_MIPS64 INSN_ISA64
802 #define ISA_MIPS32R2 INSN_ISA32R2
803 #define ISA_MIPS64R2 INSN_ISA64R2
806 /* CPU defines, use instead of hardcoding processor number. Keep this
807 in sync with bfd/archures.c in order for machine selection to work. */
808 #define CPU_UNKNOWN 0 /* Gas internal use. */
809 #define CPU_R3000 3000
810 #define CPU_R3900 3900
811 #define CPU_R4000 4000
812 #define CPU_R4010 4010
813 #define CPU_VR4100 4100
814 #define CPU_R4111 4111
815 #define CPU_VR4120 4120
816 #define CPU_R4300 4300
817 #define CPU_R4400 4400
818 #define CPU_R4600 4600
819 #define CPU_R4650 4650
820 #define CPU_R5000 5000
821 #define CPU_VR5400 5400
822 #define CPU_VR5500 5500
823 #define CPU_R5900 5900
824 #define CPU_R6000 6000
825 #define CPU_RM7000 7000
826 #define CPU_R8000 8000
827 #define CPU_RM9000 9000
828 #define CPU_R10000 10000
829 #define CPU_R12000 12000
830 #define CPU_R14000 14000
831 #define CPU_R16000 16000
832 #define CPU_MIPS16 16
833 #define CPU_MIPS32 32
834 #define CPU_MIPS32R2 33
836 #define CPU_MIPS64 64
837 #define CPU_MIPS64R2 65
838 #define CPU_SB1 12310201 /* octal 'SB', 01. */
839 #define CPU_LOONGSON_2E 3001
840 #define CPU_LOONGSON_2F 3002
841 #define CPU_LOONGSON_3A 3003
842 #define CPU_OCTEON 6501
843 #define CPU_OCTEONP 6601
844 #define CPU_OCTEON2 6502
845 #define CPU_XLR 887682 /* decimal 'XLR' */
847 /* Return true if the given CPU is included in INSN_* mask MASK. */
849 static inline bfd_boolean
850 cpu_is_member (int cpu
, unsigned int mask
)
857 return (mask
& INSN_4650
) != 0;
860 return (mask
& INSN_4010
) != 0;
863 return (mask
& INSN_4100
) != 0;
866 return (mask
& INSN_3900
) != 0;
872 return (mask
& INSN_10000
) != 0;
875 return (mask
& INSN_SB1
) != 0;
878 return (mask
& INSN_4111
) != 0;
881 return (mask
& INSN_4120
) != 0;
884 return (mask
& INSN_5400
) != 0;
887 return (mask
& INSN_5500
) != 0;
890 return (mask
& INSN_5900
) != 0;
892 case CPU_LOONGSON_2E
:
893 return (mask
& INSN_LOONGSON_2E
) != 0;
895 case CPU_LOONGSON_2F
:
896 return (mask
& INSN_LOONGSON_2F
) != 0;
898 case CPU_LOONGSON_3A
:
899 return (mask
& INSN_LOONGSON_3A
) != 0;
902 return (mask
& INSN_OCTEON
) != 0;
905 return (mask
& INSN_OCTEONP
) != 0;
908 return (mask
& INSN_OCTEON2
) != 0;
911 return (mask
& INSN_XLR
) != 0;
918 /* Test for membership in an ISA including chip specific ISAs. INSN
919 is pointer to an element of the opcode table; ISA is the specified
920 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
921 test, or zero if no CPU specific ISA test is desired. Return true
922 if instruction INSN is available to the given ISA and CPU. */
924 static inline bfd_boolean
925 opcode_is_member (const struct mips_opcode
*insn
, int isa
, int ase
, int cpu
)
927 if (!cpu_is_member (cpu
, insn
->exclusions
))
929 /* Test for ISA level compatibility. */
930 if ((isa
& INSN_ISA_MASK
) != 0
931 && (insn
->membership
& INSN_ISA_MASK
) != 0
932 && ((mips_isa_table
[(isa
& INSN_ISA_MASK
) - 1]
933 >> ((insn
->membership
& INSN_ISA_MASK
) - 1)) & 1) != 0)
936 /* Test for ASE compatibility. */
937 if ((ase
& insn
->ase
) != 0)
940 /* Test for processor-specific extensions. */
941 if (cpu_is_member (cpu
, insn
->membership
))
947 /* This is a list of macro expanded instructions.
949 _I appended means immediate
950 _A appended means target address of a jump
951 _AB appended means address with (possibly zero) base register
952 _D appended means 64 bit floating point constant
953 _S appended means 32 bit floating point constant. */
1208 /* The order of overloaded instructions matters. Label arguments and
1209 register arguments look the same. Instructions that can have either
1210 for arguments must apear in the correct order in this table for the
1211 assembler to pick the right one. In other words, entries with
1212 immediate operands must apear after the same instruction with
1215 Many instructions are short hand for other instructions (i.e., The
1216 jal <register> instruction is short for jalr <register>). */
1218 extern const struct mips_opcode mips_builtin_opcodes
[];
1219 extern const int bfd_mips_num_builtin_opcodes
;
1220 extern struct mips_opcode
*mips_opcodes
;
1221 extern int bfd_mips_num_opcodes
;
1222 #define NUMOPCODES bfd_mips_num_opcodes
1225 /* The rest of this file adds definitions for the mips16 TinyRISC
1228 /* These are the bitmasks and shift counts used for the different
1229 fields in the instruction formats. Other than OP, no masks are
1230 provided for the fixed portions of an instruction, since they are
1233 The I format uses IMM11.
1235 The RI format uses RX and IMM8.
1237 The RR format uses RX, and RY.
1239 The RRI format uses RX, RY, and IMM5.
1241 The RRR format uses RX, RY, and RZ.
1243 The RRI_A format uses RX, RY, and IMM4.
1245 The SHIFT format uses RX, RY, and SHAMT.
1247 The I8 format uses IMM8.
1249 The I8_MOVR32 format uses RY and REGR32.
1251 The IR_MOV32R format uses REG32R and MOV32Z.
1253 The I64 format uses IMM8.
1255 The RI64 format uses RY and IMM5.
1258 #define MIPS16OP_MASK_OP 0x1f
1259 #define MIPS16OP_SH_OP 11
1260 #define MIPS16OP_MASK_IMM11 0x7ff
1261 #define MIPS16OP_SH_IMM11 0
1262 #define MIPS16OP_MASK_RX 0x7
1263 #define MIPS16OP_SH_RX 8
1264 #define MIPS16OP_MASK_IMM8 0xff
1265 #define MIPS16OP_SH_IMM8 0
1266 #define MIPS16OP_MASK_RY 0x7
1267 #define MIPS16OP_SH_RY 5
1268 #define MIPS16OP_MASK_IMM5 0x1f
1269 #define MIPS16OP_SH_IMM5 0
1270 #define MIPS16OP_MASK_RZ 0x7
1271 #define MIPS16OP_SH_RZ 2
1272 #define MIPS16OP_MASK_IMM4 0xf
1273 #define MIPS16OP_SH_IMM4 0
1274 #define MIPS16OP_MASK_REGR32 0x1f
1275 #define MIPS16OP_SH_REGR32 0
1276 #define MIPS16OP_MASK_REG32R 0x1f
1277 #define MIPS16OP_SH_REG32R 3
1278 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1279 #define MIPS16OP_MASK_MOVE32Z 0x7
1280 #define MIPS16OP_SH_MOVE32Z 0
1281 #define MIPS16OP_MASK_IMM6 0x3f
1282 #define MIPS16OP_SH_IMM6 5
1284 /* These are the characters which may appears in the args field of a MIPS16
1285 instruction. They appear in the order in which the fields appear when the
1286 instruction is used. Commas and parentheses in the args string are ignored
1287 when assembling, and written into the output when disassembling.
1289 "y" 3 bit register (MIPS16OP_*_RY)
1290 "x" 3 bit register (MIPS16OP_*_RX)
1291 "z" 3 bit register (MIPS16OP_*_RZ)
1292 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1293 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1294 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1295 "0" zero register ($0)
1296 "S" stack pointer ($sp or $29)
1298 "R" return address register ($ra or $31)
1299 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1300 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1301 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1302 "a" 26 bit jump address
1303 "i" likewise, but flips bit 0
1304 "e" 11 bit extension value
1305 "l" register list for entry instruction
1306 "L" register list for exit instruction
1308 The remaining codes may be extended. Except as otherwise noted,
1309 the full extended operand is a 16 bit signed value.
1310 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1311 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1312 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1313 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1314 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1315 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1316 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1317 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1318 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1319 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1320 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1321 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1322 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1323 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1324 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1325 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1326 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1327 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1328 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1329 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1330 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1331 "m" 7 bit register list for save instruction (18 bit extended)
1332 "M" 7 bit register list for restore instruction (18 bit extended)
1335 /* Save/restore encoding for the args field when all 4 registers are
1336 either saved as arguments or saved/restored as statics. */
1337 #define MIPS16_ALL_ARGS 0xe
1338 #define MIPS16_ALL_STATICS 0xb
1340 /* For the mips16, we use the same opcode table format and a few of
1341 the same flags. However, most of the flags are different. */
1343 /* Modifies the register in MIPS16OP_*_RX. */
1344 #define MIPS16_INSN_WRITE_X 0x00000001
1345 /* Modifies the register in MIPS16OP_*_RY. */
1346 #define MIPS16_INSN_WRITE_Y 0x00000002
1347 /* Modifies the register in MIPS16OP_*_RZ. */
1348 #define MIPS16_INSN_WRITE_Z 0x00000004
1349 /* Modifies the T ($24) register. */
1350 #define MIPS16_INSN_WRITE_T 0x00000008
1351 /* Modifies the SP ($29) register. */
1352 #define MIPS16_INSN_WRITE_SP 0x00000010
1353 /* Modifies the RA ($31) register. */
1354 #define MIPS16_INSN_WRITE_31 0x00000020
1355 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1356 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1357 /* Reads the register in MIPS16OP_*_RX. */
1358 #define MIPS16_INSN_READ_X 0x00000080
1359 /* Reads the register in MIPS16OP_*_RY. */
1360 #define MIPS16_INSN_READ_Y 0x00000100
1361 /* Reads the register in MIPS16OP_*_MOVE32Z. */
1362 #define MIPS16_INSN_READ_Z 0x00000200
1363 /* Reads the T ($24) register. */
1364 #define MIPS16_INSN_READ_T 0x00000400
1365 /* Reads the SP ($29) register. */
1366 #define MIPS16_INSN_READ_SP 0x00000800
1367 /* Reads the RA ($31) register. */
1368 #define MIPS16_INSN_READ_31 0x00001000
1369 /* Reads the program counter. */
1370 #define MIPS16_INSN_READ_PC 0x00002000
1371 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
1372 #define MIPS16_INSN_READ_GPR_X 0x00004000
1373 /* Is an unconditional branch insn. */
1374 #define MIPS16_INSN_UNCOND_BRANCH 0x00008000
1375 /* Is a conditional branch insn. */
1376 #define MIPS16_INSN_COND_BRANCH 0x00010000
1378 /* The following flags have the same value for the mips16 opcode
1383 INSN_UNCOND_BRANCH_DELAY
1384 INSN_COND_BRANCH_DELAY
1385 INSN_COND_BRANCH_LIKELY (never used)
1394 extern const struct mips_opcode mips16_opcodes
[];
1395 extern const int bfd_mips16_num_opcodes
;
1397 /* These are the bit masks and shift counts used for the different fields
1398 in the microMIPS instruction formats. No masks are provided for the
1399 fixed portions of an instruction, since they are not needed. */
1401 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff
1402 #define MICROMIPSOP_SH_IMMEDIATE 0
1403 #define MICROMIPSOP_MASK_DELTA 0xffff
1404 #define MICROMIPSOP_SH_DELTA 0
1405 #define MICROMIPSOP_MASK_CODE10 0x3ff
1406 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
1407 #define MICROMIPSOP_MASK_TRAP 0xf
1408 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
1409 #define MICROMIPSOP_MASK_SHAMT 0x1f
1410 #define MICROMIPSOP_SH_SHAMT 11
1411 #define MICROMIPSOP_MASK_TARGET 0x3ffffff
1412 #define MICROMIPSOP_SH_TARGET 0
1413 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
1414 #define MICROMIPSOP_SH_EXTLSB 6
1415 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
1416 #define MICROMIPSOP_SH_EXTMSBD 11
1417 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
1418 #define MICROMIPSOP_SH_INSMSB 11
1419 #define MICROMIPSOP_MASK_CODE 0x3ff
1420 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
1421 #define MICROMIPSOP_MASK_CODE2 0x3ff
1422 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
1423 #define MICROMIPSOP_MASK_CACHE 0x1f
1424 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
1425 #define MICROMIPSOP_MASK_SEL 0x7
1426 #define MICROMIPSOP_SH_SEL 11
1427 #define MICROMIPSOP_MASK_OFFSET12 0xfff
1428 #define MICROMIPSOP_SH_OFFSET12 0
1429 #define MICROMIPSOP_MASK_3BITPOS 0x7
1430 #define MICROMIPSOP_SH_3BITPOS 21
1431 #define MICROMIPSOP_MASK_STYPE 0x1f
1432 #define MICROMIPSOP_SH_STYPE 16
1433 #define MICROMIPSOP_MASK_OFFSET10 0x3ff
1434 #define MICROMIPSOP_SH_OFFSET10 6
1435 #define MICROMIPSOP_MASK_RS 0x1f
1436 #define MICROMIPSOP_SH_RS 16
1437 #define MICROMIPSOP_MASK_RT 0x1f
1438 #define MICROMIPSOP_SH_RT 21
1439 #define MICROMIPSOP_MASK_RD 0x1f
1440 #define MICROMIPSOP_SH_RD 11
1441 #define MICROMIPSOP_MASK_FS 0x1f
1442 #define MICROMIPSOP_SH_FS 16
1443 #define MICROMIPSOP_MASK_FT 0x1f
1444 #define MICROMIPSOP_SH_FT 21
1445 #define MICROMIPSOP_MASK_FD 0x1f
1446 #define MICROMIPSOP_SH_FD 11
1447 #define MICROMIPSOP_MASK_FR 0x1f
1448 #define MICROMIPSOP_SH_FR 6
1449 #define MICROMIPSOP_MASK_RS3 0x1f
1450 #define MICROMIPSOP_SH_RS3 6
1451 #define MICROMIPSOP_MASK_PREFX 0x1f
1452 #define MICROMIPSOP_SH_PREFX 11
1453 #define MICROMIPSOP_MASK_BCC 0x7
1454 #define MICROMIPSOP_SH_BCC 18
1455 #define MICROMIPSOP_MASK_CCC 0x7
1456 #define MICROMIPSOP_SH_CCC 13
1457 #define MICROMIPSOP_MASK_COPZ 0x7fffff
1458 #define MICROMIPSOP_SH_COPZ 3
1460 #define MICROMIPSOP_MASK_MB 0x7
1461 #define MICROMIPSOP_SH_MB 23
1462 #define MICROMIPSOP_MASK_MC 0x7
1463 #define MICROMIPSOP_SH_MC 4
1464 #define MICROMIPSOP_MASK_MD 0x7
1465 #define MICROMIPSOP_SH_MD 7
1466 #define MICROMIPSOP_MASK_ME 0x7
1467 #define MICROMIPSOP_SH_ME 1
1468 #define MICROMIPSOP_MASK_MF 0x7
1469 #define MICROMIPSOP_SH_MF 3
1470 #define MICROMIPSOP_MASK_MG 0x7
1471 #define MICROMIPSOP_SH_MG 0
1472 #define MICROMIPSOP_MASK_MH 0x7
1473 #define MICROMIPSOP_SH_MH 7
1474 #define MICROMIPSOP_MASK_MJ 0x1f
1475 #define MICROMIPSOP_SH_MJ 0
1476 #define MICROMIPSOP_MASK_ML 0x7
1477 #define MICROMIPSOP_SH_ML 4
1478 #define MICROMIPSOP_MASK_MM 0x7
1479 #define MICROMIPSOP_SH_MM 1
1480 #define MICROMIPSOP_MASK_MN 0x7
1481 #define MICROMIPSOP_SH_MN 4
1482 #define MICROMIPSOP_MASK_MP 0x1f
1483 #define MICROMIPSOP_SH_MP 5
1484 #define MICROMIPSOP_MASK_MQ 0x7
1485 #define MICROMIPSOP_SH_MQ 7
1487 #define MICROMIPSOP_MASK_IMMA 0x7f
1488 #define MICROMIPSOP_SH_IMMA 0
1489 #define MICROMIPSOP_MASK_IMMB 0x7
1490 #define MICROMIPSOP_SH_IMMB 1
1491 #define MICROMIPSOP_MASK_IMMC 0xf
1492 #define MICROMIPSOP_SH_IMMC 0
1493 #define MICROMIPSOP_MASK_IMMD 0x3ff
1494 #define MICROMIPSOP_SH_IMMD 0
1495 #define MICROMIPSOP_MASK_IMME 0x7f
1496 #define MICROMIPSOP_SH_IMME 0
1497 #define MICROMIPSOP_MASK_IMMF 0xf
1498 #define MICROMIPSOP_SH_IMMF 0
1499 #define MICROMIPSOP_MASK_IMMG 0xf
1500 #define MICROMIPSOP_SH_IMMG 0
1501 #define MICROMIPSOP_MASK_IMMH 0xf
1502 #define MICROMIPSOP_SH_IMMH 0
1503 #define MICROMIPSOP_MASK_IMMI 0x7f
1504 #define MICROMIPSOP_SH_IMMI 0
1505 #define MICROMIPSOP_MASK_IMMJ 0xf
1506 #define MICROMIPSOP_SH_IMMJ 0
1507 #define MICROMIPSOP_MASK_IMML 0xf
1508 #define MICROMIPSOP_SH_IMML 0
1509 #define MICROMIPSOP_MASK_IMMM 0x7
1510 #define MICROMIPSOP_SH_IMMM 1
1511 #define MICROMIPSOP_MASK_IMMN 0x3
1512 #define MICROMIPSOP_SH_IMMN 4
1513 #define MICROMIPSOP_MASK_IMMO 0xf
1514 #define MICROMIPSOP_SH_IMMO 0
1515 #define MICROMIPSOP_MASK_IMMP 0x1f
1516 #define MICROMIPSOP_SH_IMMP 0
1517 #define MICROMIPSOP_MASK_IMMQ 0x7fffff
1518 #define MICROMIPSOP_SH_IMMQ 0
1519 #define MICROMIPSOP_MASK_IMMU 0x1f
1520 #define MICROMIPSOP_SH_IMMU 0
1521 #define MICROMIPSOP_MASK_IMMW 0x3f
1522 #define MICROMIPSOP_SH_IMMW 1
1523 #define MICROMIPSOP_MASK_IMMX 0xf
1524 #define MICROMIPSOP_SH_IMMX 1
1525 #define MICROMIPSOP_MASK_IMMY 0x1ff
1526 #define MICROMIPSOP_SH_IMMY 1
1529 #define MICROMIPSOP_MASK_DSPACC 0x3
1530 #define MICROMIPSOP_SH_DSPACC 14
1531 #define MICROMIPSOP_MASK_DSPSFT 0x3f
1532 #define MICROMIPSOP_SH_DSPSFT 16
1533 #define MICROMIPSOP_MASK_SA3 0x7
1534 #define MICROMIPSOP_SH_SA3 13
1535 #define MICROMIPSOP_MASK_SA4 0xf
1536 #define MICROMIPSOP_SH_SA4 12
1537 #define MICROMIPSOP_MASK_IMM8 0xff
1538 #define MICROMIPSOP_SH_IMM8 13
1539 #define MICROMIPSOP_MASK_IMM10 0x3ff
1540 #define MICROMIPSOP_SH_IMM10 16
1541 #define MICROMIPSOP_MASK_WRDSP 0x3f
1542 #define MICROMIPSOP_SH_WRDSP 14
1543 #define MICROMIPSOP_MASK_BP 0x3
1544 #define MICROMIPSOP_SH_BP 14
1546 /* Placeholders for fields that only exist in the traditional 32-bit
1547 instruction encoding; see the comment above for details. */
1548 #define MICROMIPSOP_MASK_CODE20 0
1549 #define MICROMIPSOP_SH_CODE20 0
1550 #define MICROMIPSOP_MASK_PERFREG 0
1551 #define MICROMIPSOP_SH_PERFREG 0
1552 #define MICROMIPSOP_MASK_CODE19 0
1553 #define MICROMIPSOP_SH_CODE19 0
1554 #define MICROMIPSOP_MASK_ALN 0
1555 #define MICROMIPSOP_SH_ALN 0
1556 #define MICROMIPSOP_MASK_VECBYTE 0
1557 #define MICROMIPSOP_SH_VECBYTE 0
1558 #define MICROMIPSOP_MASK_VECALIGN 0
1559 #define MICROMIPSOP_SH_VECALIGN 0
1560 #define MICROMIPSOP_MASK_DSPACC_S 0
1561 #define MICROMIPSOP_SH_DSPACC_S 0
1562 #define MICROMIPSOP_MASK_DSPSFT_7 0
1563 #define MICROMIPSOP_SH_DSPSFT_7 0
1564 #define MICROMIPSOP_MASK_RDDSP 0
1565 #define MICROMIPSOP_SH_RDDSP 0
1566 #define MICROMIPSOP_MASK_MT_U 0
1567 #define MICROMIPSOP_SH_MT_U 0
1568 #define MICROMIPSOP_MASK_MT_H 0
1569 #define MICROMIPSOP_SH_MT_H 0
1570 #define MICROMIPSOP_MASK_MTACC_T 0
1571 #define MICROMIPSOP_SH_MTACC_T 0
1572 #define MICROMIPSOP_MASK_MTACC_D 0
1573 #define MICROMIPSOP_SH_MTACC_D 0
1574 #define MICROMIPSOP_MASK_BBITIND 0
1575 #define MICROMIPSOP_SH_BBITIND 0
1576 #define MICROMIPSOP_MASK_CINSPOS 0
1577 #define MICROMIPSOP_SH_CINSPOS 0
1578 #define MICROMIPSOP_MASK_CINSLM1 0
1579 #define MICROMIPSOP_SH_CINSLM1 0
1580 #define MICROMIPSOP_MASK_SEQI 0
1581 #define MICROMIPSOP_SH_SEQI 0
1582 #define MICROMIPSOP_SH_OFFSET_A 0
1583 #define MICROMIPSOP_MASK_OFFSET_A 0
1584 #define MICROMIPSOP_SH_OFFSET_B 0
1585 #define MICROMIPSOP_MASK_OFFSET_B 0
1586 #define MICROMIPSOP_SH_OFFSET_C 0
1587 #define MICROMIPSOP_MASK_OFFSET_C 0
1588 #define MICROMIPSOP_SH_RZ 0
1589 #define MICROMIPSOP_MASK_RZ 0
1590 #define MICROMIPSOP_SH_FZ 0
1591 #define MICROMIPSOP_MASK_FZ 0
1593 /* microMIPS Enhanced VA Scheme */
1594 #define MICROMIPSOP_SH_EVAOFFSET 0
1595 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
1597 /* These are the characters which may appears in the args field of a microMIPS
1598 instruction. They appear in the order in which the fields appear
1599 when the instruction is used. Commas and parentheses in the args
1600 string are ignored when assembling, and written into the output
1603 The followings are for 16-bit microMIPS instructions.
1606 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1607 The same register used as both source and target.
1608 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1609 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1610 The same register used as both source and target.
1611 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1612 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1613 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
1614 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1615 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1616 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1617 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1618 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1619 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1620 "mr" must be program counter
1622 "mt" must be the same as the previous register
1623 "mx" must be the same as the destination register
1627 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1628 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1629 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1630 32768, 65535) (MICROMIPSOP_*_IMMC)
1631 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1632 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1633 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
1634 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1635 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1636 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1637 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1638 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1639 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1640 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1641 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1642 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1643 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1644 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1645 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1646 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1649 In most cases 32-bit microMIPS instructions use the same characters
1650 as MIPS (with ADDIUPC being a notable exception, but there are some
1653 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1654 "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
1655 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1656 ">" shift amount between 32 and 63, stored after subtracting 32
1657 (MICROMIPSOP_*_SHAMT)
1658 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1659 "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1660 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1661 "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1662 "+i" likewise, but flips bit 0
1663 "b" 5-bit base register (MICROMIPSOP_*_RS)
1664 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1665 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1666 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1667 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1668 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1669 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1670 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1671 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1672 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1673 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1674 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1675 "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1676 "t" 5-bit target register (MICROMIPSOP_*_RT)
1677 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1678 "v" 5-bit same register used as both source and destination
1680 "w" 5-bit same register used as both target and destination
1682 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1683 "z" must be zero register
1684 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1685 "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1686 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1688 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1689 LSB (MICROMIPSOP_*_EXTLSB).
1690 Enforces: 0 <= pos < 32.
1691 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1692 Requires that "+A" or "+E" occur first to set position.
1693 Enforces: 0 < (pos+size) <= 32.
1694 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1695 Requires that "+A" or "+E" occur first to set position.
1696 Enforces: 0 < (pos+size) <= 32.
1697 (Also used by DEXT w/ different limits, but limits for
1698 that are checked by the M_DEXT macro.)
1699 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1700 Enforces: 32 <= pos < 64.
1701 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1702 Requires that "+A" or "+E" occur first to set position.
1703 Enforces: 32 < (pos+size) <= 64.
1704 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1705 Requires that "+A" or "+E" occur first to set position.
1706 Enforces: 32 < (pos+size) <= 64.
1707 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1708 Requires that "+A" or "+E" occur first to set position.
1709 Enforces: 32 < (pos+size) <= 64.
1711 PC-relative addition (ADDIUPC) instruction:
1712 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1713 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1715 Floating point instructions:
1716 "D" 5-bit destination register (MICROMIPSOP_*_FD)
1717 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1718 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1719 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1720 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1721 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1722 "V" 5-bit same register used as floating source and destination or target
1725 Coprocessor instructions:
1726 "E" 5-bit target register (MICROMIPSOP_*_RT)
1727 "G" 5-bit source register (MICROMIPSOP_*_RS)
1728 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1731 "A" general 32 bit expression
1732 "I" 32-bit immediate (value placed in imm_expr).
1733 "+I" 32-bit immediate (value placed in imm2_expr).
1734 "F" 64-bit floating point constant in .rdata
1735 "L" 64-bit floating point constant in .lit8
1736 "f" 32-bit floating point constant
1737 "l" 32-bit floating point constant in .lit4
1740 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
1741 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
1742 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
1743 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
1744 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
1745 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
1746 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
1747 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
1748 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
1749 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
1751 microMIPS Enhanced VA Scheme:
1752 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
1755 "()" parens surrounding optional value
1756 "," separates operands
1757 "+" start of extension sequence
1758 "m" start of microMIPS extension sequence
1760 Characters used so far, for quick reference when adding more:
1763 "ABCDEFGHI KLMN RST V "
1764 "abcd f hijklmnopqrstuvw yz"
1766 Extension character sequences used so far ("+" followed by the
1767 following), for quick reference when adding more:
1773 Extension character sequences used so far ("m" followed by the
1774 following), for quick reference when adding more:
1777 " BCDEFGHIJ LMNOPQ U WXYZ"
1778 " bcdefghij lmn pq st xyz"
1781 extern const struct mips_opcode micromips_opcodes
[];
1782 extern const int bfd_micromips_num_opcodes
;
1784 /* A NOP insn impemented as "or at,at,zero".
1785 Used to implement -mfix-loongson2f. */
1786 #define LOONGSON2F_NOP_INSN 0x00200825
1788 #endif /* _MIPS_H_ */
projects / deliverable / binutils-gdb.git / blob