1 /* Nios II opcode list for GAS, the GNU assembler.
2 Copyright (C) 2012, 2013 Free Software Foundation, Inc.
3 Contributed by Nigel Gray (ngray@altera.com).
4 Contributed by Mentor Graphics, Inc.
6 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
8 GAS/GDB is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS/GDB is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS or GDB; see the file COPYING3. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
28 /****************************************************************************
29 * This file contains structures, bit masks and shift counts used
30 * by the GNU toolchain to define the Nios II instruction set and
31 * access various opcode fields.
32 ****************************************************************************/
34 /* Identify different overflow situations for error messages. */
37 call_target_overflow
= 0,
38 branch_target_overflow
,
39 address_offset_overflow
,
40 signed_immed16_overflow
,
41 unsigned_immed16_overflow
,
42 unsigned_immed5_overflow
,
43 custom_opcode_overflow
,
47 /* This structure holds information for a particular instruction.
49 The args field is a string describing the operands. The following
50 letters can appear in the args:
51 c - a 5-bit control register index or break opcode
52 d - a 5-bit destination register index
53 s - a 5-bit left source register index
54 t - a 5-bit right source register index
55 i - a 16-bit signed immediate
56 u - a 16-bit unsigned immediate
57 j - a 5-bit unsigned immediate
58 k - a 6-bit unsigned immediate
59 l - an 8-bit unsigned immediate
60 m - a 26-bit unsigned immediate
61 Literal ',', '(', and ')' characters may also appear in the args as
64 The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection
65 of bits describing the instruction, notably any relevant hazard
68 When assembling, the match field contains the opcode template, which
69 is modified by the arguments to produce the actual opcode
70 that is emitted. If pinfo is INSN_MACRO, then this is 0.
72 If pinfo is INSN_MACRO, the mask field stores the macro identifier.
73 Otherwise this is a bit mask for the relevant portions of the opcode
74 when disassembling. If the actual opcode anded with the match field
75 equals the opcode field, then we have found the correct instruction. */
79 const char *name
; /* The name of the instruction. */
80 const char *args
; /* A string describing the arguments for this
82 const char *args_test
; /* Like args, but with an extra argument for
83 the expected opcode. */
84 unsigned long num_args
; /* The number of arguments the instruction
86 unsigned long match
; /* The basic opcode for the instruction. */
87 unsigned long mask
; /* Mask for the opcode field of the
89 unsigned long pinfo
; /* Is this a real instruction or instruction
91 enum overflow_type overflow_msg
; /* Used to generate informative
92 message when fixup overflows. */
95 /* This value is used in the nios2_opcode.pinfo field to indicate that the
96 instruction is a macro or pseudo-op. This requires special treatment by
97 the assembler, and is used by the disassembler to determine whether to
99 #define NIOS2_INSN_MACRO 0x80000000
100 #define NIOS2_INSN_MACRO_MOV 0x80000001
101 #define NIOS2_INSN_MACRO_MOVI 0x80000002
102 #define NIOS2_INSN_MACRO_MOVIA 0x80000004
104 #define NIOS2_INSN_RELAXABLE 0x40000000
105 #define NIOS2_INSN_UBRANCH 0x00000010
106 #define NIOS2_INSN_CBRANCH 0x00000020
107 #define NIOS2_INSN_CALL 0x00000040
109 #define NIOS2_INSN_ADDI 0x00000080
110 #define NIOS2_INSN_ANDI 0x00000100
111 #define NIOS2_INSN_ORI 0x00000200
112 #define NIOS2_INSN_XORI 0x00000400
115 /* Associates a register name ($6) with a 5-bit index (eg 6). */
123 /* These are bit masks and shift counts for accessing the various
124 fields of a Nios II instruction. */
126 /* Macros for getting and setting an instruction field. */
127 #define GET_INSN_FIELD(X, i) \
128 (((i) & OP_MASK_##X) >> OP_SH_##X)
129 #define SET_INSN_FIELD(X, i, j) \
130 ((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X)))
132 /* Instruction field definitions. */
136 #define IW_A_MASK 0x1f
141 #define IW_B_MASK 0x1f
146 #define IW_C_MASK 0x1f
148 #define IW_IMM16_LSB 6
149 #define IW_IMM16_MSB 21
150 #define IW_IMM16_SZ 16
151 #define IW_IMM16_MASK 0xffff
153 #define IW_IMM26_LSB 6
154 #define IW_IMM26_MSB 31
155 #define IW_IMM26_SZ 26
156 #define IW_IMM26_MASK 0x3ffffff
161 #define IW_OP_MASK 0x3f
163 #define IW_OPX_LSB 11
164 #define IW_OPX_MSB 16
166 #define IW_OPX_MASK 0x3f
168 #define IW_SHIFT_IMM5_LSB 6
169 #define IW_SHIFT_IMM5_MSB 10
170 #define IW_SHIFT_IMM5_SZ 5
171 #define IW_SHIFT_IMM5_MASK 0x1f
173 #define IW_CONTROL_REGNUM_LSB 6
174 #define IW_CONTROL_REGNUM_MSB 9
175 #define IW_CONTROL_REGNUM_SZ 4
176 #define IW_CONTROL_REGNUM_MASK 0xf
178 /* Operator mask and shift. */
179 #define OP_MASK_OP (IW_OP_MASK << IW_OP_LSB)
180 #define OP_SH_OP IW_OP_LSB
182 /* Masks and shifts for I-type instructions. */
183 #define OP_MASK_IOP (IW_OP_MASK << IW_OP_LSB)
184 #define OP_SH_IOP IW_OP_LSB
186 #define OP_MASK_IMM16 (IW_IMM16_MASK << IW_IMM16_LSB)
187 #define OP_SH_IMM16 IW_IMM16_LSB
189 #define OP_MASK_IRD (IW_B_MASK << IW_B_LSB)
190 #define OP_SH_IRD IW_B_LSB /* The same as T for I-type. */
192 #define OP_MASK_IRT (IW_B_MASK << IW_B_LSB)
193 #define OP_SH_IRT IW_B_LSB
195 #define OP_MASK_IRS (IW_A_MASK << IW_A_LSB)
196 #define OP_SH_IRS IW_A_LSB
198 /* Masks and shifts for R-type instructions. */
199 #define OP_MASK_ROP (IW_OP_MASK << IW_OP_LSB)
200 #define OP_SH_ROP IW_OP_LSB
202 #define OP_MASK_ROPX (IW_OPX_MASK << IW_OPX_LSB)
203 #define OP_SH_ROPX IW_OPX_LSB
205 #define OP_MASK_RRD (IW_C_MASK << IW_C_LSB)
206 #define OP_SH_RRD IW_C_LSB
208 #define OP_MASK_RRT (IW_B_MASK << IW_B_LSB)
209 #define OP_SH_RRT IW_B_LSB
211 #define OP_MASK_RRS (IW_A_MASK << IW_A_LSB)
212 #define OP_SH_RRS IW_A_LSB
214 /* Masks and shifts for J-type instructions. */
215 #define OP_MASK_JOP (IW_OP_MASK << IW_OP_LSB)
216 #define OP_SH_JOP IW_OP_LSB
218 #define OP_MASK_IMM26 (IW_IMM26_MASK << IW_IMM26_LSB)
219 #define OP_SH_IMM26 IW_IMM26_LSB
221 /* Masks and shifts for CTL instructions. */
222 #define OP_MASK_RCTL 0x000007c0
225 /* Break instruction imm5 field. */
226 #define OP_MASK_TRAP_IMM5 0x000007c0
227 #define OP_SH_TRAP_IMM5 6
229 /* Instruction imm5 field. */
230 #define OP_MASK_IMM5 (IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB)
231 #define OP_SH_IMM5 IW_SHIFT_IMM5_LSB
233 /* Cache operation fields (type j,i(s)). */
234 #define OP_MASK_CACHE_OPX (IW_B_MASK << IW_B_LSB)
235 #define OP_SH_CACHE_OPX IW_B_LSB
236 #define OP_MASK_CACHE_RRS (IW_A_MASK << IW_A_LSB)
237 #define OP_SH_CACHE_RRS IW_A_LSB
239 /* Custom instruction masks. */
240 #define OP_MASK_CUSTOM_A 0x00010000
241 #define OP_SH_CUSTOM_A 16
243 #define OP_MASK_CUSTOM_B 0x00008000
244 #define OP_SH_CUSTOM_B 15
246 #define OP_MASK_CUSTOM_C 0x00004000
247 #define OP_SH_CUSTOM_C 14
249 #define OP_MASK_CUSTOM_N 0x00003fc0
250 #define OP_SH_CUSTOM_N 6
251 #define OP_MAX_CUSTOM_N 255
253 /* OP instruction values. */
267 #define OP_CMPGEUI 40
269 #define OP_CMPLTUI 48
273 #define OP_FLUSHDA 27
303 /* OPX instruction values. */
311 #define OPX_CMPGEU 40
313 #define OPX_CMPLTU 48
319 #define OPX_FLUSHI 12
321 #define OPX_HBREAK 53
326 #define OPX_MULXSS 31
327 #define OPX_MULXSU 23
329 #define OPX_NEXTPC 28
350 /* The following macros define the opcode matches for each
351 instruction code & OP_MASK_INST == OP_MATCH_INST. */
353 /* OP instruction matches. */
354 #define OP_MATCH_ADDI OP_ADDI
355 #define OP_MATCH_ANDHI OP_ANDHI
356 #define OP_MATCH_ANDI OP_ANDI
357 #define OP_MATCH_BEQ OP_BEQ
358 #define OP_MATCH_BGE OP_BGE
359 #define OP_MATCH_BGEU OP_BGEU
360 #define OP_MATCH_BLT OP_BLT
361 #define OP_MATCH_BLTU OP_BLTU
362 #define OP_MATCH_BNE OP_BNE
363 #define OP_MATCH_BR OP_BR
364 #define OP_MATCH_FLUSHD OP_FLUSHD
365 #define OP_MATCH_FLUSHDA OP_FLUSHDA
366 #define OP_MATCH_INITD OP_INITD
367 #define OP_MATCH_INITDA OP_INITDA
368 #define OP_MATCH_CALL OP_CALL
369 #define OP_MATCH_CMPEQI OP_CMPEQI
370 #define OP_MATCH_CMPGEI OP_CMPGEI
371 #define OP_MATCH_CMPGEUI OP_CMPGEUI
372 #define OP_MATCH_CMPLTI OP_CMPLTI
373 #define OP_MATCH_CMPLTUI OP_CMPLTUI
374 #define OP_MATCH_CMPNEI OP_CMPNEI
375 #define OP_MATCH_JMPI OP_JMPI
376 #define OP_MATCH_LDB OP_LDB
377 #define OP_MATCH_LDBIO OP_LDBIO
378 #define OP_MATCH_LDBU OP_LDBU
379 #define OP_MATCH_LDBUIO OP_LDBUIO
380 #define OP_MATCH_LDH OP_LDH
381 #define OP_MATCH_LDHIO OP_LDHIO
382 #define OP_MATCH_LDHU OP_LDHU
383 #define OP_MATCH_LDHUIO OP_LDHUIO
384 #define OP_MATCH_LDL OP_LDL
385 #define OP_MATCH_LDW OP_LDW
386 #define OP_MATCH_LDWIO OP_LDWIO
387 #define OP_MATCH_MULI OP_MULI
388 #define OP_MATCH_OPX OP_OPX
389 #define OP_MATCH_ORHI OP_ORHI
390 #define OP_MATCH_ORI OP_ORI
391 #define OP_MATCH_RDPRS OP_RDPRS
392 #define OP_MATCH_STB OP_STB
393 #define OP_MATCH_STBIO OP_STBIO
394 #define OP_MATCH_STC OP_STC
395 #define OP_MATCH_STH OP_STH
396 #define OP_MATCH_STHIO OP_STHIO
397 #define OP_MATCH_STW OP_STW
398 #define OP_MATCH_STWIO OP_STWIO
399 #define OP_MATCH_CUSTOM OP_CUSTOM
400 #define OP_MATCH_XORHI OP_XORHI
401 #define OP_MATCH_XORI OP_XORI
402 #define OP_MATCH_OPX OP_OPX
404 /* OPX instruction values. */
405 #define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX)
407 #define OP_MATCH_ADD OPX_MATCH (OPX_ADD)
408 #define OP_MATCH_AND OPX_MATCH (OPX_AND)
409 #define OP_MATCH_BREAK ((0x1e << 17) | OPX_MATCH (OPX_BREAK))
410 #define OP_MATCH_BRET (0xf0000000 | OPX_MATCH (OPX_BRET))
411 #define OP_MATCH_CALLR ((0x1f << 17) | OPX_MATCH (OPX_CALLR))
412 #define OP_MATCH_CMPEQ OPX_MATCH (OPX_CMPEQ)
413 #define OP_MATCH_CMPGE OPX_MATCH (OPX_CMPGE)
414 #define OP_MATCH_CMPGEU OPX_MATCH (OPX_CMPGEU)
415 #define OP_MATCH_CMPLT OPX_MATCH (OPX_CMPLT)
416 #define OP_MATCH_CMPLTU OPX_MATCH (OPX_CMPLTU)
417 #define OP_MATCH_CMPNE OPX_MATCH (OPX_CMPNE)
418 #define OP_MATCH_DIV OPX_MATCH (OPX_DIV)
419 #define OP_MATCH_DIVU OPX_MATCH (OPX_DIVU)
420 #define OP_MATCH_JMP OPX_MATCH (OPX_JMP)
421 #define OP_MATCH_MUL OPX_MATCH (OPX_MUL)
422 #define OP_MATCH_MULXSS OPX_MATCH (OPX_MULXSS)
423 #define OP_MATCH_MULXSU OPX_MATCH (OPX_MULXSU)
424 #define OP_MATCH_MULXUU OPX_MATCH (OPX_MULXUU)
425 #define OP_MATCH_NEXTPC OPX_MATCH (OPX_NEXTPC)
426 #define OP_MATCH_NOR OPX_MATCH (OPX_NOR)
427 #define OP_MATCH_OR OPX_MATCH (OPX_OR)
428 #define OP_MATCH_RDCTL OPX_MATCH (OPX_RDCTL)
429 #define OP_MATCH_RET (0xf8000000 | OPX_MATCH (OPX_RET))
430 #define OP_MATCH_ROL OPX_MATCH (OPX_ROL)
431 #define OP_MATCH_ROLI OPX_MATCH (OPX_ROLI)
432 #define OP_MATCH_ROR OPX_MATCH (OPX_ROR)
433 #define OP_MATCH_SLL OPX_MATCH (OPX_SLL)
434 #define OP_MATCH_SLLI OPX_MATCH (OPX_SLLI)
435 #define OP_MATCH_SRA OPX_MATCH (OPX_SRA)
436 #define OP_MATCH_SRAI OPX_MATCH (OPX_SRAI)
437 #define OP_MATCH_SRL OPX_MATCH (OPX_SRL)
438 #define OP_MATCH_SRLI OPX_MATCH (OPX_SRLI)
439 #define OP_MATCH_SUB OPX_MATCH (OPX_SUB)
440 #define OP_MATCH_SYNC OPX_MATCH (OPX_SYNC)
441 #define OP_MATCH_TRAP ((0x1d << 17) | OPX_MATCH (OPX_TRAP))
442 #define OP_MATCH_ERET (0xe8000000 | OPX_MATCH (OPX_ERET))
443 #define OP_MATCH_WRCTL OPX_MATCH (OPX_WRCTL)
444 #define OP_MATCH_WRPRS OPX_MATCH (OPX_WRPRS)
445 #define OP_MATCH_XOR OPX_MATCH (OPX_XOR)
446 #define OP_MATCH_FLUSHI OPX_MATCH (OPX_FLUSHI)
447 #define OP_MATCH_FLUSHP OPX_MATCH (OPX_FLUSHP)
448 #define OP_MATCH_INITI OPX_MATCH (OPX_INITI)
450 /* Some unusual op masks. */
451 #define OP_MASK_BREAK ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
452 | OP_MASK_ROPX | OP_MASK_OP) \
454 #define OP_MASK_CALLR ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
456 #define OP_MASK_JMP ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
458 #define OP_MASK_SYNC ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
460 #define OP_MASK_TRAP ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
461 | OP_MASK_ROPX | OP_MASK_OP) \
463 #define OP_MASK_WRCTL ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
464 | OP_MASK_OP)) /*& 0xfffff83f */
465 #define OP_MASK_NEXTPC ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
467 #define OP_MASK_FLUSHI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
469 #define OP_MASK_INITI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
472 #define OP_MASK_ROLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
473 #define OP_MASK_SLLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
474 #define OP_MASK_SRAI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
475 #define OP_MASK_SRLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
476 #define OP_MASK_RDCTL ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
477 | OP_MASK_OP)) /*& 0xfffff83f */
480 #define OP_MASK 0xffffffff
483 /* These convenience macros to extract instruction fields are used by GDB. */
484 #define GET_IW_A(Iw) \
485 (((Iw) >> IW_A_LSB) & IW_A_MASK)
486 #define GET_IW_B(Iw) \
487 (((Iw) >> IW_B_LSB) & IW_B_MASK)
488 #define GET_IW_C(Iw) \
489 (((Iw) >> IW_C_LSB) & IW_C_MASK)
490 #define GET_IW_CONTROL_REGNUM(Iw) \
491 (((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK)
492 #define GET_IW_IMM16(Iw) \
493 (((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK)
494 #define GET_IW_IMM26(Iw) \
495 (((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK)
496 #define GET_IW_OP(Iw) \
497 (((Iw) >> IW_OP_LSB) & IW_OP_MASK)
498 #define GET_IW_OPX(Iw) \
499 (((Iw) >> IW_OPX_LSB) & IW_OPX_MASK)
501 /* These are the data structures we use to hold the instruction information. */
502 extern const struct nios2_opcode nios2_builtin_opcodes
[];
503 extern const int bfd_nios2_num_builtin_opcodes
;
504 extern struct nios2_opcode
*nios2_opcodes
;
505 extern int bfd_nios2_num_opcodes
;
507 /* These are the data structures used to hold the register information. */
508 extern const struct nios2_reg nios2_builtin_regs
[];
509 extern struct nios2_reg
*nios2_regs
;
510 extern const int nios2_num_builtin_regs
;
511 extern int nios2_num_regs
;
513 /* Machine-independent macro for number of opcodes. */
514 #define NUMOPCODES bfd_nios2_num_opcodes
515 #define NUMREGISTERS nios2_num_regs;
517 /* This is made extern so that the assembler can use it to find out
518 what instruction caused an error. */
519 extern const struct nios2_opcode
*nios2_find_opcode_hash (unsigned long);
521 #endif /* _NIOS2_H */