include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 typedef uint64_t ppc_cpu_t;
  32
  33 /* The opcode table is an array of struct powerpc_opcode.  */
  34
  35 struct powerpc_opcode
  36 {
  37   /* The opcode name.  */
  38   const char *name;
  39
  40   /* The opcode itself.  Those bits which will be filled in with
  41      operands are zeroes.  */
  42   unsigned long opcode;
  43
  44   /* The opcode mask.  This is used by the disassembler.  This is a
  45      mask containing ones indicating those bits which must match the
  46      opcode field, and zeroes indicating those bits which need not
  47      match (and are presumably filled in by operands).  */
  48   unsigned long mask;
  49
  50   /* One bit flags for the opcode.  These are used to indicate which
  51      specific processors support the instructions.  The defined values
  52      are listed below.  */
  53   ppc_cpu_t flags;
  54
  55   /* One bit flags for the opcode.  These are used to indicate which
  56      specific processors no longer support the instructions.  The defined
  57      values are listed below.  */
  58   ppc_cpu_t deprecated;
  59
  60   /* An array of operand codes.  Each code is an index into the
  61      operand table.  They appear in the order which the operands must
  62      appear in assembly code, and are terminated by a zero.  */
  63   unsigned char operands[8];
  64 };
  65
  66 /* The table itself is sorted by major opcode number, and is otherwise
  67    in the order in which the disassembler should consider
  68    instructions.  */
  69 extern const struct powerpc_opcode powerpc_opcodes[];
  70 extern const int powerpc_num_opcodes;
  71 extern const struct powerpc_opcode vle_opcodes[];
  72 extern const int vle_num_opcodes;
  73 extern const struct powerpc_opcode spe2_opcodes[];
  74 extern const int spe2_num_opcodes;
  75
  76 /* Values defined for the flags field of a struct powerpc_opcode.  */
  77
  78 /* Opcode is defined for the PowerPC architecture.  */
  79 #define PPC_OPCODE_PPC                 0x1ull
  80
  81 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  82 #define PPC_OPCODE_POWER               0x2ull
  83
  84 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  85 #define PPC_OPCODE_POWER2              0x4ull
  86
  87 /* Opcode is only defined on 64 bit architectures.  */
  88 #define PPC_OPCODE_64                  0x8ull
  89
  90 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  91    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  92    but it also supports many additional POWER instructions.  */
  93 #define PPC_OPCODE_601                0x10ull
  94
  95 /* Opcode is supported in both the Power and PowerPC architectures
  96    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
  97    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
  98    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
  99    between POWER and POWERPC.  */
 100 #define PPC_OPCODE_COMMON             0x20ull
 101
 102 /* Opcode is supported for any Power or PowerPC platform (this is
 103    for the assembler's -many option, and it eliminates duplicates).  */
 104 #define PPC_OPCODE_ANY                0x40ull
 105
 106 /* Opcode is supported as part of the 64-bit bridge.  */
 107 #define PPC_OPCODE_64_BRIDGE          0x80ull
 108
 109 /* Opcode is supported by Altivec Vector Unit */
 110 #define PPC_OPCODE_ALTIVEC           0x100ull
 111
 112 /* Opcode is supported by PowerPC 403 processor.  */
 113 #define PPC_OPCODE_403               0x200ull
 114
 115 /* Opcode is supported by PowerPC BookE processor.  */
 116 #define PPC_OPCODE_BOOKE             0x400ull
 117
 118 /* Opcode is only supported by Power4 architecture.  */
 119 #define PPC_OPCODE_POWER4            0x800ull
 120
 121 /* Opcode is only supported by e500x2 Core.
 122    This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in
 123    their comment mark opcodes so that when those instructions are used
 124    an APUinfo entry can be generated.  */
 125 #define PPC_OPCODE_SPE              0x1000ull
 126
 127 /* Opcode is supported by Integer select APU.  */
 128 #define PPC_OPCODE_ISEL             0x2000ull
 129
 130 /* Opcode is an e500 SPE floating point instruction.  */
 131 #define PPC_OPCODE_EFS              0x4000ull
 132
 133 /* Opcode is supported by branch locking APU.  */
 134 #define PPC_OPCODE_BRLOCK           0x8000ull
 135
 136 /* Opcode is supported by performance monitor APU.  */
 137 #define PPC_OPCODE_PMR             0x10000ull
 138
 139 /* Opcode is supported by cache locking APU.  */
 140 #define PPC_OPCODE_CACHELCK        0x20000ull
 141
 142 /* Opcode is supported by machine check APU.  */
 143 #define PPC_OPCODE_RFMCI           0x40000ull
 144
 145 /* Opcode is supported by PowerPC 440 processor.  */
 146 #define PPC_OPCODE_440             0x80000ull
 147
 148 /* Opcode is only supported by Power5 architecture.  */
 149 #define PPC_OPCODE_POWER5         0x100000ull
 150
 151 /* Opcode is supported by PowerPC e300 family.  */
 152 #define PPC_OPCODE_E300           0x200000ull
 153
 154 /* Opcode is only supported by Power6 architecture.  */
 155 #define PPC_OPCODE_POWER6         0x400000ull
 156
 157 /* Opcode is only supported by PowerPC Cell family.  */
 158 #define PPC_OPCODE_CELL           0x800000ull
 159
 160 /* Opcode is supported by CPUs with paired singles support.  */
 161 #define PPC_OPCODE_PPCPS         0x1000000ull
 162
 163 /* Opcode is supported by Power E500MC */
 164 #define PPC_OPCODE_E500MC        0x2000000ull
 165
 166 /* Opcode is supported by PowerPC 405 processor.  */
 167 #define PPC_OPCODE_405           0x4000000ull
 168
 169 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 170 #define PPC_OPCODE_VSX           0x8000000ull
 171
 172 /* Opcode is only supported by Power7 architecture.  */
 173 #define PPC_OPCODE_POWER7       0x10000000ull
 174
 175 /* Opcode is supported by A2.  */
 176 #define PPC_OPCODE_A2           0x20000000ull
 177
 178 /* Opcode is supported by PowerPC 476 processor.  */
 179 #define PPC_OPCODE_476          0x40000000ull
 180
 181 /* Opcode is supported by AppliedMicro Titan core */
 182 #define PPC_OPCODE_TITAN        0x80000000ull
 183
 184 /* Opcode which is supported by the e500 family */
 185 #define PPC_OPCODE_E500        0x100000000ull
 186
 187 /* Opcode is supported by Power E6500 */
 188 #define PPC_OPCODE_E6500       0x200000000ull
 189
 190 /* Opcode is supported by Thread management APU */
 191 #define PPC_OPCODE_TMR         0x400000000ull
 192
 193 /* Opcode which is supported by the VLE extension.  */
 194 #define PPC_OPCODE_VLE         0x800000000ull
 195
 196 /* Opcode is only supported by Power8 architecture.  */
 197 #define PPC_OPCODE_POWER8     0x1000000000ull
 198
 199 /* Opcode is supported by ppc750cl.  */
 200 #define PPC_OPCODE_750        0x2000000000ull
 201
 202 /* Opcode is supported by ppc7450.  */
 203 #define PPC_OPCODE_7450       0x4000000000ull
 204
 205 /* Opcode is supported by ppc821/850/860.  */
 206 #define PPC_OPCODE_860        0x8000000000ull
 207
 208 /* Opcode is only supported by Power9 architecture.  */
 209 #define PPC_OPCODE_POWER9    0x10000000000ull
 210
 211 /* Opcode is supported by e200z4.  */
 212 #define PPC_OPCODE_E200Z4    0x20000000000ull
 213
 214 /* Disassemble to instructions matching later in the opcode table
 215    with fewer "mask" bits set rather than the earlist match.  Fewer
 216    "mask" bits set imply a more general form of the opcode, in fact
 217    the underlying machine instruction.  */
 218 #define PPC_OPCODE_RAW       0x40000000000ull
 219
 220 /* Opcode is supported by PowerPC LSP */
 221 #define PPC_OPCODE_LSP       0x80000000000ull
 222
 223 /* Opcode is only supported by Freescale SPE2 APU.  */
 224 #define PPC_OPCODE_SPE2     0x100000000000ull
 225
 226 /* Opcode is supported by EFS2.  */
 227 #define PPC_OPCODE_EFS2     0x200000000000ull
 228
 229 /* A macro to extract the major opcode from an instruction.  */
 230 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 231
 232 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
 233 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
 234
 235 /* A macro to extract the major opcode from a VLE instruction.  */
 236 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
 237
 238 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
 239 #define VLE_OP_TO_SEG(i) ((i) >> 1)
 240
 241 /* A macro to extract the extended opcode from a SPE2 instruction.  */
 242 #define SPE2_XOP(i) ((i) & 0x7ff)
 243
 244 /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment.  */
 245 #define SPE2_XOP_TO_SEG(i) ((i) >> 7)
 246 \f
 247 /* The operands table is an array of struct powerpc_operand.  */
 248
 249 struct powerpc_operand
 250 {
 251   /* A bitmask of bits in the operand.  */
 252   unsigned int bitm;
 253
 254   /* The shift operation to be applied to the operand.  No shift
 255      is made if this is zero.  For positive values, the operand
 256      is shifted left by SHIFT.  For negative values, the operand
 257      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
 258      that BITM and SHIFT cannot be used to determine where the
 259      operand goes in the insn.  */
 260   int shift;
 261
 262   /* Insertion function.  This is used by the assembler.  To insert an
 263      operand value into an instruction, check this field.
 264
 265      If it is NULL, execute
 266          if (o->shift >= 0)
 267            i |= (op & o->bitm) << o->shift;
 268          else
 269            i |= (op & o->bitm) >> -o->shift;
 270      (i is the instruction which we are filling in, o is a pointer to
 271      this structure, and op is the operand value).
 272
 273      If this field is not NULL, then simply call it with the
 274      instruction and the operand value.  It will return the new value
 275      of the instruction.  If the ERRMSG argument is not NULL, then if
 276      the operand value is illegal, *ERRMSG will be set to a warning
 277      string (the operand will be inserted in any case).  If the
 278      operand value is legal, *ERRMSG will be unchanged (most operands
 279      can accept any value).  */
 280   unsigned long (*insert)
 281     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 282
 283   /* Extraction function.  This is used by the disassembler.  To
 284      extract this operand type from an instruction, check this field.
 285
 286      If it is NULL, compute
 287          if (o->shift >= 0)
 288            op = (i >> o->shift) & o->bitm;
 289          else
 290            op = (i << -o->shift) & o->bitm;
 291          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 292            sign_extend (op);
 293      (i is the instruction, o is a pointer to this structure, and op
 294      is the result).
 295
 296      If this field is not NULL, then simply call it with the
 297      instruction value.  It will return the value of the operand.  If
 298      the INVALID argument is not NULL, *INVALID will be set to
 299      non-zero if this operand type can not actually be extracted from
 300      this operand (i.e., the instruction does not match).  If the
 301      operand is valid, *INVALID will not be changed.  */
 302   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 303
 304   /* One bit syntax flags.  */
 305   unsigned long flags;
 306 };
 307
 308 /* Elements in the table are retrieved by indexing with values from
 309    the operands field of the powerpc_opcodes table.  */
 310
 311 extern const struct powerpc_operand powerpc_operands[];
 312 extern const unsigned int num_powerpc_operands;
 313
 314 /* Use with the shift field of a struct powerpc_operand to indicate
 315      that BITM and SHIFT cannot be used to determine where the operand
 316      goes in the insn.  */
 317 #define PPC_OPSHIFT_INV (-1U << 31)
 318
 319 /* Values defined for the flags field of a struct powerpc_operand.
 320    Keep the register bits low:  They need to fit in an unsigned short.  */
 321
 322 /* This operand names a register.  The disassembler uses this to print
 323    register names with a leading 'r'.  */
 324 #define PPC_OPERAND_GPR (0x1)
 325
 326 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 327 #define PPC_OPERAND_GPR_0 (0x2)
 328
 329 /* This operand names a floating point register.  The disassembler
 330    prints these with a leading 'f'.  */
 331 #define PPC_OPERAND_FPR (0x4)
 332
 333 /* This operand names a vector unit register.  The disassembler
 334    prints these with a leading 'v'.  */
 335 #define PPC_OPERAND_VR (0x8)
 336
 337 /* This operand names a vector-scalar unit register.  The disassembler
 338    prints these with a leading 'vs'.  */
 339 #define PPC_OPERAND_VSR (0x10)
 340
 341 /* This operand may use the symbolic names for the CR fields (even
 342    without -mregnames), which are
 343        lt  0    gt  1   eq  2   so  3   un  3
 344        cr0 0    cr1 1   cr2 2   cr3 3
 345        cr4 4    cr5 5   cr6 6   cr7 7
 346    These may be combined arithmetically, as in cr2*4+gt.  These are
 347    only supported on the PowerPC, not the POWER.  */
 348 #define PPC_OPERAND_CR_BIT (0x20)
 349
 350 /* This is a CR FIELD that does not use symbolic names (unless
 351    -mregnames is in effect).  */
 352 #define PPC_OPERAND_CR_REG (0x40)
 353
 354 /* This operand names a special purpose register.  */
 355 #define PPC_OPERAND_SPR (0x80)
 356
 357 /* This operand names a paired-single graphics quantization register.  */
 358 #define PPC_OPERAND_GQR (0x100)
 359
 360 /* This operand is a relative branch displacement.  The disassembler
 361    prints these symbolically if possible.  */
 362 #define PPC_OPERAND_RELATIVE (0x200)
 363
 364 /* This operand is an absolute branch address.  The disassembler
 365    prints these symbolically if possible.  */
 366 #define PPC_OPERAND_ABSOLUTE (0x400)
 367
 368 /* This operand takes signed values.  */
 369 #define PPC_OPERAND_SIGNED (0x800)
 370
 371 /* This operand takes signed values, but also accepts a full positive
 372    range of values when running in 32 bit mode.  That is, if bits is
 373    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 374    this flag is ignored.  */
 375 #define PPC_OPERAND_SIGNOPT (0x1000)
 376
 377 /* The next operand should be wrapped in parentheses rather than
 378    separated from this one by a comma.  This is used for the load and
 379    store instructions which want their operands to look like
 380        reg,displacement(reg)
 381    */
 382 #define PPC_OPERAND_PARENS (0x2000)
 383
 384 /* This operand is for the DS field in a DS form instruction.  */
 385 #define PPC_OPERAND_DS (0x4000)
 386
 387 /* This operand is for the DQ field in a DQ form instruction.  */
 388 #define PPC_OPERAND_DQ (0x8000)
 389
 390 /* This operand should be regarded as a negative number for the
 391    purposes of overflow checking (i.e., the normal most negative
 392    number is disallowed and one more than the normal most positive
 393    number is allowed).  This flag will only be set for a signed
 394    operand.  */
 395 #define PPC_OPERAND_NEGATIVE (0x10000)
 396
 397 /* Valid range of operand is 0..n rather than 0..n-1.  */
 398 #define PPC_OPERAND_PLUS1 (0x20000)
 399
 400 /* This operand does not actually exist in the assembler input.  This
 401    is used to support extended mnemonics such as mr, for which two
 402    operands fields are identical.  The assembler should call the
 403    insert function with any op value.  The disassembler should call
 404    the extract function, ignore the return value, and check the value
 405    placed in the valid argument.  */
 406 #define PPC_OPERAND_FAKE (0x40000)
 407
 408 /* This operand is optional, and is zero if omitted.  This is used for
 409    example, in the optional BF field in the comparison instructions.  The
 410    assembler must count the number of operands remaining on the line,
 411    and the number of operands remaining for the opcode, and decide
 412    whether this operand is present or not.  The disassembler should
 413    print this operand out only if it is not zero.  */
 414 #define PPC_OPERAND_OPTIONAL (0x80000)
 415
 416 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 417    is omitted, then for the next operand use this operand value plus
 418    1, ignoring the next operand field for the opcode.  This wretched
 419    hack is needed because the Power rotate instructions can take
 420    either 4 or 5 operands.  The disassembler should print this operand
 421    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 422 #define PPC_OPERAND_NEXT (0x100000)
 423
 424 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 425    is omitted, then the value it should use for the operand is stored
 426    in the SHIFT field of the immediatly following operand field.  */
 427 #define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
 428
 429 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
 430    only optional when generating 32-bit code.  */
 431 #define PPC_OPERAND_OPTIONAL32 (0x400000)
 432
 433 /* Xilinx APU and FSL related operands */
 434 #define PPC_OPERAND_FSL (0x800000)
 435 #define PPC_OPERAND_FCR (0x1000000)
 436 #define PPC_OPERAND_UDI (0x2000000)
 437 \f
 438 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 439    with the operands table for simplicity.  The macro table is an
 440    array of struct powerpc_macro.  */
 441
 442 struct powerpc_macro
 443 {
 444   /* The macro name.  */
 445   const char *name;
 446
 447   /* The number of operands the macro takes.  */
 448   unsigned int operands;
 449
 450   /* One bit flags for the opcode.  These are used to indicate which
 451      specific processors support the instructions.  The values are the
 452      same as those for the struct powerpc_opcode flags field.  */
 453   ppc_cpu_t flags;
 454
 455   /* A format string to turn the macro into a normal instruction.
 456      Each %N in the string is replaced with operand number N (zero
 457      based).  */
 458   const char *format;
 459 };
 460
 461 extern const struct powerpc_macro powerpc_macros[];
 462 extern const int powerpc_num_macros;
 463
 464 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
 465
 466 static inline long
 467 ppc_optional_operand_value (const struct powerpc_operand *operand)
 468 {
 469   if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
 470     return (operand+1)->shift;
 471   return 0;
 472 }
 473
 474 /* PowerPC VLE insns.  */
 475 /* Form I16L, uses 16A relocs.  */
 476 #define E_OR2I_INSN             0x7000C000
 477 #define E_AND2I_DOT_INSN        0x7000C800
 478 #define E_OR2IS_INSN            0x7000D000
 479 #define E_LIS_INSN              0x7000E000
 480 #define E_AND2IS_DOT_INSN       0x7000E800
 481
 482 /* Form I16A, uses 16D relocs.  */
 483 #define E_ADD2I_DOT_INSN        0x70008800
 484 #define E_ADD2IS_INSN           0x70009000
 485 #define E_CMP16I_INSN           0x70009800
 486 #define E_MULL2I_INSN           0x7000A000
 487 #define E_CMPL16I_INSN          0x7000A800
 488 #define E_CMPH16I_INSN          0x7000B000
 489 #define E_CMPHL16I_INSN         0x7000B800
 490
 491 #ifdef __cplusplus
 492 }
 493 #endif
 494
 495 #endif /* PPC_H */