include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 typedef uint64_t ppc_cpu_t;
  32
  33 /* The opcode table is an array of struct powerpc_opcode.  */
  34
  35 struct powerpc_opcode
  36 {
  37   /* The opcode name.  */
  38   const char *name;
  39
  40   /* The opcode itself.  Those bits which will be filled in with
  41      operands are zeroes.  */
  42   unsigned long opcode;
  43
  44   /* The opcode mask.  This is used by the disassembler.  This is a
  45      mask containing ones indicating those bits which must match the
  46      opcode field, and zeroes indicating those bits which need not
  47      match (and are presumably filled in by operands).  */
  48   unsigned long mask;
  49
  50   /* One bit flags for the opcode.  These are used to indicate which
  51      specific processors support the instructions.  The defined values
  52      are listed below.  */
  53   ppc_cpu_t flags;
  54
  55   /* One bit flags for the opcode.  These are used to indicate which
  56      specific processors no longer support the instructions.  The defined
  57      values are listed below.  */
  58   ppc_cpu_t deprecated;
  59
  60   /* An array of operand codes.  Each code is an index into the
  61      operand table.  They appear in the order which the operands must
  62      appear in assembly code, and are terminated by a zero.  */
  63   unsigned char operands[8];
  64 };
  65
  66 /* The table itself is sorted by major opcode number, and is otherwise
  67    in the order in which the disassembler should consider
  68    instructions.  */
  69 extern const struct powerpc_opcode powerpc_opcodes[];
  70 extern const int powerpc_num_opcodes;
  71 extern const struct powerpc_opcode vle_opcodes[];
  72 extern const int vle_num_opcodes;
  73
  74 /* Values defined for the flags field of a struct powerpc_opcode.  */
  75
  76 /* Opcode is defined for the PowerPC architecture.  */
  77 #define PPC_OPCODE_PPC                 0x1ull
  78
  79 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  80 #define PPC_OPCODE_POWER               0x2ull
  81
  82 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  83 #define PPC_OPCODE_POWER2              0x4ull
  84
  85 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  86    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  87    but it also supports many additional POWER instructions.  */
  88 #define PPC_OPCODE_601                 0x8ull
  89
  90 /* Opcode is supported in both the Power and PowerPC architectures
  91    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
  92    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
  93    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
  94    between POWER and POWERPC.  */
  95 #define PPC_OPCODE_COMMON             0x10ull
  96
  97 /* Opcode is supported for any Power or PowerPC platform (this is
  98    for the assembler's -many option, and it eliminates duplicates).  */
  99 #define PPC_OPCODE_ANY                0x20ull
 100
 101 /* Opcode is only defined on 64 bit architectures.  */
 102 #define PPC_OPCODE_64                 0x40ull
 103
 104 /* Opcode is supported as part of the 64-bit bridge.  */
 105 #define PPC_OPCODE_64_BRIDGE          0x80ull
 106
 107 /* Opcode is supported by Altivec Vector Unit */
 108 #define PPC_OPCODE_ALTIVEC           0x100ull
 109
 110 /* Opcode is supported by PowerPC 403 processor.  */
 111 #define PPC_OPCODE_403               0x200ull
 112
 113 /* Opcode is supported by PowerPC BookE processor.  */
 114 #define PPC_OPCODE_BOOKE             0x400ull
 115
 116 /* Opcode is supported by PowerPC 440 processor.  */
 117 #define PPC_OPCODE_440               0x800ull
 118
 119 /* Opcode is only supported by Power4 architecture.  */
 120 #define PPC_OPCODE_POWER4           0x1000ull
 121
 122 /* Opcode is only supported by Power7 architecture.  */
 123 #define PPC_OPCODE_POWER7           0x2000ull
 124
 125 /* Opcode is only supported by e500x2 Core.  */
 126 #define PPC_OPCODE_SPE              0x4000ull
 127
 128 /* Opcode is supported by e500x2 Integer select APU.  */
 129 #define PPC_OPCODE_ISEL             0x8000ull
 130
 131 /* Opcode is an e500 SPE floating point instruction.  */
 132 #define PPC_OPCODE_EFS             0x10000ull
 133
 134 /* Opcode is supported by branch locking APU.  */
 135 #define PPC_OPCODE_BRLOCK          0x20000ull
 136
 137 /* Opcode is supported by performance monitor APU.  */
 138 #define PPC_OPCODE_PMR             0x40000ull
 139
 140 /* Opcode is supported by cache locking APU.  */
 141 #define PPC_OPCODE_CACHELCK        0x80000ull
 142
 143 /* Opcode is supported by machine check APU.  */
 144 #define PPC_OPCODE_RFMCI          0x100000ull
 145
 146 /* Opcode is only supported by Power5 architecture.  */
 147 #define PPC_OPCODE_POWER5         0x200000ull
 148
 149 /* Opcode is supported by PowerPC e300 family.  */
 150 #define PPC_OPCODE_E300           0x400000ull
 151
 152 /* Opcode is only supported by Power6 architecture.  */
 153 #define PPC_OPCODE_POWER6         0x800000ull
 154
 155 /* Opcode is only supported by PowerPC Cell family.  */
 156 #define PPC_OPCODE_CELL          0x1000000ull
 157
 158 /* Opcode is supported by CPUs with paired singles support.  */
 159 #define PPC_OPCODE_PPCPS         0x2000000ull
 160
 161 /* Opcode is supported by Power E500MC */
 162 #define PPC_OPCODE_E500MC        0x4000000ull
 163
 164 /* Opcode is supported by PowerPC 405 processor.  */
 165 #define PPC_OPCODE_405           0x8000000ull
 166
 167 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 168 #define PPC_OPCODE_VSX          0x10000000ull
 169
 170 /* Opcode is supported by A2.  */
 171 #define PPC_OPCODE_A2           0x20000000ull
 172
 173 /* Opcode is supported by PowerPC 476 processor.  */
 174 #define PPC_OPCODE_476          0x40000000ull
 175
 176 /* Opcode is supported by AppliedMicro Titan core */
 177 #define PPC_OPCODE_TITAN        0x80000000ull
 178
 179 /* Opcode which is supported by the e500 family */
 180 #define PPC_OPCODE_E500        0x100000000ull
 181
 182 /* Opcode is supported by Power E6500 */
 183 #define PPC_OPCODE_E6500       0x400000000ull
 184
 185 /* Opcode is supported by Thread management APU */
 186 #define PPC_OPCODE_TMR         0x800000000ull
 187
 188 /* Opcode which is supported by the VLE extension.  */
 189 #define PPC_OPCODE_VLE        0x1000000000ull
 190
 191 /* Opcode is only supported by Power8 architecture.  */
 192 #define PPC_OPCODE_POWER8     0x2000000000ull
 193
 194 /* Opcode is supported by ppc750cl.  */
 195 #define PPC_OPCODE_750        0x4000000000ull
 196
 197 /* Opcode is supported by ppc7450.  */
 198 #define PPC_OPCODE_7450       0x8000000000ull
 199
 200 /* Opcode is supported by ppc821/850/860.  */
 201 #define PPC_OPCODE_860       0x10000000000ull
 202
 203 /* Opcode is only supported by Power9 architecture.  */
 204 #define PPC_OPCODE_POWER9    0x20000000000ull
 205
 206 /* Opcode is supported by e200z4.  */
 207 #define PPC_OPCODE_E200Z4    0x80000000000ull
 208
 209 /* Disassemble to instructions matching later in the opcode table
 210    with fewer "mask" bits set rather than the earlist match.  Fewer
 211    "mask" bits set imply a more general form of the opcode, in fact
 212    the underlying machine instruction.  */
 213 #define PPC_OPCODE_RAW      0x100000000000ull
 214
 215 /* A macro to extract the major opcode from an instruction.  */
 216 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 217
 218 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
 219 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
 220
 221 /* A macro to extract the major opcode from a VLE instruction.  */
 222 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
 223
 224 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
 225 #define VLE_OP_TO_SEG(i) ((i) >> 1)
 226 \f
 227 /* The operands table is an array of struct powerpc_operand.  */
 228
 229 struct powerpc_operand
 230 {
 231   /* A bitmask of bits in the operand.  */
 232   unsigned int bitm;
 233
 234   /* The shift operation to be applied to the operand.  No shift
 235      is made if this is zero.  For positive values, the operand
 236      is shifted left by SHIFT.  For negative values, the operand
 237      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
 238      that BITM and SHIFT cannot be used to determine where the
 239      operand goes in the insn.  */
 240   int shift;
 241
 242   /* Insertion function.  This is used by the assembler.  To insert an
 243      operand value into an instruction, check this field.
 244
 245      If it is NULL, execute
 246          if (o->shift >= 0)
 247            i |= (op & o->bitm) << o->shift;
 248          else
 249            i |= (op & o->bitm) >> -o->shift;
 250      (i is the instruction which we are filling in, o is a pointer to
 251      this structure, and op is the operand value).
 252
 253      If this field is not NULL, then simply call it with the
 254      instruction and the operand value.  It will return the new value
 255      of the instruction.  If the ERRMSG argument is not NULL, then if
 256      the operand value is illegal, *ERRMSG will be set to a warning
 257      string (the operand will be inserted in any case).  If the
 258      operand value is legal, *ERRMSG will be unchanged (most operands
 259      can accept any value).  */
 260   unsigned long (*insert)
 261     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 262
 263   /* Extraction function.  This is used by the disassembler.  To
 264      extract this operand type from an instruction, check this field.
 265
 266      If it is NULL, compute
 267          if (o->shift >= 0)
 268            op = (i >> o->shift) & o->bitm;
 269          else
 270            op = (i << -o->shift) & o->bitm;
 271          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 272            sign_extend (op);
 273      (i is the instruction, o is a pointer to this structure, and op
 274      is the result).
 275
 276      If this field is not NULL, then simply call it with the
 277      instruction value.  It will return the value of the operand.  If
 278      the INVALID argument is not NULL, *INVALID will be set to
 279      non-zero if this operand type can not actually be extracted from
 280      this operand (i.e., the instruction does not match).  If the
 281      operand is valid, *INVALID will not be changed.  */
 282   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 283
 284   /* One bit syntax flags.  */
 285   unsigned long flags;
 286 };
 287
 288 /* Elements in the table are retrieved by indexing with values from
 289    the operands field of the powerpc_opcodes table.  */
 290
 291 extern const struct powerpc_operand powerpc_operands[];
 292 extern const unsigned int num_powerpc_operands;
 293
 294 /* Use with the shift field of a struct powerpc_operand to indicate
 295      that BITM and SHIFT cannot be used to determine where the operand
 296      goes in the insn.  */
 297 #define PPC_OPSHIFT_INV (-1U << 31)
 298
 299 /* Values defined for the flags field of a struct powerpc_operand.
 300    Keep the register bits low:  They need to fit in an unsigned short.  */
 301
 302 /* This operand names a register.  The disassembler uses this to print
 303    register names with a leading 'r'.  */
 304 #define PPC_OPERAND_GPR (0x1)
 305
 306 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 307 #define PPC_OPERAND_GPR_0 (0x2)
 308
 309 /* This operand names a floating point register.  The disassembler
 310    prints these with a leading 'f'.  */
 311 #define PPC_OPERAND_FPR (0x4)
 312
 313 /* This operand names a vector unit register.  The disassembler
 314    prints these with a leading 'v'.  */
 315 #define PPC_OPERAND_VR (0x8)
 316
 317 /* This operand names a vector-scalar unit register.  The disassembler
 318    prints these with a leading 'vs'.  */
 319 #define PPC_OPERAND_VSR (0x10)
 320
 321 /* This operand may use the symbolic names for the CR fields (even
 322    without -mregnames), which are
 323        lt  0    gt  1   eq  2   so  3   un  3
 324        cr0 0    cr1 1   cr2 2   cr3 3
 325        cr4 4    cr5 5   cr6 6   cr7 7
 326    These may be combined arithmetically, as in cr2*4+gt.  These are
 327    only supported on the PowerPC, not the POWER.  */
 328 #define PPC_OPERAND_CR_BIT (0x20)
 329
 330 /* This is a CR FIELD that does not use symbolic names (unless
 331    -mregnames is in effect).  */
 332 #define PPC_OPERAND_CR_REG (0x40)
 333
 334 /* This operand names a special purpose register.  */
 335 #define PPC_OPERAND_SPR (0x80)
 336
 337 /* This operand names a paired-single graphics quantization register.  */
 338 #define PPC_OPERAND_GQR (0x100)
 339
 340 /* This operand is a relative branch displacement.  The disassembler
 341    prints these symbolically if possible.  */
 342 #define PPC_OPERAND_RELATIVE (0x200)
 343
 344 /* This operand is an absolute branch address.  The disassembler
 345    prints these symbolically if possible.  */
 346 #define PPC_OPERAND_ABSOLUTE (0x400)
 347
 348 /* This operand takes signed values.  */
 349 #define PPC_OPERAND_SIGNED (0x800)
 350
 351 /* This operand takes signed values, but also accepts a full positive
 352    range of values when running in 32 bit mode.  That is, if bits is
 353    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 354    this flag is ignored.  */
 355 #define PPC_OPERAND_SIGNOPT (0x1000)
 356
 357 /* The next operand should be wrapped in parentheses rather than
 358    separated from this one by a comma.  This is used for the load and
 359    store instructions which want their operands to look like
 360        reg,displacement(reg)
 361    */
 362 #define PPC_OPERAND_PARENS (0x2000)
 363
 364 /* This operand is for the DS field in a DS form instruction.  */
 365 #define PPC_OPERAND_DS (0x4000)
 366
 367 /* This operand is for the DQ field in a DQ form instruction.  */
 368 #define PPC_OPERAND_DQ (0x8000)
 369
 370 /* This operand should be regarded as a negative number for the
 371    purposes of overflow checking (i.e., the normal most negative
 372    number is disallowed and one more than the normal most positive
 373    number is allowed).  This flag will only be set for a signed
 374    operand.  */
 375 #define PPC_OPERAND_NEGATIVE (0x10000)
 376
 377 /* Valid range of operand is 0..n rather than 0..n-1.  */
 378 #define PPC_OPERAND_PLUS1 (0x20000)
 379
 380 /* This operand does not actually exist in the assembler input.  This
 381    is used to support extended mnemonics such as mr, for which two
 382    operands fields are identical.  The assembler should call the
 383    insert function with any op value.  The disassembler should call
 384    the extract function, ignore the return value, and check the value
 385    placed in the valid argument.  */
 386 #define PPC_OPERAND_FAKE (0x40000)
 387
 388 /* This operand is optional, and is zero if omitted.  This is used for
 389    example, in the optional BF field in the comparison instructions.  The
 390    assembler must count the number of operands remaining on the line,
 391    and the number of operands remaining for the opcode, and decide
 392    whether this operand is present or not.  The disassembler should
 393    print this operand out only if it is not zero.  */
 394 #define PPC_OPERAND_OPTIONAL (0x80000)
 395
 396 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 397    is omitted, then for the next operand use this operand value plus
 398    1, ignoring the next operand field for the opcode.  This wretched
 399    hack is needed because the Power rotate instructions can take
 400    either 4 or 5 operands.  The disassembler should print this operand
 401    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 402 #define PPC_OPERAND_NEXT (0x100000)
 403
 404 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 405    is omitted, then the value it should use for the operand is stored
 406    in the SHIFT field of the immediatly following operand field.  */
 407 #define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
 408
 409 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
 410    only optional when generating 32-bit code.  */
 411 #define PPC_OPERAND_OPTIONAL32 (0x400000)
 412
 413 /* Xilinx APU and FSL related operands */
 414 #define PPC_OPERAND_FSL (0x800000)
 415 #define PPC_OPERAND_FCR (0x1000000)
 416 #define PPC_OPERAND_UDI (0x2000000)
 417 \f
 418 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 419    with the operands table for simplicity.  The macro table is an
 420    array of struct powerpc_macro.  */
 421
 422 struct powerpc_macro
 423 {
 424   /* The macro name.  */
 425   const char *name;
 426
 427   /* The number of operands the macro takes.  */
 428   unsigned int operands;
 429
 430   /* One bit flags for the opcode.  These are used to indicate which
 431      specific processors support the instructions.  The values are the
 432      same as those for the struct powerpc_opcode flags field.  */
 433   ppc_cpu_t flags;
 434
 435   /* A format string to turn the macro into a normal instruction.
 436      Each %N in the string is replaced with operand number N (zero
 437      based).  */
 438   const char *format;
 439 };
 440
 441 extern const struct powerpc_macro powerpc_macros[];
 442 extern const int powerpc_num_macros;
 443
 444 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
 445
 446 static inline long
 447 ppc_optional_operand_value (const struct powerpc_operand *operand)
 448 {
 449   if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
 450     return (operand+1)->shift;
 451   return 0;
 452 }
 453
 454 /* PowerPC VLE insns.  */
 455 /* Form I16L, uses 16A relocs.  */
 456 #define E_OR2I_INSN             0x7000C000
 457 #define E_AND2I_DOT_INSN        0x7000C800
 458 #define E_OR2IS_INSN            0x7000D000
 459 #define E_LIS_INSN              0x7000E000
 460 #define E_AND2IS_DOT_INSN       0x7000E800
 461
 462 /* Form I16A, uses 16D relocs.  */
 463 #define E_ADD2I_DOT_INSN        0x70008800
 464 #define E_ADD2IS_INSN           0x70009000
 465 #define E_CMP16I_INSN           0x70009800
 466 #define E_MULL2I_INSN           0x7000A000
 467 #define E_CMPL16I_INSN          0x7000A800
 468 #define E_CMPH16I_INSN          0x7000B000
 469 #define E_CMPHL16I_INSN         0x7000B800
 470
 471 #ifdef __cplusplus
 472 }
 473 #endif
 474
 475 #endif /* PPC_H */