include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   3    2007 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 typedef unsigned long ppc_cpu_t;
  26
  27 /* The opcode table is an array of struct powerpc_opcode.  */
  28
  29 struct powerpc_opcode
  30 {
  31   /* The opcode name.  */
  32   const char *name;
  33
  34   /* The opcode itself.  Those bits which will be filled in with
  35      operands are zeroes.  */
  36   unsigned long opcode;
  37
  38   /* The opcode mask.  This is used by the disassembler.  This is a
  39      mask containing ones indicating those bits which must match the
  40      opcode field, and zeroes indicating those bits which need not
  41      match (and are presumably filled in by operands).  */
  42   unsigned long mask;
  43
  44   /* One bit flags for the opcode.  These are used to indicate which
  45      specific processors support the instructions.  The defined values
  46      are listed below.  */
  47   ppc_cpu_t flags;
  48
  49   /* An array of operand codes.  Each code is an index into the
  50      operand table.  They appear in the order which the operands must
  51      appear in assembly code, and are terminated by a zero.  */
  52   unsigned char operands[8];
  53 };
  54
  55 /* The table itself is sorted by major opcode number, and is otherwise
  56    in the order in which the disassembler should consider
  57    instructions.  */
  58 extern const struct powerpc_opcode powerpc_opcodes[];
  59 extern const int powerpc_num_opcodes;
  60
  61 /* Values defined for the flags field of a struct powerpc_opcode.  */
  62
  63 /* Opcode is defined for the PowerPC architecture.  */
  64 #define PPC_OPCODE_PPC                   1
  65
  66 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  67 #define PPC_OPCODE_POWER                 2
  68
  69 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  70 #define PPC_OPCODE_POWER2                4
  71
  72 /* Opcode is only defined on 32 bit architectures.  */
  73 #define PPC_OPCODE_32                    8
  74
  75 /* Opcode is only defined on 64 bit architectures.  */
  76 #define PPC_OPCODE_64                 0x10
  77
  78 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  79    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  80    but it also supports many additional POWER instructions.  */
  81 #define PPC_OPCODE_601                0x20
  82
  83 /* Opcode is supported in both the Power and PowerPC architectures
  84    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  85 #define PPC_OPCODE_COMMON             0x40
  86
  87 /* Opcode is supported for any Power or PowerPC platform (this is
  88    for the assembler's -many option, and it eliminates duplicates).  */
  89 #define PPC_OPCODE_ANY                0x80
  90
  91 /* Opcode is supported as part of the 64-bit bridge.  */
  92 #define PPC_OPCODE_64_BRIDGE         0x100
  93
  94 /* Opcode is supported by Altivec Vector Unit */
  95 #define PPC_OPCODE_ALTIVEC           0x200
  96
  97 /* Opcode is supported by PowerPC 403 processor.  */
  98 #define PPC_OPCODE_403               0x400
  99
 100 /* Opcode is supported by PowerPC BookE processor.  */
 101 #define PPC_OPCODE_BOOKE             0x800
 102
 103 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 104 #define PPC_OPCODE_BOOKE64          0x1000
 105
 106 /* Opcode is supported by PowerPC 440 processor.  */
 107 #define PPC_OPCODE_440              0x2000
 108
 109 /* Opcode is only supported by Power4 architecture.  */
 110 #define PPC_OPCODE_POWER4           0x4000
 111
 112 /* Opcode isn't supported by Power4 architecture.  */
 113 #define PPC_OPCODE_NOPOWER4         0x8000
 114
 115 /* Opcode is only supported by POWERPC Classic architecture.  */
 116 #define PPC_OPCODE_CLASSIC         0x10000
 117
 118 /* Opcode is only supported by e500x2 Core.  */
 119 #define PPC_OPCODE_SPE             0x20000
 120
 121 /* Opcode is supported by e500x2 Integer select APU.  */
 122 #define PPC_OPCODE_ISEL            0x40000
 123
 124 /* Opcode is an e500 SPE floating point instruction.  */
 125 #define PPC_OPCODE_EFS             0x80000
 126
 127 /* Opcode is supported by branch locking APU.  */
 128 #define PPC_OPCODE_BRLOCK         0x100000
 129
 130 /* Opcode is supported by performance monitor APU.  */
 131 #define PPC_OPCODE_PMR            0x200000
 132
 133 /* Opcode is supported by cache locking APU.  */
 134 #define PPC_OPCODE_CACHELCK       0x400000
 135
 136 /* Opcode is supported by machine check APU.  */
 137 #define PPC_OPCODE_RFMCI          0x800000
 138
 139 /* Opcode is only supported by Power5 architecture.  */
 140 #define PPC_OPCODE_POWER5        0x1000000
 141
 142 /* Opcode is supported by PowerPC e300 family.  */
 143 #define PPC_OPCODE_E300          0x2000000
 144
 145 /* Opcode is only supported by Power6 architecture.  */
 146 #define PPC_OPCODE_POWER6        0x4000000
 147
 148 /* Opcode is only supported by PowerPC Cell family.  */
 149 #define PPC_OPCODE_CELL          0x8000000
 150
 151 /* Opcode is supported by CPUs with paired singles support.  */
 152 #define PPC_OPCODE_PPCPS         0x10000000
 153
 154 /* Opcode is supported by Power E500MC */
 155 #define PPC_OPCODE_E500MC        0x20000000
 156
 157 /* A macro to extract the major opcode from an instruction.  */
 158 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 159 \f
 160 /* The operands table is an array of struct powerpc_operand.  */
 161
 162 struct powerpc_operand
 163 {
 164   /* A bitmask of bits in the operand.  */
 165   unsigned int bitm;
 166
 167   /* How far the operand is left shifted in the instruction.
 168      -1 to indicate that BITM and SHIFT cannot be used to determine
 169      where the operand goes in the insn.  */
 170   int shift;
 171
 172   /* Insertion function.  This is used by the assembler.  To insert an
 173      operand value into an instruction, check this field.
 174
 175      If it is NULL, execute
 176          i |= (op & o->bitm) << o->shift;
 177      (i is the instruction which we are filling in, o is a pointer to
 178      this structure, and op is the operand value).
 179
 180      If this field is not NULL, then simply call it with the
 181      instruction and the operand value.  It will return the new value
 182      of the instruction.  If the ERRMSG argument is not NULL, then if
 183      the operand value is illegal, *ERRMSG will be set to a warning
 184      string (the operand will be inserted in any case).  If the
 185      operand value is legal, *ERRMSG will be unchanged (most operands
 186      can accept any value).  */
 187   unsigned long (*insert)
 188     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 189
 190   /* Extraction function.  This is used by the disassembler.  To
 191      extract this operand type from an instruction, check this field.
 192
 193      If it is NULL, compute
 194          op = (i >> o->shift) & o->bitm;
 195          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 196            sign_extend (op);
 197      (i is the instruction, o is a pointer to this structure, and op
 198      is the result).
 199
 200      If this field is not NULL, then simply call it with the
 201      instruction value.  It will return the value of the operand.  If
 202      the INVALID argument is not NULL, *INVALID will be set to
 203      non-zero if this operand type can not actually be extracted from
 204      this operand (i.e., the instruction does not match).  If the
 205      operand is valid, *INVALID will not be changed.  */
 206   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 207
 208   /* One bit syntax flags.  */
 209   unsigned long flags;
 210 };
 211
 212 /* Elements in the table are retrieved by indexing with values from
 213    the operands field of the powerpc_opcodes table.  */
 214
 215 extern const struct powerpc_operand powerpc_operands[];
 216 extern const unsigned int num_powerpc_operands;
 217
 218 /* Values defined for the flags field of a struct powerpc_operand.  */
 219
 220 /* This operand takes signed values.  */
 221 #define PPC_OPERAND_SIGNED (0x1)
 222
 223 /* This operand takes signed values, but also accepts a full positive
 224    range of values when running in 32 bit mode.  That is, if bits is
 225    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 226    this flag is ignored.  */
 227 #define PPC_OPERAND_SIGNOPT (0x2)
 228
 229 /* This operand does not actually exist in the assembler input.  This
 230    is used to support extended mnemonics such as mr, for which two
 231    operands fields are identical.  The assembler should call the
 232    insert function with any op value.  The disassembler should call
 233    the extract function, ignore the return value, and check the value
 234    placed in the valid argument.  */
 235 #define PPC_OPERAND_FAKE (0x4)
 236
 237 /* The next operand should be wrapped in parentheses rather than
 238    separated from this one by a comma.  This is used for the load and
 239    store instructions which want their operands to look like
 240        reg,displacement(reg)
 241    */
 242 #define PPC_OPERAND_PARENS (0x8)
 243
 244 /* This operand may use the symbolic names for the CR fields, which
 245    are
 246        lt  0    gt  1   eq  2   so  3   un  3
 247        cr0 0    cr1 1   cr2 2   cr3 3
 248        cr4 4    cr5 5   cr6 6   cr7 7
 249    These may be combined arithmetically, as in cr2*4+gt.  These are
 250    only supported on the PowerPC, not the POWER.  */
 251 #define PPC_OPERAND_CR (0x10)
 252
 253 /* This operand names a register.  The disassembler uses this to print
 254    register names with a leading 'r'.  */
 255 #define PPC_OPERAND_GPR (0x20)
 256
 257 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 258 #define PPC_OPERAND_GPR_0 (0x40)
 259
 260 /* This operand names a floating point register.  The disassembler
 261    prints these with a leading 'f'.  */
 262 #define PPC_OPERAND_FPR (0x80)
 263
 264 /* This operand is a relative branch displacement.  The disassembler
 265    prints these symbolically if possible.  */
 266 #define PPC_OPERAND_RELATIVE (0x100)
 267
 268 /* This operand is an absolute branch address.  The disassembler
 269    prints these symbolically if possible.  */
 270 #define PPC_OPERAND_ABSOLUTE (0x200)
 271
 272 /* This operand is optional, and is zero if omitted.  This is used for
 273    example, in the optional BF field in the comparison instructions.  The
 274    assembler must count the number of operands remaining on the line,
 275    and the number of operands remaining for the opcode, and decide
 276    whether this operand is present or not.  The disassembler should
 277    print this operand out only if it is not zero.  */
 278 #define PPC_OPERAND_OPTIONAL (0x400)
 279
 280 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 281    is omitted, then for the next operand use this operand value plus
 282    1, ignoring the next operand field for the opcode.  This wretched
 283    hack is needed because the Power rotate instructions can take
 284    either 4 or 5 operands.  The disassembler should print this operand
 285    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 286 #define PPC_OPERAND_NEXT (0x800)
 287
 288 /* This operand should be regarded as a negative number for the
 289    purposes of overflow checking (i.e., the normal most negative
 290    number is disallowed and one more than the normal most positive
 291    number is allowed).  This flag will only be set for a signed
 292    operand.  */
 293 #define PPC_OPERAND_NEGATIVE (0x1000)
 294
 295 /* This operand names a vector unit register.  The disassembler
 296    prints these with a leading 'v'.  */
 297 #define PPC_OPERAND_VR (0x2000)
 298
 299 /* This operand is for the DS field in a DS form instruction.  */
 300 #define PPC_OPERAND_DS (0x4000)
 301
 302 /* This operand is for the DQ field in a DQ form instruction.  */
 303 #define PPC_OPERAND_DQ (0x8000)
 304
 305 /* Valid range of operand is 0..n rather than 0..n-1.  */
 306 #define PPC_OPERAND_PLUS1 (0x10000)
 307 \f
 308 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 309    with the operands table for simplicity.  The macro table is an
 310    array of struct powerpc_macro.  */
 311
 312 struct powerpc_macro
 313 {
 314   /* The macro name.  */
 315   const char *name;
 316
 317   /* The number of operands the macro takes.  */
 318   unsigned int operands;
 319
 320   /* One bit flags for the opcode.  These are used to indicate which
 321      specific processors support the instructions.  The values are the
 322      same as those for the struct powerpc_opcode flags field.  */
 323   ppc_cpu_t flags;
 324
 325   /* A format string to turn the macro into a normal instruction.
 326      Each %N in the string is replaced with operand number N (zero
 327      based).  */
 328   const char *format;
 329 };
 330
 331 extern const struct powerpc_macro powerpc_macros[];
 332 extern const int powerpc_num_macros;
 333
 334 #endif /* PPC_H */