include/opcode/sparc.h

   1 /* Definitions for opcode table for the sparc.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
   3    2003, 2005, 2010, 2011 Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   6    the GNU Binutils.
   7
   8    GAS/GDB is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    GAS/GDB is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS or GDB; see the file COPYING3.  If not, write to
  20    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
  21    Boston, MA 02110-1301, USA.  */
  22
  23 #include "ansidecl.h"
  24
  25 /* The SPARC opcode table (and other related data) is defined in
  26    the opcodes library in sparc-opc.c.  If you change anything here, make
  27    sure you fix up that file, and vice versa.  */
  28
  29  /* FIXME-someday: perhaps the ,a's and such should be embedded in the
  30     instruction's name rather than the args.  This would make gas faster, pinsn
  31     slower, but would mess up some macros a bit.  xoxorich. */
  32
  33 /* List of instruction sets variations.
  34    These values are such that each element is either a superset of a
  35    preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
  36    returns non-zero.
  37    The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
  38    Don't change this without updating sparc-opc.c.  */
  39
  40 enum sparc_opcode_arch_val
  41 {
  42   SPARC_OPCODE_ARCH_V6 = 0,
  43   SPARC_OPCODE_ARCH_V7,
  44   SPARC_OPCODE_ARCH_V8,
  45   SPARC_OPCODE_ARCH_SPARCLET,
  46   SPARC_OPCODE_ARCH_SPARCLITE,
  47   /* V9 variants must appear last.  */
  48   SPARC_OPCODE_ARCH_V9,
  49   SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */
  50   SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */
  51   SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
  52 };
  53
  54 /* The highest architecture in the table.  */
  55 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
  56
  57 /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
  58    insn encoding/decoding.  */
  59 #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
  60
  61 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
  62 #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
  63
  64 /* Table of cpu variants.  */
  65
  66 typedef struct sparc_opcode_arch
  67 {
  68   const char *name;
  69   /* Mask of sparc_opcode_arch_val's supported.
  70      EG: For v7 this would be
  71      (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
  72      These are short's because sparc_opcode.architecture is.  */
  73   short supported;
  74 } sparc_opcode_arch;
  75
  76 extern const struct sparc_opcode_arch sparc_opcode_archs[];
  77
  78 /* Given architecture name, look up it's sparc_opcode_arch_val value.  */
  79 extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
  80
  81 /* Return the bitmask of supported architectures for ARCH.  */
  82 #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
  83
  84 /* Non-zero if ARCH1 conflicts with ARCH2.
  85    IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
  86 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
  87  (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
  88    != SPARC_OPCODE_SUPPORTED (ARCH1)) \
  89   && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
  90      != SPARC_OPCODE_SUPPORTED (ARCH2)))
  91
  92 /* Structure of an opcode table entry.  */
  93
  94 typedef struct sparc_opcode
  95 {
  96   const char *name;
  97   unsigned long match;  /* Bits that must be set.  */
  98   unsigned long lose;   /* Bits that must not be set.  */
  99   const char *args;
 100   /* This was called "delayed" in versions before the flags.  */
 101   unsigned int flags;
 102   unsigned int hwcaps;
 103   short architecture;   /* Bitmask of sparc_opcode_arch_val's.  */
 104 } sparc_opcode;
 105
 106 /* FIXME: Add F_ANACHRONISTIC flag for v9.  */
 107 #define F_DELAYED       0x00000001 /* Delayed branch.  */
 108 #define F_ALIAS         0x00000002 /* Alias for a "real" instruction.  */
 109 #define F_UNBR          0x00000004 /* Unconditional branch.  */
 110 #define F_CONDBR        0x00000008 /* Conditional branch.  */
 111 #define F_JSR           0x00000010 /* Subroutine call.  */
 112 #define F_FLOAT         0x00000020 /* Floating point instruction (not a branch).  */
 113 #define F_FBR           0x00000040 /* Floating point branch.  */
 114
 115 /* These must match the HWCAP_* values precisely.  */
 116 #define HWCAP_MUL32     0x00000001 /* umul/umulcc/smul/smulcc insns */
 117 #define HWCAP_DIV32     0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
 118 #define HWCAP_FSMULD    0x00000004 /* 'fsmuld' insn */
 119 #define HWCAP_V8PLUS    0x00000008 /* v9 insns available to 32bit */
 120 #define HWCAP_POPC      0x00000010 /* 'popc' insn */
 121 #define HWCAP_VIS       0x00000020 /* VIS insns */
 122 #define HWCAP_VIS2      0x00000040 /* VIS2 insns */
 123 #define HWCAP_ASI_BLK_INIT      \
 124                         0x00000080 /* block init ASIs */
 125 #define HWCAP_FMAF      0x00000100 /* fused multiply-add */
 126 #define HWCAP_VIS3      0x00000400 /* VIS3 insns */
 127 #define HWCAP_HPC       0x00000800 /* HPC insns */
 128 #define HWCAP_RANDOM    0x00001000 /* 'random' insn */
 129 #define HWCAP_TRANS     0x00002000 /* transaction insns */
 130 #define HWCAP_FJFMAU    0x00004000 /* unfused multiply-add */
 131 #define HWCAP_IMA       0x00008000 /* integer multiply-add */
 132 #define HWCAP_ASI_CACHE_SPARING \
 133                         0x00010000 /* cache sparing ASIs */
 134 #define HWCAP_AES       0x00020000 /* AES crypto insns */
 135 #define HWCAP_DES       0x00040000 /* DES crypto insns */
 136 #define HWCAP_KASUMI    0x00080000 /* KASUMI crypto insns */
 137 #define HWCAP_CAMELLIA  0x00100000 /* CAMELLIA crypto insns */
 138 #define HWCAP_MD5       0x00200000 /* MD5 hashing insns */
 139 #define HWCAP_SHA1      0x00400000 /* SHA1 hashing insns */
 140 #define HWCAP_SHA256    0x00800000 /* SHA256 hashing insns */
 141 #define HWCAP_SHA512    0x01000000 /* SHA512 hashing insns */
 142 #define HWCAP_MPMUL     0x02000000 /* Multiple Precision Multiply */
 143 #define HWCAP_MONT      0x04000000 /* Montgomery Mult/Sqrt */
 144 #define HWCAP_PAUSE     0x08000000 /* Pause insn */
 145 #define HWCAP_CBCOND    0x10000000 /* Compare and Branch insns */
 146 #define HWCAP_CRC32C    0x20000000 /* CRC32C insn */
 147
 148 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
 149    macro), which is 64 bits. It is handled as a special case.
 150
 151    The match component is a mask saying which bits must match a particular
 152    opcode in order for an instruction to be an instance of that opcode.
 153
 154    The args component is a string containing one character for each operand of the
 155    instruction.
 156
 157    Kinds of operands:
 158         #       Number used by optimizer.       It is ignored.
 159         1       rs1 register.
 160         2       rs2 register.
 161         d       rd register.
 162         e       frs1 floating point register.
 163         v       frs1 floating point register (double/even).
 164         V       frs1 floating point register (quad/multiple of 4).
 165         f       frs2 floating point register.
 166         B       frs2 floating point register (double/even).
 167         R       frs2 floating point register (quad/multiple of 4).
 168         4       frs3 floating point register.
 169         5       frs3 floating point register (doube/even).
 170         g       frsd floating point register.
 171         H       frsd floating point register (double/even).
 172         J       frsd floating point register (quad/multiple of 4).
 173         b       crs1 coprocessor register
 174         c       crs2 coprocessor register
 175         D       crsd coprocessor register
 176         m       alternate space register (asr) in rd
 177         M       alternate space register (asr) in rs1
 178         h       22 high bits.
 179         X       5 bit unsigned immediate
 180         Y       6 bit unsigned immediate
 181         3       SIAM mode (3 bits). (v9b)
 182         K       MEMBAR mask (7 bits). (v9)
 183         j       10 bit Immediate. (v9)
 184         I       11 bit Immediate. (v9)
 185         i       13 bit Immediate.
 186         n       22 bit immediate.
 187         k       2+14 bit PC relative immediate. (v9)
 188         G       19 bit PC relative immediate. (v9)
 189         l       22 bit PC relative immediate.
 190         L       30 bit PC relative immediate.
 191         a       Annul.  The annul bit is set.
 192         A       Alternate address space. Stored as 8 bits.
 193         C       Coprocessor state register.
 194         F       floating point state register.
 195         p       Processor state register.
 196         N       Branch predict clear ",pn" (v9)
 197         T       Branch predict set ",pt" (v9)
 198         z       %icc. (v9)
 199         Z       %xcc. (v9)
 200         q       Floating point queue.
 201         r       Single register that is both rs1 and rd.
 202         O       Single register that is both rs2 and rd.
 203         Q       Coprocessor queue.
 204         S       Special case.
 205         t       Trap base register.
 206         w       Window invalid mask register.
 207         y       Y register.
 208         u       sparclet coprocessor registers in rd position
 209         U       sparclet coprocessor registers in rs1 position
 210         E       %ccr. (v9)
 211         s       %fprs. (v9)
 212         P       %pc.  (v9)
 213         W       %tick.  (v9)
 214         o       %asi. (v9)
 215         6       %fcc0. (v9)
 216         7       %fcc1. (v9)
 217         8       %fcc2. (v9)
 218         9       %fcc3. (v9)
 219         !       Privileged Register in rd (v9)
 220         ?       Privileged Register in rs1 (v9)
 221         *       Prefetch function constant. (v9)
 222         x       OPF field (v9 impdep).
 223         0       32/64 bit immediate for set or setx (v9) insns
 224         _       Ancillary state register in rd (v9a)
 225         /       Ancillary state register in rs1 (v9a)
 226         (       entire floating point state register (%efsr)
 227         )       5 bit immediate placed in RS3 field
 228         =       2+8 bit PC relative immediate. (v9)  */
 229
 230 #define OP2(x)          (((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
 231 #define OP3(x)          (((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
 232 #define OP(x)           ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
 233 #define OPF(x)          (((x) & 0x1ff) << 5) /* Opf field of float insns.  */
 234 #define OPF_LOW5(x)     OPF ((x) & 0x1f)     /* V9.  */
 235 #define OPF_LOW4(x)     OPF ((x) & 0xf)      /* V9.  */
 236 #define F3F(x, y, z)    (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
 237 #define F3I(x)          (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
 238 #define F2(x, y)        (OP (x) | OP2(y))    /* Format 2 insns.  */
 239 #define F3(x, y, z)     (OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */
 240 #define F1(x)           (OP (x))
 241 #define DISP30(x)       ((x) & 0x3fffffff)
 242 #define ASI(x)          (((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
 243 #define RS2(x)          ((x) & 0x1f)         /* Rs2 field.  */
 244 #define SIMM13(x)       ((x) & 0x1fff)       /* Simm13 field.  */
 245 #define RD(x)           (((x) & 0x1f) << 25) /* Destination register field.  */
 246 #define RS1(x)          (((x) & 0x1f) << 14) /* Rs1 field.  */
 247 #define RS3(x)          (((x) & 0x1f) << 9)  /* Rs3 field.  */
 248 #define ASI_RS2(x)      (SIMM13 (x))
 249 #define MEMBAR(x)       ((x) & 0x7f)
 250 #define SLCPOP(x)       (((x) & 0x7f) << 6)  /* Sparclet cpop.  */
 251
 252 #define ANNUL   (1 << 29)
 253 #define BPRED   (1 << 19)       /* V9.  */
 254 #define IMMED   F3I (1)
 255 #define RD_G0   RD (~0)
 256 #define RS1_G0  RS1 (~0)
 257 #define RS2_G0  RS2 (~0)
 258
 259 extern const struct sparc_opcode sparc_opcodes[];
 260 extern const int sparc_num_opcodes;
 261
 262 extern int sparc_encode_asi (const char *);
 263 extern const char *sparc_decode_asi (int);
 264 extern int sparc_encode_membar (const char *);
 265 extern const char *sparc_decode_membar (int);
 266 extern int sparc_encode_prefetch (const char *);
 267 extern const char *sparc_decode_prefetch (int);
 268 extern int sparc_encode_sparclet_cpreg (const char *);
 269 extern const char *sparc_decode_sparclet_cpreg (int);
 270
 271 /* Local Variables:
 272    fill-column: 131
 273    comment-column: 0
 274    End: */
 275