* tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot
[deliverable/binutils-gdb.git] / include / opcode / tic80.h
1 /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
2 Copyright 1996, 1997 Free Software Foundation, Inc.
3 Written by Fred Fish (fnf@cygnus.com), Cygnus Support
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 1, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 #ifndef TIC80_H
22 #define TIC80_H
23
24 /* The opcode table is an array of struct tic80_opcode. */
25
26 struct tic80_opcode
27 {
28 /* The opcode name. */
29
30 const char *name;
31
32 /* The opcode itself. Those bits which will be filled in with operands
33 are zeroes. */
34
35 unsigned long opcode;
36
37 /* The opcode mask. This is used by the disassembler. This is a mask
38 containing ones indicating those bits which must match the opcode
39 field, and zeroes indicating those bits which need not match (and are
40 presumably filled in by operands). */
41
42 unsigned long mask;
43
44 /* Special purpose flags for this opcode. */
45
46 unsigned char flags;
47
48 /* An array of operand codes. Each code is an index into the operand
49 table. They appear in the order which the operands must appear in
50 assembly code, and are terminated by a zero. FIXME: Adjust size to
51 match actual requirements when TIc80 support is complete */
52
53 unsigned char operands[8];
54 };
55
56 /* The table itself is sorted by major opcode number, and is otherwise in
57 the order in which the disassembler should consider instructions.
58 FIXME: This isn't currently true. */
59
60 extern const struct tic80_opcode tic80_opcodes[];
61 extern const int tic80_num_opcodes;
62
63 \f
64 /* The operands table is an array of struct tic80_operand. */
65
66 struct tic80_operand
67 {
68 /* The number of bits in the operand. */
69
70 int bits;
71
72 /* How far the operand is left shifted in the instruction. */
73
74 int shift;
75
76 /* Insertion function. This is used by the assembler. To insert an
77 operand value into an instruction, check this field.
78
79 If it is NULL, execute
80 i |= (op & ((1 << o->bits) - 1)) << o->shift;
81 (i is the instruction which we are filling in, o is a pointer to
82 this structure, and op is the opcode value; this assumes twos
83 complement arithmetic).
84
85 If this field is not NULL, then simply call it with the
86 instruction and the operand value. It will return the new value
87 of the instruction. If the ERRMSG argument is not NULL, then if
88 the operand value is illegal, *ERRMSG will be set to a warning
89 string (the operand will be inserted in any case). If the
90 operand value is legal, *ERRMSG will be unchanged (most operands
91 can accept any value). */
92
93 unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
94 const char **errmsg));
95
96 /* Extraction function. This is used by the disassembler. To
97 extract this operand type from an instruction, check this field.
98
99 If it is NULL, compute
100 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
101 if ((o->flags & PPC_OPERAND_SIGNED) != 0
102 && (op & (1 << (o->bits - 1))) != 0)
103 op -= 1 << o->bits;
104 (i is the instruction, o is a pointer to this structure, and op
105 is the result; this assumes twos complement arithmetic).
106
107 If this field is not NULL, then simply call it with the
108 instruction value. It will return the value of the operand. If
109 the INVALID argument is not NULL, *INVALID will be set to
110 non-zero if this operand type can not actually be extracted from
111 this operand (i.e., the instruction does not match). If the
112 operand is valid, *INVALID will not be changed. */
113
114 long (*extract) PARAMS ((unsigned long instruction, int *invalid));
115
116 /* One bit syntax flags. */
117
118 unsigned long flags;
119 };
120
121 /* Elements in the table are retrieved by indexing with values from
122 the operands field of the tic80_opcodes table. */
123
124 extern const struct tic80_operand tic80_operands[];
125
126 /* Values defined for the flags field of a struct tic80_operand. */
127
128 /* This operand takes signed values. */
129 #define TIC80_OPERAND_SIGNED (01)
130
131 /* The next operand should be wrapped in parentheses rather than separated
132 from this one by a comma. This is used for various instructions, like
133 the load and store instructions, which want their operands to look like
134 "displacement(reg)" */
135 #define TIC80_OPERAND_PARENS (02)
136
137 /* This operand is a bit number and may use symbolic names such as "eq.b",
138 "or.f", etc. */
139 #define TIC80_OPERAND_BITNUM (04)
140
141 /* This operand names a register. The disassembler uses this to print
142 register names with a leading 'r'. */
143 #define TIC80_OPERAND_GPR (010)
144
145 /* This operand names a floating point accumulator register. The disassembler
146 prints these with a leading 'a'. */
147 #define TIC80_OPERAND_FPA (020)
148
149 /* This operand is a PC relative branch offset. The disassembler prints
150 these symbolically if possible. Note that the offsets are taken as word
151 offsets. */
152 #define TIC80_OPERAND_PCREL (040)
153
154 /* This flag is a hint to the disassembler for using hex as the prefered
155 printing format, even for small positive or negative immediate values.
156 Normally values in the range -999 to 999 are printed as signed decimal
157 values and other values are printed in hex. */
158 #define TIC80_OPERAND_BITFIELD (0100)
159
160 /* This operand is a condition code, which may be given symbolically as
161 "eq0.b", "ne0.w", etc. */
162 #define TIC80_OPERAND_CC (0200)
163
164 /* This operand is a control register number, or may also be given
165 symbolically as "EIP", "EPC", etc. */
166 #define TIC80_OPERAND_CR (0400)
167
168 /* This operand may have a ":m" modifier specified by bit 17 in a short
169 immediate form instruction. */
170 #define TIC80_OPERAND_M_SI (01000)
171
172 /* This operand may have a ":m" modifier specified by bit 15 in a long
173 immediate or register form instruction. */
174 #define TIC80_OPERAND_M_LI (02000)
175
176 /* This operand may have a ":s" modifier specified in bit 11 in a long
177 immediate or register form instruction. */
178 #define TIC80_OPERAND_SCALED (04000)
179
180 /* This operand is a floating point value */
181 #define TIC80_OPERAND_FLOAT (010000)
182
183 /* This operand is an byte offset from a base relocation. The lower
184 two bits of the final relocated address are ignored when the value is
185 written to the program counter. */
186 #define TIC80_OPERAND_BASEREL (020000)
187
188 /* Flag bits for the struct tic80_opcode flags field. */
189
190 #define TIC80_VECTOR 01 /* Is a vector instruction */
191 #define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */
192
193 #endif /* TIC80_H */
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