include/uapi/rdma/hfi/hfi1_user.h

   1 /*
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2015 Intel Corporation.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * BSD LICENSE
  20  *
  21  * Copyright(c) 2015 Intel Corporation.
  22  *
  23  * Redistribution and use in source and binary forms, with or without
  24  * modification, are permitted provided that the following conditions
  25  * are met:
  26  *
  27  *  - Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions and the following disclaimer.
  29  *  - Redistributions in binary form must reproduce the above copyright
  30  *    notice, this list of conditions and the following disclaimer in
  31  *    the documentation and/or other materials provided with the
  32  *    distribution.
  33  *  - Neither the name of Intel Corporation nor the names of its
  34  *    contributors may be used to endorse or promote products derived
  35  *    from this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  */
  50
  51 /*
  52  * This file contains defines, structures, etc. that are used
  53  * to communicate between kernel and user code.
  54  */
  55
  56 #ifndef _LINUX__HFI1_USER_H
  57 #define _LINUX__HFI1_USER_H
  58
  59 #include <linux/types.h>
  60
  61 /*
  62  * This version number is given to the driver by the user code during
  63  * initialization in the spu_userversion field of hfi1_user_info, so
  64  * the driver can check for compatibility with user code.
  65  *
  66  * The major version changes when data structures change in an incompatible
  67  * way. The driver must be the same for initialization to succeed.
  68  */
  69 #define HFI1_USER_SWMAJOR 4
  70
  71 /*
  72  * Minor version differences are always compatible
  73  * a within a major version, however if user software is larger
  74  * than driver software, some new features and/or structure fields
  75  * may not be implemented; the user code must deal with this if it
  76  * cares, or it must abort after initialization reports the difference.
  77  */
  78 #define HFI1_USER_SWMINOR 0
  79
  80 /*
  81  * Set of HW and driver capability/feature bits.
  82  * These bit values are used to configure enabled/disabled HW and
  83  * driver features. The same set of bits are communicated to user
  84  * space.
  85  */
  86 #define HFI1_CAP_DMA_RTAIL        (1UL <<  0) /* Use DMA'ed RTail value */
  87 #define HFI1_CAP_SDMA             (1UL <<  1) /* Enable SDMA support */
  88 #define HFI1_CAP_SDMA_AHG         (1UL <<  2) /* Enable SDMA AHG support */
  89 #define HFI1_CAP_EXTENDED_PSN     (1UL <<  3) /* Enable Extended PSN support */
  90 #define HFI1_CAP_HDRSUPP          (1UL <<  4) /* Enable Header Suppression */
  91 /* 1UL << 5 unused */
  92 #define HFI1_CAP_USE_SDMA_HEAD    (1UL <<  6) /* DMA Hdr Q tail vs. use CSR */
  93 #define HFI1_CAP_MULTI_PKT_EGR    (1UL <<  7) /* Enable multi-packet Egr buffs*/
  94 #define HFI1_CAP_NODROP_RHQ_FULL  (1UL <<  8) /* Don't drop on Hdr Q full */
  95 #define HFI1_CAP_NODROP_EGR_FULL  (1UL <<  9) /* Don't drop on EGR buffs full */
  96 #define HFI1_CAP_TID_UNMAP        (1UL << 10) /* Enable Expected TID caching */
  97 #define HFI1_CAP_PRINT_UNIMPL     (1UL << 11) /* Show for unimplemented feats */
  98 #define HFI1_CAP_ALLOW_PERM_JKEY  (1UL << 12) /* Allow use of permissive JKEY */
  99 #define HFI1_CAP_NO_INTEGRITY     (1UL << 13) /* Enable ctxt integrity checks */
 100 #define HFI1_CAP_PKEY_CHECK       (1UL << 14) /* Enable ctxt PKey checking */
 101 #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */
 102 /* 1UL << 16 unused */
 103 #define HFI1_CAP_SDMA_HEAD_CHECK  (1UL << 17) /* SDMA head checking */
 104 #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */
 105
 106 #define HFI1_RCVHDR_ENTSIZE_2    (1UL << 0)
 107 #define HFI1_RCVHDR_ENTSIZE_16   (1UL << 1)
 108 #define HFI1_RCVDHR_ENTSIZE_32   (1UL << 2)
 109
 110 /*
 111  * If the unit is specified via open, HFI choice is fixed.  If port is
 112  * specified, it's also fixed.  Otherwise we try to spread contexts
 113  * across ports and HFIs, using different algorithms.  WITHIN is
 114  * the old default, prior to this mechanism.
 115  */
 116 #define HFI1_ALG_ACROSS 0 /* round robin contexts across HFIs, then
 117                           * ports; this is the default */
 118 #define HFI1_ALG_WITHIN 1 /* use all contexts on an HFI (round robin
 119                           * active ports within), then next HFI */
 120 #define HFI1_ALG_COUNT  2 /* number of algorithm choices */
 121
 122
 123 /* User commands. */
 124 #define HFI1_CMD_ASSIGN_CTXT     1      /* allocate HFI and context */
 125 #define HFI1_CMD_CTXT_INFO       2      /* find out what resources we got */
 126 #define HFI1_CMD_USER_INFO       3      /* set up userspace */
 127 #define HFI1_CMD_TID_UPDATE      4      /* update expected TID entries */
 128 #define HFI1_CMD_TID_FREE        5      /* free expected TID entries */
 129 #define HFI1_CMD_CREDIT_UPD      6      /* force an update of PIO credit */
 130 #define HFI1_CMD_SDMA_STATUS_UPD 7      /* force update of SDMA status ring */
 131
 132 #define HFI1_CMD_RECV_CTRL       8      /* control receipt of packets */
 133 #define HFI1_CMD_POLL_TYPE       9      /* set the kind of polling we want */
 134 #define HFI1_CMD_ACK_EVENT       10     /* ack & clear user status bits */
 135 #define HFI1_CMD_SET_PKEY        11     /* set context's pkey */
 136 #define HFI1_CMD_CTXT_RESET      12     /* reset context's HW send context */
 137 /* separate EPROM commands from normal PSM commands */
 138 #define HFI1_CMD_EP_INFO         64      /* read EPROM device ID */
 139 #define HFI1_CMD_EP_ERASE_CHIP   65      /* erase whole EPROM */
 140 /* range 66-74 no longer used */
 141 #define HFI1_CMD_EP_ERASE_RANGE  75      /* erase EPROM range */
 142 #define HFI1_CMD_EP_READ_RANGE   76      /* read EPROM range */
 143 #define HFI1_CMD_EP_WRITE_RANGE  77      /* write EPROM range */
 144
 145 #define _HFI1_EVENT_FROZEN_BIT         0
 146 #define _HFI1_EVENT_LINKDOWN_BIT       1
 147 #define _HFI1_EVENT_LID_CHANGE_BIT     2
 148 #define _HFI1_EVENT_LMC_CHANGE_BIT     3
 149 #define _HFI1_EVENT_SL2VL_CHANGE_BIT   4
 150 #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_SL2VL_CHANGE_BIT
 151
 152 #define HFI1_EVENT_FROZEN            (1UL << _HFI1_EVENT_FROZEN_BIT)
 153 #define HFI1_EVENT_LINKDOWN          (1UL << _HFI1_EVENT_LINKDOWN_BIT)
 154 #define HFI1_EVENT_LID_CHANGE        (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
 155 #define HFI1_EVENT_LMC_CHANGE        (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
 156 #define HFI1_EVENT_SL2VL_CHANGE      (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
 157
 158 /*
 159  * These are the status bits readable (in ASCII form, 64bit value)
 160  * from the "status" sysfs file.  For binary compatibility, values
 161  * must remain as is; removed states can be reused for different
 162  * purposes.
 163  */
 164 #define HFI1_STATUS_INITTED       0x1    /* basic initialization done */
 165 /* Chip has been found and initialized */
 166 #define HFI1_STATUS_CHIP_PRESENT 0x20
 167 /* IB link is at ACTIVE, usable for data traffic */
 168 #define HFI1_STATUS_IB_READY     0x40
 169 /* link is configured, LID, MTU, etc. have been set */
 170 #define HFI1_STATUS_IB_CONF      0x80
 171 /* A Fatal hardware error has occurred. */
 172 #define HFI1_STATUS_HWERROR     0x200
 173
 174 /*
 175  * Number of supported shared contexts.
 176  * This is the maximum number of software contexts that can share
 177  * a hardware send/receive context.
 178  */
 179 #define HFI1_MAX_SHARED_CTXTS 8
 180
 181 /*
 182  * Poll types
 183  */
 184 #define HFI1_POLL_TYPE_ANYRCV     0x0
 185 #define HFI1_POLL_TYPE_URGENT     0x1
 186
 187 /*
 188  * This structure is passed to the driver to tell it where
 189  * user code buffers are, sizes, etc.   The offsets and sizes of the
 190  * fields must remain unchanged, for binary compatibility.  It can
 191  * be extended, if userversion is changed so user code can tell, if needed
 192  */
 193 struct hfi1_user_info {
 194         /*
 195          * version of user software, to detect compatibility issues.
 196          * Should be set to HFI1_USER_SWVERSION.
 197          */
 198         __u32 userversion;
 199         __u16 pad;
 200         /* HFI selection algorithm, if unit has not selected */
 201         __u16 hfi1_alg;
 202         /*
 203          * If two or more processes wish to share a context, each process
 204          * must set the subcontext_cnt and subcontext_id to the same
 205          * values.  The only restriction on the subcontext_id is that
 206          * it be unique for a given node.
 207          */
 208         __u16 subctxt_cnt;
 209         __u16 subctxt_id;
 210         /* 128bit UUID passed in by PSM. */
 211         __u8 uuid[16];
 212 };
 213
 214 struct hfi1_ctxt_info {
 215         __u64 runtime_flags;    /* chip/drv runtime flags (HFI1_CAP_*) */
 216         __u32 rcvegr_size;      /* size of each eager buffer */
 217         __u16 num_active;       /* number of active units */
 218         __u16 unit;             /* unit (chip) assigned to caller */
 219         __u16 ctxt;             /* ctxt on unit assigned to caller */
 220         __u16 subctxt;          /* subctxt on unit assigned to caller */
 221         __u16 rcvtids;          /* number of Rcv TIDs for this context */
 222         __u16 credits;          /* number of PIO credits for this context */
 223         __u16 numa_node;        /* NUMA node of the assigned device */
 224         __u16 rec_cpu;          /* cpu # for affinity (0xffff if none) */
 225         __u16 send_ctxt;        /* send context in use by this user context */
 226         __u16 egrtids;          /* number of RcvArray entries for Eager Rcvs */
 227         __u16 rcvhdrq_cnt;      /* number of RcvHdrQ entries */
 228         __u16 rcvhdrq_entsize;  /* size (in bytes) for each RcvHdrQ entry */
 229         __u16 sdma_ring_size;   /* number of entries in SDMA request ring */
 230 };
 231
 232 struct hfi1_tid_info {
 233         /* virtual address of first page in transfer */
 234         __u64 vaddr;
 235         /* pointer to tid array. this array is big enough */
 236         __u64 tidlist;
 237         /* number of tids programmed by this request */
 238         __u32 tidcnt;
 239         /* length of transfer buffer programmed by this request */
 240         __u32 length;
 241         /*
 242          * pointer to bitmap of TIDs used for this call;
 243          * checked for being large enough at open
 244          */
 245         __u64 tidmap;
 246 };
 247
 248 struct hfi1_cmd {
 249         __u32 type;        /* command type */
 250         __u32 len;         /* length of struct pointed to by add */
 251         __u64 addr;        /* pointer to user structure */
 252 };
 253
 254 enum hfi1_sdma_comp_state {
 255         FREE = 0,
 256         QUEUED,
 257         COMPLETE,
 258         ERROR
 259 };
 260
 261 /*
 262  * SDMA completion ring entry
 263  */
 264 struct hfi1_sdma_comp_entry {
 265         __u32 status;
 266         __u32 errcode;
 267 };
 268
 269 /*
 270  * Device status and notifications from driver to user-space.
 271  */
 272 struct hfi1_status {
 273         __u64 dev;      /* device/hw status bits */
 274         __u64 port;     /* port state and status bits */
 275         char freezemsg[0];
 276 };
 277
 278 /*
 279  * This structure is returned by the driver immediately after
 280  * open to get implementation-specific info, and info specific to this
 281  * instance.
 282  *
 283  * This struct must have explicit pad fields where type sizes
 284  * may result in different alignments between 32 and 64 bit
 285  * programs, since the 64 bit * bit kernel requires the user code
 286  * to have matching offsets
 287  */
 288 struct hfi1_base_info {
 289         /* version of hardware, for feature checking. */
 290         __u32 hw_version;
 291         /* version of software, for feature checking. */
 292         __u32 sw_version;
 293         /* Job key */
 294         __u16 jkey;
 295         __u16 padding1;
 296         /*
 297          * The special QP (queue pair) value that identifies PSM
 298          * protocol packet from standard IB packets.
 299          */
 300         __u32 bthqp;
 301         /* PIO credit return address, */
 302         __u64 sc_credits_addr;
 303         /*
 304          * Base address of write-only pio buffers for this process.
 305          * Each buffer has sendpio_credits*64 bytes.
 306          */
 307         __u64 pio_bufbase_sop;
 308         /*
 309          * Base address of write-only pio buffers for this process.
 310          * Each buffer has sendpio_credits*64 bytes.
 311          */
 312         __u64 pio_bufbase;
 313         /* address where receive buffer queue is mapped into */
 314         __u64 rcvhdr_bufbase;
 315         /* base address of Eager receive buffers. */
 316         __u64 rcvegr_bufbase;
 317         /* base address of SDMA completion ring */
 318         __u64 sdma_comp_bufbase;
 319         /*
 320          * User register base for init code, not to be used directly by
 321          * protocol or applications.  Always maps real chip register space.
 322          * the register addresses are:
 323          * ur_rcvhdrhead, ur_rcvhdrtail, ur_rcvegrhead, ur_rcvegrtail,
 324          * ur_rcvtidflow
 325          */
 326         __u64 user_regbase;
 327         /* notification events */
 328         __u64 events_bufbase;
 329         /* status page */
 330         __u64 status_bufbase;
 331         /* rcvhdrtail update */
 332         __u64 rcvhdrtail_base;
 333         /*
 334          * shared memory pages for subctxts if ctxt is shared; these cover
 335          * all the processes in the group sharing a single context.
 336          * all have enough space for the num_subcontexts value on this job.
 337          */
 338         __u64 subctxt_uregbase;
 339         __u64 subctxt_rcvegrbuf;
 340         __u64 subctxt_rcvhdrbuf;
 341 };
 342
 343 enum sdma_req_opcode {
 344         EXPECTED = 0,
 345         EAGER
 346 };
 347
 348 #define HFI1_SDMA_REQ_VERSION_MASK 0xF
 349 #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0
 350 #define HFI1_SDMA_REQ_OPCODE_MASK 0xF
 351 #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4
 352 #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF
 353 #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8
 354
 355 struct sdma_req_info {
 356         /*
 357          * bits 0-3 - version (currently unused)
 358          * bits 4-7 - opcode (enum sdma_req_opcode)
 359          * bits 8-15 - io vector count
 360          */
 361         __u16 ctrl;
 362         /*
 363          * Number of fragments contained in this request.
 364          * User-space has already computed how many
 365          * fragment-sized packet the user buffer will be
 366          * split into.
 367          */
 368         __u16 npkts;
 369         /*
 370          * Size of each fragment the user buffer will be
 371          * split into.
 372          */
 373         __u16 fragsize;
 374         /*
 375          * Index of the slot in the SDMA completion ring
 376          * this request should be using. User-space is
 377          * in charge of managing its own ring.
 378          */
 379         __u16 comp_idx;
 380 } __packed;
 381
 382 /*
 383  * SW KDETH header.
 384  * swdata is SW defined portion.
 385  */
 386 struct hfi1_kdeth_header {
 387         __le32 ver_tid_offset;
 388         __le16 jkey;
 389         __le16 hcrc;
 390         __le32 swdata[7];
 391 } __packed;
 392
 393 /*
 394  * Structure describing the headers that User space uses. The
 395  * structure above is a subset of this one.
 396  */
 397 struct hfi1_pkt_header {
 398         __le16 pbc[4];
 399         __be16 lrh[4];
 400         __be32 bth[3];
 401         struct hfi1_kdeth_header kdeth;
 402 } __packed;
 403
 404
 405 /*
 406  * The list of usermode accessible registers.
 407  */
 408 enum hfi1_ureg {
 409         /* (RO)  DMA RcvHdr to be used next. */
 410         ur_rcvhdrtail = 0,
 411         /* (RW)  RcvHdr entry to be processed next by host. */
 412         ur_rcvhdrhead = 1,
 413         /* (RO)  Index of next Eager index to use. */
 414         ur_rcvegrindextail = 2,
 415         /* (RW)  Eager TID to be processed next */
 416         ur_rcvegrindexhead = 3,
 417         /* (RO)  Receive Eager Offset Tail */
 418         ur_rcvegroffsettail = 4,
 419         /* For internal use only; max register number. */
 420         ur_maxreg,
 421         /* (RW)  Receive TID flow table */
 422         ur_rcvtidflowtable = 256
 423 };
 424
 425 #endif /* _LINIUX__HFI1_USER_H */